OpenCores
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[/] [rise/] [trunk/] [vhdl/] [idmem.edn] - Blame information for rev 149

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Line No. Rev Author Line
1 25 ustadler
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
2 102 ustadler
(status (written (timeStamp 2007 1 14 14 42 55)
3 25 ustadler
   (author "Xilinx, Inc.")
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   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.1.03i"))))
5
   (comment "
6
      This file is owned and controlled by Xilinx and must be used
7
      solely for design, simulation, implementation and creation of
8
      design files limited to Xilinx devices or technologies. Use
9
      with non-Xilinx devices or technologies is expressly prohibited
10
      and immediately terminates your license.
11
 
12
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
13
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
14
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
15
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
16
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
17
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
18
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
19
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
20
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
21
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
22
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
23
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24
      FOR A PARTICULAR PURPOSE.
25
 
26
      Xilinx products are not intended for use in life support
27
      appliances, devices, or systems. Use in such applications are
28
      expressly prohibited.
29
 
30
      (c) Copyright 1995-2005 Xilinx, Inc.
31
      All rights reserved.
32
 
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   ")
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   (comment "Core parameters: ")
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       (comment "c_sinit_value = 0 ")
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       (comment "c_has_en = 0 ")
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       (comment "c_reg_inputs = 0 ")
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       (comment "c_yclk_is_rising = 1 ")
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       (comment "c_ysinit_is_high = 0 ")
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       (comment "c_ywe_is_high = 1 ")
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       (comment "c_yprimitive_type = 8kx2 ")
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       (comment "c_ytop_addr = 1024 ")
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       (comment "c_yhierarchy = hierarchy1 ")
44 102 ustadler
       (comment "c_has_limit_data_pitch = 1 ")
45 25 ustadler
       (comment "c_has_rdy = 0 ")
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       (comment "c_write_mode = 0 ")
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       (comment "c_width = 16 ")
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       (comment "c_yuse_single_primitive = 0 ")
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       (comment "c_has_nd = 0 ")
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       (comment "c_has_we = 1 ")
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       (comment "c_enable_rlocs = 0 ")
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       (comment "c_has_rfd = 0 ")
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       (comment "c_has_din = 1 ")
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       (comment "c_ybottom_addr = 0 ")
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       (comment "c_pipe_stages = 0 ")
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       (comment "c_yen_is_high = 1 ")
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       (comment "c_family = spartan3 ")
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       (comment "InstanceName = idmem ")
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       (comment "c_depth = 4096 ")
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       (comment "c_has_default_data = 0 ")
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       (comment "c_limit_data_pitch = 18 ")
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       (comment "c_has_sinit = 1 ")
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       (comment "c_mem_init_file = idmem.mif ")
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       (comment "c_yydisable_warnings = 1 ")
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       (comment "c_default_data = 0 ")
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       (comment "c_ymake_bmm = 0 ")
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       (comment "c_addr_width = 12 ")
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   (external xilinxun (edifLevel 0)
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      (technology (numberDefinition))
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       (cell VCC (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port P (direction OUTPUT))
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               )
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           )
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       )
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       (cell GND (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port G (direction OUTPUT))
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               )
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           )
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       )
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       (cell INV (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port I (direction INPUT))
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                   (port O (direction OUTPUT))
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               )
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           )
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       )
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       (cell RAMB16_S4 (cellType GENERIC)
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           (view view_1 (viewType NETLIST)
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               (interface
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                   (port WE (direction INPUT))
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                   (port EN (direction INPUT))
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                   (port SSR (direction INPUT))
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                   (port CLK (direction INPUT))
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                   (port (rename DI_0_ "DI<0>") (direction INPUT))
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                   (port (rename DI_1_ "DI<1>") (direction INPUT))
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                   (port (rename DI_2_ "DI<2>") (direction INPUT))
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                   (port (rename DI_3_ "DI<3>") (direction INPUT))
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                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))
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                   (port (rename DO_1_ "DO<1>") (direction OUTPUT))
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                   (port (rename DO_2_ "DO<2>") (direction OUTPUT))
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                   (port (rename DO_3_ "DO<3>") (direction OUTPUT))
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                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))
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                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))
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                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))
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                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))
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                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))
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                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))
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                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))
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                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))
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                   (port (rename ADDR_8_ "ADDR<8>") (direction INPUT))
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                   (port (rename ADDR_9_ "ADDR<9>") (direction INPUT))
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                   (port (rename ADDR_10_ "ADDR<10>") (direction INPUT))
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                   (port (rename ADDR_11_ "ADDR<11>") (direction INPUT))
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               )
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           )
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       )
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   )
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(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
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(cell idmem
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 (cellType GENERIC) (view view_1 (viewType NETLIST)
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  (interface
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   (port ( array ( rename addr "addr<11:0>") 12 ) (direction INPUT))
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   (port ( rename clk "clk") (direction INPUT))
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   (port ( array ( rename din "din<15:0>") 16 ) (direction INPUT))
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   (port ( rename sinit "sinit") (direction INPUT))
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   (port ( rename we "we") (direction INPUT))
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   (port ( array ( rename dout "dout<15:0>") 16 ) (direction OUTPUT))
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   )
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  (contents
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   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
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   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
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   (instance BU3
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      (viewRef view_1 (cellRef INV (libraryRef xilinxun)))
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   )
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      (property WRITE_MODE (string "WRITE_FIRST"))
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   )
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    )
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   )
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454
    )
455
   )
456
   (net (rename N5 "addr<8>")
457
    (joined
458
      (portRef (member addr 3))
459
      (portRef ADDR_8_ (instanceRef B7))
460
      (portRef ADDR_8_ (instanceRef B11))
461
      (portRef ADDR_8_ (instanceRef B15))
462
      (portRef ADDR_8_ (instanceRef B19))
463
    )
464
   )
465
   (net (rename N6 "addr<7>")
466
    (joined
467
      (portRef (member addr 4))
468
      (portRef ADDR_7_ (instanceRef B7))
469
      (portRef ADDR_7_ (instanceRef B11))
470
      (portRef ADDR_7_ (instanceRef B15))
471
      (portRef ADDR_7_ (instanceRef B19))
472
    )
473
   )
474
   (net (rename N7 "addr<6>")
475
    (joined
476
      (portRef (member addr 5))
477
      (portRef ADDR_6_ (instanceRef B7))
478
      (portRef ADDR_6_ (instanceRef B11))
479
      (portRef ADDR_6_ (instanceRef B15))
480
      (portRef ADDR_6_ (instanceRef B19))
481
    )
482
   )
483
   (net (rename N8 "addr<5>")
484
    (joined
485
      (portRef (member addr 6))
486
      (portRef ADDR_5_ (instanceRef B7))
487
      (portRef ADDR_5_ (instanceRef B11))
488
      (portRef ADDR_5_ (instanceRef B15))
489
      (portRef ADDR_5_ (instanceRef B19))
490
    )
491
   )
492
   (net (rename N9 "addr<4>")
493
    (joined
494
      (portRef (member addr 7))
495
      (portRef ADDR_4_ (instanceRef B7))
496
      (portRef ADDR_4_ (instanceRef B11))
497
      (portRef ADDR_4_ (instanceRef B15))
498
      (portRef ADDR_4_ (instanceRef B19))
499
    )
500
   )
501
   (net (rename N10 "addr<3>")
502
    (joined
503
      (portRef (member addr 8))
504
      (portRef ADDR_3_ (instanceRef B7))
505
      (portRef ADDR_3_ (instanceRef B11))
506
      (portRef ADDR_3_ (instanceRef B15))
507
      (portRef ADDR_3_ (instanceRef B19))
508
    )
509
   )
510
   (net (rename N11 "addr<2>")
511
    (joined
512
      (portRef (member addr 9))
513
      (portRef ADDR_2_ (instanceRef B7))
514
      (portRef ADDR_2_ (instanceRef B11))
515
      (portRef ADDR_2_ (instanceRef B15))
516
      (portRef ADDR_2_ (instanceRef B19))
517
    )
518
   )
519
   (net (rename N12 "addr<1>")
520
    (joined
521
      (portRef (member addr 10))
522
      (portRef ADDR_1_ (instanceRef B7))
523
      (portRef ADDR_1_ (instanceRef B11))
524
      (portRef ADDR_1_ (instanceRef B15))
525
      (portRef ADDR_1_ (instanceRef B19))
526
    )
527
   )
528
   (net (rename N13 "addr<0>")
529
    (joined
530
      (portRef (member addr 11))
531
      (portRef ADDR_0_ (instanceRef B7))
532
      (portRef ADDR_0_ (instanceRef B11))
533
      (portRef ADDR_0_ (instanceRef B15))
534
      (portRef ADDR_0_ (instanceRef B19))
535
    )
536
   )
537
   (net (rename N14 "clk")
538
    (joined
539
      (portRef clk)
540
      (portRef CLK (instanceRef B7))
541
      (portRef CLK (instanceRef B11))
542
      (portRef CLK (instanceRef B15))
543
      (portRef CLK (instanceRef B19))
544
    )
545
   )
546
   (net (rename N15 "din<15>")
547
    (joined
548
      (portRef (member din 0))
549
      (portRef DI_3_ (instanceRef B19))
550
    )
551
   )
552
   (net (rename N16 "din<14>")
553
    (joined
554
      (portRef (member din 1))
555
      (portRef DI_2_ (instanceRef B19))
556
    )
557
   )
558
   (net (rename N17 "din<13>")
559
    (joined
560
      (portRef (member din 2))
561
      (portRef DI_1_ (instanceRef B19))
562
    )
563
   )
564
   (net (rename N18 "din<12>")
565
    (joined
566
      (portRef (member din 3))
567
      (portRef DI_0_ (instanceRef B19))
568
    )
569
   )
570
   (net (rename N19 "din<11>")
571
    (joined
572
      (portRef (member din 4))
573
      (portRef DI_3_ (instanceRef B15))
574
    )
575
   )
576
   (net (rename N20 "din<10>")
577
    (joined
578
      (portRef (member din 5))
579
      (portRef DI_2_ (instanceRef B15))
580
    )
581
   )
582
   (net (rename N21 "din<9>")
583
    (joined
584
      (portRef (member din 6))
585
      (portRef DI_1_ (instanceRef B15))
586
    )
587
   )
588
   (net (rename N22 "din<8>")
589
    (joined
590
      (portRef (member din 7))
591
      (portRef DI_0_ (instanceRef B15))
592
    )
593
   )
594
   (net (rename N23 "din<7>")
595
    (joined
596
      (portRef (member din 8))
597
      (portRef DI_3_ (instanceRef B11))
598
    )
599
   )
600
   (net (rename N24 "din<6>")
601
    (joined
602
      (portRef (member din 9))
603
      (portRef DI_2_ (instanceRef B11))
604
    )
605
   )
606
   (net (rename N25 "din<5>")
607
    (joined
608
      (portRef (member din 10))
609
      (portRef DI_1_ (instanceRef B11))
610
    )
611
   )
612
   (net (rename N26 "din<4>")
613
    (joined
614
      (portRef (member din 11))
615
      (portRef DI_0_ (instanceRef B11))
616
    )
617
   )
618
   (net (rename N27 "din<3>")
619
    (joined
620
      (portRef (member din 12))
621
      (portRef DI_3_ (instanceRef B7))
622
    )
623
   )
624
   (net (rename N28 "din<2>")
625
    (joined
626
      (portRef (member din 13))
627
      (portRef DI_2_ (instanceRef B7))
628
    )
629
   )
630
   (net (rename N29 "din<1>")
631
    (joined
632
      (portRef (member din 14))
633
      (portRef DI_1_ (instanceRef B7))
634
    )
635
   )
636
   (net (rename N30 "din<0>")
637
    (joined
638
      (portRef (member din 15))
639
      (portRef DI_0_ (instanceRef B7))
640
    )
641
   )
642
   (net (rename N31 "dout<15>")
643
    (joined
644
      (portRef (member dout 0))
645
      (portRef DO_3_ (instanceRef B19))
646
    )
647
   )
648
   (net (rename N32 "dout<14>")
649
    (joined
650
      (portRef (member dout 1))
651
      (portRef DO_2_ (instanceRef B19))
652
    )
653
   )
654
   (net (rename N33 "dout<13>")
655
    (joined
656
      (portRef (member dout 2))
657
      (portRef DO_1_ (instanceRef B19))
658
    )
659
   )
660
   (net (rename N34 "dout<12>")
661
    (joined
662
      (portRef (member dout 3))
663
      (portRef DO_0_ (instanceRef B19))
664
    )
665
   )
666
   (net (rename N35 "dout<11>")
667
    (joined
668
      (portRef (member dout 4))
669
      (portRef DO_3_ (instanceRef B15))
670
    )
671
   )
672
   (net (rename N36 "dout<10>")
673
    (joined
674
      (portRef (member dout 5))
675
      (portRef DO_2_ (instanceRef B15))
676
    )
677
   )
678
   (net (rename N37 "dout<9>")
679
    (joined
680
      (portRef (member dout 6))
681
      (portRef DO_1_ (instanceRef B15))
682
    )
683
   )
684
   (net (rename N38 "dout<8>")
685
    (joined
686
      (portRef (member dout 7))
687
      (portRef DO_0_ (instanceRef B15))
688
    )
689
   )
690
   (net (rename N39 "dout<7>")
691
    (joined
692
      (portRef (member dout 8))
693
      (portRef DO_3_ (instanceRef B11))
694
    )
695
   )
696
   (net (rename N40 "dout<6>")
697
    (joined
698
      (portRef (member dout 9))
699
      (portRef DO_2_ (instanceRef B11))
700
    )
701
   )
702
   (net (rename N41 "dout<5>")
703
    (joined
704
      (portRef (member dout 10))
705
      (portRef DO_1_ (instanceRef B11))
706
    )
707
   )
708
   (net (rename N42 "dout<4>")
709
    (joined
710
      (portRef (member dout 11))
711
      (portRef DO_0_ (instanceRef B11))
712
    )
713
   )
714
   (net (rename N43 "dout<3>")
715
    (joined
716
      (portRef (member dout 12))
717
      (portRef DO_3_ (instanceRef B7))
718
    )
719
   )
720
   (net (rename N44 "dout<2>")
721
    (joined
722
      (portRef (member dout 13))
723
      (portRef DO_2_ (instanceRef B7))
724
    )
725
   )
726
   (net (rename N45 "dout<1>")
727
    (joined
728
      (portRef (member dout 14))
729
      (portRef DO_1_ (instanceRef B7))
730
    )
731
   )
732
   (net (rename N46 "dout<0>")
733
    (joined
734
      (portRef (member dout 15))
735
      (portRef DO_0_ (instanceRef B7))
736
    )
737
   )
738
   (net (rename N51 "sinit")
739
    (joined
740
      (portRef sinit)
741
      (portRef I (instanceRef BU3))
742
    )
743
   )
744
   (net (rename N52 "we")
745
    (joined
746
      (portRef we)
747
      (portRef WE (instanceRef B7))
748
      (portRef WE (instanceRef B11))
749
      (portRef WE (instanceRef B15))
750
      (portRef WE (instanceRef B19))
751
    )
752
   )
753
   (net N84
754
    (joined
755
      (portRef O (instanceRef BU3))
756
      (portRef SSR (instanceRef B7))
757
      (portRef SSR (instanceRef B11))
758
      (portRef SSR (instanceRef B15))
759
      (portRef SSR (instanceRef B19))
760
    )
761
   )
762
))))
763
(design idmem (cellRef idmem (libraryRef test_lib))
764
  (property X_CORE_INFO (string "blkmemsp_v6_2, Coregen 8.1.03i"))
765
  (property PART (string "xc3s200-ft256-5") (owner "Xilinx")))
766
)

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