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[/] [rise/] [trunk/] [vhdl/] [register_file.vhd] - Blame information for rev 148

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1 2 jlechner 
-- File: register_file.vhd
2 
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
3 
-- Created: 2006-11-29
4 
-- Last updated: 2006-11-29
5 
 
6 
-- Description:
7 
-- Entity implementing register file.
8 
-------------------------------------------------------------------------------
9 
 
10 
library IEEE;
11 
use IEEE.STD_LOGIC_1164.all;
12 49 ustadler 
use IEEE.STD_LOGIC_ARITH.all;
13 
 
14 2 jlechner 
use WORK.RISE_PACK.all;
15 71 jlechner 
use work.RISE_PACK_SPECIFIC.all;
16 2 jlechner 
 
17 
entity register_file is
18 
 
19 
  port (
20 57 cwalter 
    clk   : in std_logic;
21 
    reset : in std_logic;
22 2 jlechner 
 
23 57 cwalter 
    rx_addr : in REGISTER_ADDR_T;
24 
    ry_addr : in REGISTER_ADDR_T;
25 
    rz_addr : in REGISTER_ADDR_T;
26 2 jlechner 
 
27 57 cwalter 
    rx_read : out REGISTER_T;
28 
    ry_read : out REGISTER_T;
29 
    rz_read : out REGISTER_T;
30 
 
31 
    dreg_addr   : in REGISTER_ADDR_T;
32 
    dreg_write  : in REGISTER_T;
33 
    dreg_enable : in std_logic;
34 
 
35 
    sr_read   : out SR_REGISTER_T;
36 
    sr_write  : in  SR_REGISTER_T;
37 
    sr_enable : in  std_logic;
38 
 
39 
    lr_write  : in PC_REGISTER_T;
40 
    lr_enable : in std_logic;
41 
 
42 
    pc_write : in  PC_REGISTER_T;
43 
    pc_read  : out PC_REGISTER_T);
44 
 
45 49 ustadler 
end register_file;
46 2 jlechner 
 
47 49 ustadler 
architecture register_file_rtl of register_file is
48 57 cwalter 
 
49 
 
50 
  signal reg_0, reg_1, reg_2, reg_3, reg_4              : REGISTER_T;
51 
  signal reg_5, reg_6, reg_7, reg_8, reg_9              : REGISTER_T;
52 
  signal reg_10, reg_11, reg_12, reg_13, reg_14, reg_15 : REGISTER_T;
53 
 
54 2 jlechner 
 
55 49 ustadler 
begin  -- register_file_rtl
56 19 ustadler 
 
57 57 cwalter 
  SYNC : process(clk, reset, dreg_enable, sr_enable, lr_enable)
58 
  begin
59 
 
60 
    if reset = '0' then
61 
 
62 
      reg_0  <= (others => '0');
63 
      reg_1  <= (others => '0');
64 
      reg_2  <= (others => '0');
65 
      reg_3  <= (others => '0');
66 
      reg_4  <= (others => '0');
67 
      reg_5  <= (others => '0');
68 
      reg_6  <= (others => '0');
69 
      reg_7  <= (others => '0');
70 
      reg_8  <= (others => '0');
71 
      reg_9  <= (others => '0');
72 
      reg_10 <= (others => '0');
73 
      reg_11 <= (others => '0');
74 
      reg_12 <= (others => '0');
75 
      reg_13 <= (others => '0');
76 
      reg_14 <= (others => '0');
77 
      reg_15 <= (others => '0');
78 2 jlechner 
 
79 19 ustadler 
 
80 57 cwalter 
    elsif clk'event and clk = '1' then
81 
 
82 
 
83 
      if dreg_addr = "0000" and dreg_enable = '1' then
84 
        reg_0 <= dreg_write;
85 
 
86 
      elsif dreg_addr = "0001" and dreg_enable = '1' then
87 
        reg_1 <= dreg_write;
88 
 
89 
      elsif dreg_addr = "0010" and dreg_enable = '1' then
90 
        reg_2 <= dreg_write;
91 
 
92 
      elsif dreg_addr = "0011" and dreg_enable = '1' then
93 
        reg_3 <= dreg_write;
94 
 
95 
      elsif dreg_addr = "0100" and dreg_enable = '1' then
96 
        reg_4 <= dreg_write;
97 
 
98 
      elsif dreg_addr = "0101" and dreg_enable = '1' then
99 
        reg_5 <= dreg_write;
100 
 
101 
      elsif dreg_addr = "0110" and dreg_enable = '1' then
102 
        reg_6 <= dreg_write;
103 
 
104 
      elsif dreg_addr = "0111" and dreg_enable = '1' then
105 
        reg_7 <= dreg_write;
106 
 
107 
      elsif dreg_addr = "1000" and dreg_enable = '1' then
108 
        reg_8 <= dreg_write;
109 
 
110 
      elsif dreg_addr = "1001" and dreg_enable = '1' then
111 
        reg_9 <= dreg_write;
112 
 
113 
      elsif dreg_addr = "1010" and dreg_enable = '1' then
114 
        reg_10 <= dreg_write;
115 
 
116 
      elsif dreg_addr = "1011" and dreg_enable = '1' then
117 
        reg_11 <= dreg_write;
118 
 
119 
      elsif dreg_addr = "1100" and dreg_enable = '1' then
120 
        reg_12 <= dreg_write;
121 
 
122 
      end if;
123 19 ustadler 
 
124 57 cwalter 
      if dreg_addr = "1101" and dreg_enable = '1' then
125 
        reg_13 <= dreg_write;
126 
      elsif lr_enable = '1' then
127 
        reg_13 <= lr_write;
128 
      end if;
129 21 ustadler 
 
130 57 cwalter 
      if dreg_addr = "1110" and dreg_enable = '1' then
131 
        reg_14 <= dreg_write;
132 
      else
133 
        reg_14 <= pc_write;
134 
      end if;
135 19 ustadler 
 
136 57 cwalter 
      if dreg_addr = "1111" and dreg_enable = '1' then
137 
        reg_15 <= dreg_write;
138 
      elsif sr_enable = '1' then
139 
        reg_15 <= sr_write;
140 
      end if;
141 21 ustadler 
 
142 57 cwalter 
    end if;
143 
 
144 
  end process SYNC;
145 21 ustadler 
 
146 57 cwalter 
  SPECIAL_READ_PROC : process (reset, reg_14, reg_15)
147 
  begin
148 
 
149 
    sr_read <= reg_15;
150 
    pc_read <= reg_14;
151 
 
152 
  end process SPECIAL_READ_PROC;
153 19 ustadler 
 
154 
 
155 57 cwalter 
  RX_READ_PROC : process(reset, rx_addr,
156 
                        reg_0, reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7,
157 
                        reg_8, reg_9, reg_10, reg_11, reg_12, reg_13, reg_14, reg_15)
158 
  begin
159 
 
160 
    if reset = '0' then
161 
 
162 
      rx_read <= (others => '0');
163 
    else
164 
 
165 
      case rx_addr is
166 
        when "0000" => rx_read <= reg_0;
167 
        when "0001" => rx_read <= reg_1;
168 
        when "0010" => rx_read <= reg_2;
169 
        when "0011" => rx_read <= reg_3;
170 
        when "0100" => rx_read <= reg_4;
171 
        when "0101" => rx_read <= reg_5;
172 
        when "0110" => rx_read <= reg_6;
173 
        when "0111" => rx_read <= reg_7;
174 
        when "1000" => rx_read <= reg_8;
175 
        when "1001" => rx_read <= reg_9;
176 
        when "1010" => rx_read <= reg_10;
177 
        when "1011" => rx_read <= reg_11;
178 
        when "1100" => rx_read <= reg_12;
179 
        when "1101" => rx_read <= reg_13;
180 
        when "1110" => rx_read <= reg_14;
181 
        when "1111" => rx_read <= reg_15;
182 
        when others => rx_read <= "XXXXXXXXXXXXXXXX";
183 
      end case;
184 
 
185 
    end if;
186 19 ustadler 
 
187 57 cwalter 
  end process RX_READ_PROC;
188 
 
189 
 
190 
  RY_READ_PROC : process(reset, ry_addr,
191 
                        reg_0, reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7,
192 
                        reg_8, reg_9, reg_10, reg_11, reg_12, reg_13, reg_14, reg_15)
193 
  begin
194 
 
195 
    if reset = '0' then
196 
 
197 
      ry_read <= (others => '0');
198 
    else
199 
 
200 
      case ry_addr is
201 
        when "0000" => ry_read <= reg_0;
202 
        when "0001" => ry_read <= reg_1;
203 
        when "0010" => ry_read <= reg_2;
204 
        when "0011" => ry_read <= reg_3;
205 
        when "0100" => ry_read <= reg_4;
206 
        when "0101" => ry_read <= reg_5;
207 
        when "0110" => ry_read <= reg_6;
208 
        when "0111" => ry_read <= reg_7;
209 
        when "1000" => ry_read <= reg_8;
210 
        when "1001" => ry_read <= reg_9;
211 
        when "1010" => ry_read <= reg_10;
212 
        when "1011" => ry_read <= reg_11;
213 
        when "1100" => ry_read <= reg_12;
214 
        when "1101" => ry_read <= reg_13;
215 
        when "1110" => ry_read <= reg_14;
216 
        when "1111" => ry_read <= reg_15;
217 
        when others => ry_read <= "XXXXXXXXXXXXXXXX";
218 
      end case;
219 
 
220 
    end if;
221 49 ustadler 
 
222 57 cwalter 
  end process RY_READ_PROC;
223 2 jlechner 
 
224 57 cwalter 
 
225 
 
226 
  RZ_READ_PROC : process(reset, rz_addr,
227 
                        reg_0, reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7,
228 
                        reg_8, reg_9, reg_10, reg_11, reg_12, reg_13, reg_14, reg_15)
229 
  begin
230 
 
231 
    if reset = '0' then
232 
 
233 
      rz_read <= (others => '0');
234 
    else
235 
 
236 
      case rz_addr is
237 
        when "0000" => rz_read <= reg_0;
238 
        when "0001" => rz_read <= reg_1;
239 
        when "0010" => rz_read <= reg_2;
240 
        when "0011" => rz_read <= reg_3;
241 
        when "0100" => rz_read <= reg_4;
242 
        when "0101" => rz_read <= reg_5;
243 
        when "0110" => rz_read <= reg_6;
244 
        when "0111" => rz_read <= reg_7;
245 
        when "1000" => rz_read <= reg_8;
246 
        when "1001" => rz_read <= reg_9;
247 
        when "1010" => rz_read <= reg_10;
248 
        when "1011" => rz_read <= reg_11;
249 
        when "1100" => rz_read <= reg_12;
250 
        when "1101" => rz_read <= reg_13;
251 
        when "1110" => rz_read <= reg_14;
252 
        when "1111" => rz_read <= reg_15;
253 
        when others => rz_read <= "XXXXXXXXXXXXXXXX";
254 
      end case;
255 
 
256 
    end if;
257 2 jlechner 
 
258 57 cwalter 
  end process RZ_READ_PROC;
259 
 
260 
 
261 
 
262 49 ustadler 
end register_file_rtl;
263 
 

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