URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [register_file.vhd] - Blame information for rev 19

Go to most recent revision | Details | Compare with Previous | View Log


 
 
-- File: register_file.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Entity implementing register file.
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
 
use WORK.RISE_PACK.all;
 
 
entity register_file is
 
  port (
    clk            : in std_logic;
    reset          : in std_logic;
 
    rx_addr        : in REGISTER_ADDR_T;
    ry_addr        : in REGISTER_ADDR_T;
    rz_addr        : in REGISTER_ADDR_T;
    dreg_addr      : in REGISTER_ADDR_T;
 
    dreg_write     : in REGISTER_T;
    rx_read        : out REGISTER_T;
    ry_read        : out REGISTER_T;
    rz_read        : out REGISTER_T;
 
    sr_write       : in SR_REGISTER_T;
    lr_write       : in PC_REGISTER_T;
    pc_write       : in PC_REGISTER_T;
    sr_read        : out SR_REGISTER_T;
    pc_read        : out PC_REGISTER_T);
 
end register_file;
 
architecture register_file_rtl of register_file is
 
 
        signal rx_read_next     : REGISTER_T;
        signal ry_read_next     : REGISTER_T;
        signal rz_read_next     : REGISTER_T;
 
        signal sr_read_next     : SR_REGISTER_T;
        signal pc_read_next     : PC_REGISTER_T;
 
        signal dreg_addr_tmp            :       REGISTER_ADDR_T;
        signal dreg_write_tmp   :       REGISTER_T;
 
        signal sr_write_tmp     :       SR_REGISTER_T;
        signal lr_write_tmp     :       PC_REGISTER_T;
        signal pc_write_tmp     :       PC_REGISTER_T;
 
 
 
        signal regx_0, regx_1, regx_2, regx_3, regx_4                                           :       REGISTER_T;
        signal regx_5, regx_6, regx_7, regx_8, regx_9                                           :       REGISTER_T;
        signal regx_10, regx_11, regx_12, regx_13, regx_14, regx_15             :       REGISTER_T;
 
        signal regy_0, regy_1, regy_2, regy_3, regy_4                                           :       REGISTER_T;
        signal regy_5, regy_6, regy_7, regy_8, regy_9                                           :       REGISTER_T;
        signal regy_10, regy_11, regy_12, regy_13, regy_14, regy_15             :       REGISTER_T;
 
        signal regz_0, regz_1, regz_2, regz_3, regz_4                                           :       REGISTER_T;
        signal regz_5, regz_6, regz_7, regz_8, regz_9                                           :       REGISTER_T;
        signal regz_10, regz_11, regz_12, regz_13, regz_14, regz_15             :       REGISTER_T;
 
begin  -- register_file_rtl
 
        SYNC: process(clk, reset)
        begin
 
                if reset = '0' then
 
                        rx_read <= (others => '0');
                        ry_read <= (others => '0');
                        rz_read <= (others => '0');
 
                        sr_read <=      (others => '0');
                        pc_read <=( others => '0');
 
                        sr_write_tmp    <=      (others => '0');
                        lr_write_tmp    <=      (others => '0');
                        pc_write_tmp    <= (others => '0');
 
                        dreg_addr_tmp   <=      (others => '0');
                        dreg_write_tmp  <= (others => '0');
 
                elsif clk'event and clk = '1' then
 
                        rx_read         <=      rx_read_next;
                        ry_read         <=      ry_read_next;
                        rz_read         <=      rz_read_next;
 
                        sr_read <=      sr_read_next;
                        pc_read <=      pc_read_next;
 
                        sr_write_tmp    <=      sr_write;
                        lr_write_tmp    <=      lr_write;
                        pc_write_tmp    <= pc_write;
 
                        dreg_addr_tmp   <=      dreg_addr;
                        dreg_write_tmp  <= dreg_write;
 
                end if;
 
        end process SYNC;
 
        WRITE: process(clk, reset)
        begin
 
                if reset = '0' then
 
                        sr_read_next    <= (others => '0');
                        pc_read_next    <= (others => '0');
 
                        regx_0  <= (others => '0');
                        regx_1  <= (others => '0');
                        regx_2  <= (others => '0');
                        regx_3  <= (others => '0');
                        regx_4  <= (others => '0');
                        regx_5  <= (others => '0');
                        regx_6  <= (others => '0');
                        regx_7  <= (others => '0');
                        regx_8  <= (others => '0');
                        regx_9  <= (others => '0');
                        regx_10 <= (others => '0');
                        regx_11 <= (others => '0');
                        regx_12 <= (others => '0');
                        regx_13 <= (others => '0');
                        regx_14 <= (others => '0');
                        regx_15 <= (others => '0');
 
                        regy_0  <= (others => '0');
                        regy_1  <= (others => '0');
                        regy_2  <= (others => '0');
                        regy_3  <= (others => '0');
                        regy_4  <= (others => '0');
                        regy_5  <= (others => '0');
                        regy_6  <= (others => '0');
                        regy_7  <= (others => '0');
                        regy_8  <= (others => '0');
                        regy_9  <= (others => '0');
                        regy_10 <= (others => '0');
                        regy_11 <= (others => '0');
                        regy_12 <= (others => '0');
                        regy_13 <= (others => '0');
                        regy_14 <= (others => '0');
                        regy_15 <= (others => '0');
 
                        regz_0  <= (others => '0');
                        regz_1  <= (others => '0');
                        regz_2  <= (others => '0');
                        regz_3  <= (others => '0');
                        regz_4  <= (others => '0');
                        regz_5  <= (others => '0');
                        regz_6  <= (others => '0');
                        regz_7  <= (others => '0');
                        regz_8  <= (others => '0');
                        regz_9  <= (others => '0');
                        regz_10 <= (others => '0');
                        regz_11 <= (others => '0');
                        regz_12 <= (others => '0');
                        regz_13 <= (others => '0');
                        regz_14 <= (others => '0');
                        regz_15 <= (others => '0');
 
                elsif clk'event and clk = '0' then
 
                        sr_read_next    <= sr_write_tmp;
                        --lr_write_next <= lr_write_tmp;
                        pc_read_next    <= pc_write_tmp;
 
 
                        if dreg_addr_tmp = "0000" then
 
                                regx_0 <= dreg_write_tmp;
                                regy_0 <= dreg_write_tmp;
                                regz_0 <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0001" then
 
                                regx_1  <= dreg_write_tmp;
                                regy_1  <= dreg_write_tmp;
                                regz_1  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0010" then
 
                                regx_2  <= dreg_write_tmp;
                                regy_2  <= dreg_write_tmp;
                                regz_2  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0011" then
 
                                regx_3  <= dreg_write_tmp;
                                regy_3  <= dreg_write_tmp;
                                regz_3  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0100" then
 
                                regx_4  <= dreg_write_tmp;
                                regy_4  <= dreg_write_tmp;
                                regz_4  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0101" then
 
                                regx_5  <= dreg_write_tmp;
                                regy_5  <= dreg_write_tmp;
                                regz_5  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0110" then
 
                                regx_6  <= dreg_write_tmp;
                                regy_6  <= dreg_write_tmp;
                                regz_6  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "0111" then
 
                                regx_7  <= dreg_write_tmp;
                                regy_7  <= dreg_write_tmp;
                                regz_7  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1000" then
 
                                regx_8  <= dreg_write_tmp;
                                regy_8  <= dreg_write_tmp;
                                regz_8  <= dreg_write_tmp;
                        elsif   dreg_addr_tmp = "1001" then
 
                                regx_9  <= dreg_write_tmp;
                                regy_9  <= dreg_write_tmp;
                                regz_9  <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1010" then
 
                                regx_10 <= dreg_write_tmp;
                                regy_10         <= dreg_write_tmp;
                                regz_10         <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1011" then
 
                                regx_11 <= dreg_write_tmp;
                                regy_11         <= dreg_write_tmp;
                                regz_11         <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1100" then
 
                                regx_12 <= dreg_write_tmp;
                                regy_12         <= dreg_write_tmp;
                                regz_12         <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1101" then
 
                                regx_13 <= dreg_write_tmp;
                                regy_13         <= dreg_write_tmp;
                                regz_13         <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1110" then
 
                                regx_14 <= dreg_write_tmp;
                                regy_14         <= dreg_write_tmp;
                                regz_14         <= dreg_write_tmp;
 
                        elsif   dreg_addr_tmp = "1111" then
 
                                regx_15 <= dreg_write_tmp;
                                regy_15         <= dreg_write_tmp;
                                regz_15         <= dreg_write_tmp;
 
                        end if;
 
                end if;
 
        end process WRITE;
 
 
        RX_READ_PROC: process(reset, rx_addr,
                                                regx_0,  regx_1, regx_2, regx_3, regx_4, regx_5, regx_6, regx_7,
                                                regx_8, regx_9, regx_10, regx_11, regx_12, regx_13, regx_14, regx_15)
        begin
 
        if reset = '0' then
 
                rx_read_next <= (others => '0');
        else
 
                CASE rx_addr IS
                        WHEN "0000" => rx_read_next <= regx_0;
                        WHEN "0001" => rx_read_next <= regx_1;
                        WHEN "0010" => rx_read_next <= regx_2;
                        WHEN "0011" => rx_read_next <= regx_3;
                        WHEN "0100" => rx_read_next <= regx_4;
                        WHEN "0101" => rx_read_next <= regx_5;
                        WHEN "0110" => rx_read_next <= regx_6;
                        WHEN "0111" => rx_read_next <= regx_7;
                        WHEN "1000" => rx_read_next <= regx_8;
                        WHEN "1001" => rx_read_next <= regx_9;
                        WHEN "1010" => rx_read_next <= regx_10;
                        WHEN "1011" => rx_read_next <= regx_11;
                        WHEN "1100" => rx_read_next <= regx_12;
                        WHEN "1101" => rx_read_next <= regx_13;
                        WHEN "1110" => rx_read_next <= regx_14;
                        WHEN "1111" => rx_read_next <= regx_15;
                        WHEN OTHERS => rx_read_next <= "XXXXXXXXXXXXXXXX";
                END CASE;
 
        end if;
 
        end process RX_READ_PROC;
 
 
 
        RY_READ_PROC: process(reset, ry_addr,
                                                regy_0,  regy_1, regy_2, regy_3, regy_4, regy_5, regy_6, regy_7,
                                                regy_8, regy_9, regy_10, regy_11, regy_12, regy_13, regy_14, regy_15)
        begin
 
        if reset = '0' then
 
                ry_read_next <= (others => '0');
        else
 
                CASE ry_addr IS
                        WHEN "0000" => ry_read_next <= regy_0;
                        WHEN "0001" => ry_read_next <= regy_1;
                        WHEN "0010" => ry_read_next <= regy_2;
                        WHEN "0011" => ry_read_next <= regy_3;
                        WHEN "0100" => ry_read_next <= regy_4;
                        WHEN "0101" => ry_read_next <= regy_5;
                        WHEN "0110" => ry_read_next <= regy_6;
                        WHEN "0111" => ry_read_next <= regy_7;
                        WHEN "1000" => ry_read_next <= regy_8;
                        WHEN "1001" => ry_read_next <= regy_9;
                        WHEN "1010" => ry_read_next <= regy_10;
                        WHEN "1011" => ry_read_next <= regy_11;
                        WHEN "1100" => ry_read_next <= regy_12;
                        WHEN "1101" => ry_read_next <= regy_13;
                        WHEN "1110" => ry_read_next <= regy_14;
                        WHEN "1111" => ry_read_next <= regy_15;
                        WHEN OTHERS => ry_read_next <= "XXXXXXXXXXXXXXXX";
                END CASE;
 
        end if;
 
        end process RY_READ_PROC;
 
 
 
        RZ_READ_PROC: process(reset, rz_addr,
                                                regz_0,  regz_1, regz_2, regz_3, regz_4, regz_5, regz_6, regz_7,
                                                regz_8, regz_9, regz_10, regz_11, regz_12, regz_13, regz_14, regz_15)
        begin
 
        if reset = '0' then
 
                rz_read_next <= (others => '0');
        else
 
                CASE rz_addr IS
                        WHEN "0000" => rz_read_next <= regz_0;
                        WHEN "0001" => rz_read_next <= regz_1;
                        WHEN "0010" => rz_read_next <= regz_2;
                        WHEN "0011" => rz_read_next <= regz_3;
                        WHEN "0100" => rz_read_next <= regz_4;
                        WHEN "0101" => rz_read_next <= regz_5;
                        WHEN "0110" => rz_read_next <= regz_6;
                        WHEN "0111" => rz_read_next <= regz_7;
                        WHEN "1000" => rz_read_next <= regz_8;
                        WHEN "1001" => rz_read_next <= regz_9;
                        WHEN "1010" => rz_read_next <= regz_10;
                        WHEN "1011" => rz_read_next <= regz_11;
                        WHEN "1100" => rz_read_next <= regz_12;
                        WHEN "1101" => rz_read_next <= regz_13;
                        WHEN "1110" => rz_read_next <= regz_14;
                        WHEN "1111" => rz_read_next <= regz_15;
                        WHEN OTHERS => rz_read_next <= "XXXXXXXXXXXXXXXX";
                END CASE;
 
        end if;
 
        end process RZ_READ_PROC;
 
 
 
end register_file_rtl;
 

Browse

Tools

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [register_file.vhd] - Blame information for rev 19

Line No.	Rev	Author	Line
1	19	ustadler
2
3	2	jlechner	`-- File: register_file.vhd`
4			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
5			`-- Created: 2006-11-29`
6			`-- Last updated: 2006-11-29`
7
8			`-- Description:`
9			`-- Entity implementing register file.`
10			`-------------------------------------------------------------------------------`
11
12			`library IEEE;`
13			`use IEEE.STD_LOGIC_1164.all;`
14			`use IEEE.STD_LOGIC_ARITH.all;`
15
16			`use WORK.RISE_PACK.all;`
17
18
19			`entity register_file is`
20
21			`port (`
22			`clk : in std_logic;`
23			`reset : in std_logic;`
24
25			`rx_addr : in REGISTER_ADDR_T;`
26			`ry_addr : in REGISTER_ADDR_T;`
27			`rz_addr : in REGISTER_ADDR_T;`
28			`dreg_addr : in REGISTER_ADDR_T;`
29
30			`dreg_write : in REGISTER_T;`
31			`rx_read : out REGISTER_T;`
32			`ry_read : out REGISTER_T;`
33			`rz_read : out REGISTER_T;`
34
35			`sr_write : in SR_REGISTER_T;`
36			`lr_write : in PC_REGISTER_T;`
37			`pc_write : in PC_REGISTER_T;`
38			`sr_read : out SR_REGISTER_T;`
39			`pc_read : out PC_REGISTER_T);`
40
41			`end register_file;`
42
43			`architecture register_file_rtl of register_file is`
44
45	19	ustadler
46			`signal rx_read_next : REGISTER_T;`
47			`signal ry_read_next : REGISTER_T;`
48			`signal rz_read_next : REGISTER_T;`
49
50			`signal sr_read_next : SR_REGISTER_T;`
51			`signal pc_read_next : PC_REGISTER_T;`
52
53			`signal dreg_addr_tmp : REGISTER_ADDR_T;`
54			`signal dreg_write_tmp : REGISTER_T;`
55
56			`signal sr_write_tmp : SR_REGISTER_T;`
57			`signal lr_write_tmp : PC_REGISTER_T;`
58			`signal pc_write_tmp : PC_REGISTER_T;`
59
60
61
62			`signal regx_0, regx_1, regx_2, regx_3, regx_4 : REGISTER_T;`
63			`signal regx_5, regx_6, regx_7, regx_8, regx_9 : REGISTER_T;`
64			`signal regx_10, regx_11, regx_12, regx_13, regx_14, regx_15 : REGISTER_T;`
65
66			`signal regy_0, regy_1, regy_2, regy_3, regy_4 : REGISTER_T;`
67			`signal regy_5, regy_6, regy_7, regy_8, regy_9 : REGISTER_T;`
68			`signal regy_10, regy_11, regy_12, regy_13, regy_14, regy_15 : REGISTER_T;`
69
70			`signal regz_0, regz_1, regz_2, regz_3, regz_4 : REGISTER_T;`
71			`signal regz_5, regz_6, regz_7, regz_8, regz_9 : REGISTER_T;`
72			`signal regz_10, regz_11, regz_12, regz_13, regz_14, regz_15 : REGISTER_T;`
73
74	2	jlechner	`begin -- register_file_rtl`
75
76	19	ustadler	`SYNC: process(clk, reset)`
77			`begin`
78
79			`if reset = '0' then`
80
81			`rx_read <= (others => '0');`
82			`ry_read <= (others => '0');`
83			`rz_read <= (others => '0');`
84
85			`sr_read <= (others => '0');`
86			`pc_read <=( others => '0');`
87
88			`sr_write_tmp <= (others => '0');`
89			`lr_write_tmp <= (others => '0');`
90			`pc_write_tmp <= (others => '0');`
91
92			`dreg_addr_tmp <= (others => '0');`
93			`dreg_write_tmp <= (others => '0');`
94
95			`elsif clk'event and clk = '1' then`
96
97			`rx_read <= rx_read_next;`
98			`ry_read <= ry_read_next;`
99			`rz_read <= rz_read_next;`
100
101			`sr_read <= sr_read_next;`
102			`pc_read <= pc_read_next;`
103
104			`sr_write_tmp <= sr_write;`
105			`lr_write_tmp <= lr_write;`
106			`pc_write_tmp <= pc_write;`
107
108			`dreg_addr_tmp <= dreg_addr;`
109			`dreg_write_tmp <= dreg_write;`
110
111			`end if;`
112
113			`end process SYNC;`
114
115			`WRITE: process(clk, reset)`
116			`begin`
117
118			`if reset = '0' then`
119
120			`sr_read_next <= (others => '0');`
121			`pc_read_next <= (others => '0');`
122
123			`regx_0 <= (others => '0');`
124			`regx_1 <= (others => '0');`
125			`regx_2 <= (others => '0');`
126			`regx_3 <= (others => '0');`
127			`regx_4 <= (others => '0');`
128			`regx_5 <= (others => '0');`
129			`regx_6 <= (others => '0');`
130			`regx_7 <= (others => '0');`
131			`regx_8 <= (others => '0');`
132			`regx_9 <= (others => '0');`
133			`regx_10 <= (others => '0');`
134			`regx_11 <= (others => '0');`
135			`regx_12 <= (others => '0');`
136			`regx_13 <= (others => '0');`
137			`regx_14 <= (others => '0');`
138			`regx_15 <= (others => '0');`
139
140			`regy_0 <= (others => '0');`
141			`regy_1 <= (others => '0');`
142			`regy_2 <= (others => '0');`
143			`regy_3 <= (others => '0');`
144			`regy_4 <= (others => '0');`
145			`regy_5 <= (others => '0');`
146			`regy_6 <= (others => '0');`
147			`regy_7 <= (others => '0');`
148			`regy_8 <= (others => '0');`
149			`regy_9 <= (others => '0');`
150			`regy_10 <= (others => '0');`
151			`regy_11 <= (others => '0');`
152			`regy_12 <= (others => '0');`
153			`regy_13 <= (others => '0');`
154			`regy_14 <= (others => '0');`
155			`regy_15 <= (others => '0');`
156
157			`regz_0 <= (others => '0');`
158			`regz_1 <= (others => '0');`
159			`regz_2 <= (others => '0');`
160			`regz_3 <= (others => '0');`
161			`regz_4 <= (others => '0');`
162			`regz_5 <= (others => '0');`
163			`regz_6 <= (others => '0');`
164			`regz_7 <= (others => '0');`
165			`regz_8 <= (others => '0');`
166			`regz_9 <= (others => '0');`
167			`regz_10 <= (others => '0');`
168			`regz_11 <= (others => '0');`
169			`regz_12 <= (others => '0');`
170			`regz_13 <= (others => '0');`
171			`regz_14 <= (others => '0');`
172			`regz_15 <= (others => '0');`
173
174			`elsif clk'event and clk = '0' then`
175
176			`sr_read_next <= sr_write_tmp;`
177			`--lr_write_next <= lr_write_tmp;`
178			`pc_read_next <= pc_write_tmp;`
179
180
181			`if dreg_addr_tmp = "0000" then`
182
183			`regx_0 <= dreg_write_tmp;`
184			`regy_0 <= dreg_write_tmp;`
185			`regz_0 <= dreg_write_tmp;`
186
187			`elsif dreg_addr_tmp = "0001" then`
188
189			`regx_1 <= dreg_write_tmp;`
190			`regy_1 <= dreg_write_tmp;`
191			`regz_1 <= dreg_write_tmp;`
192
193			`elsif dreg_addr_tmp = "0010" then`
194
195			`regx_2 <= dreg_write_tmp;`
196			`regy_2 <= dreg_write_tmp;`
197			`regz_2 <= dreg_write_tmp;`
198
199			`elsif dreg_addr_tmp = "0011" then`
200
201			`regx_3 <= dreg_write_tmp;`
202			`regy_3 <= dreg_write_tmp;`
203			`regz_3 <= dreg_write_tmp;`
204
205			`elsif dreg_addr_tmp = "0100" then`
206
207			`regx_4 <= dreg_write_tmp;`
208			`regy_4 <= dreg_write_tmp;`
209			`regz_4 <= dreg_write_tmp;`
210
211			`elsif dreg_addr_tmp = "0101" then`
212
213			`regx_5 <= dreg_write_tmp;`
214			`regy_5 <= dreg_write_tmp;`
215			`regz_5 <= dreg_write_tmp;`
216
217			`elsif dreg_addr_tmp = "0110" then`
218
219			`regx_6 <= dreg_write_tmp;`
220			`regy_6 <= dreg_write_tmp;`
221			`regz_6 <= dreg_write_tmp;`
222
223			`elsif dreg_addr_tmp = "0111" then`
224
225			`regx_7 <= dreg_write_tmp;`
226			`regy_7 <= dreg_write_tmp;`
227			`regz_7 <= dreg_write_tmp;`
228
229			`elsif dreg_addr_tmp = "1000" then`
230
231			`regx_8 <= dreg_write_tmp;`
232			`regy_8 <= dreg_write_tmp;`
233			`regz_8 <= dreg_write_tmp;`
234			`elsif dreg_addr_tmp = "1001" then`
235
236			`regx_9 <= dreg_write_tmp;`
237			`regy_9 <= dreg_write_tmp;`
238			`regz_9 <= dreg_write_tmp;`
239
240			`elsif dreg_addr_tmp = "1010" then`
241
242			`regx_10 <= dreg_write_tmp;`
243			`regy_10 <= dreg_write_tmp;`
244			`regz_10 <= dreg_write_tmp;`
245
246			`elsif dreg_addr_tmp = "1011" then`
247
248			`regx_11 <= dreg_write_tmp;`
249			`regy_11 <= dreg_write_tmp;`
250			`regz_11 <= dreg_write_tmp;`
251
252			`elsif dreg_addr_tmp = "1100" then`
253
254			`regx_12 <= dreg_write_tmp;`
255			`regy_12 <= dreg_write_tmp;`
256			`regz_12 <= dreg_write_tmp;`
257
258			`elsif dreg_addr_tmp = "1101" then`
259
260			`regx_13 <= dreg_write_tmp;`
261			`regy_13 <= dreg_write_tmp;`
262			`regz_13 <= dreg_write_tmp;`
263
264			`elsif dreg_addr_tmp = "1110" then`
265
266			`regx_14 <= dreg_write_tmp;`
267			`regy_14 <= dreg_write_tmp;`
268			`regz_14 <= dreg_write_tmp;`
269
270			`elsif dreg_addr_tmp = "1111" then`
271
272			`regx_15 <= dreg_write_tmp;`
273			`regy_15 <= dreg_write_tmp;`
274			`regz_15 <= dreg_write_tmp;`
275
276			`end if;`
277
278			`end if;`
279
280			`end process WRITE;`
281
282
283			`RX_READ_PROC: process(reset, rx_addr,`
284			`regx_0, regx_1, regx_2, regx_3, regx_4, regx_5, regx_6, regx_7,`
285			`regx_8, regx_9, regx_10, regx_11, regx_12, regx_13, regx_14, regx_15)`
286			`begin`
287
288			`if reset = '0' then`
289
290			`rx_read_next <= (others => '0');`
291			`else`
292
293			`CASE rx_addr IS`
294			`WHEN "0000" => rx_read_next <= regx_0;`
295			`WHEN "0001" => rx_read_next <= regx_1;`
296			`WHEN "0010" => rx_read_next <= regx_2;`
297			`WHEN "0011" => rx_read_next <= regx_3;`
298			`WHEN "0100" => rx_read_next <= regx_4;`
299			`WHEN "0101" => rx_read_next <= regx_5;`
300			`WHEN "0110" => rx_read_next <= regx_6;`
301			`WHEN "0111" => rx_read_next <= regx_7;`
302			`WHEN "1000" => rx_read_next <= regx_8;`
303			`WHEN "1001" => rx_read_next <= regx_9;`
304			`WHEN "1010" => rx_read_next <= regx_10;`
305			`WHEN "1011" => rx_read_next <= regx_11;`
306			`WHEN "1100" => rx_read_next <= regx_12;`
307			`WHEN "1101" => rx_read_next <= regx_13;`
308			`WHEN "1110" => rx_read_next <= regx_14;`
309			`WHEN "1111" => rx_read_next <= regx_15;`
310			`WHEN OTHERS => rx_read_next <= "XXXXXXXXXXXXXXXX";`
311			`END CASE;`
312
313			`end if;`
314
315			`end process RX_READ_PROC;`
316
317
318
319			`RY_READ_PROC: process(reset, ry_addr,`
320			`regy_0, regy_1, regy_2, regy_3, regy_4, regy_5, regy_6, regy_7,`
321			`regy_8, regy_9, regy_10, regy_11, regy_12, regy_13, regy_14, regy_15)`
322			`begin`
323
324			`if reset = '0' then`
325
326			`ry_read_next <= (others => '0');`
327			`else`
328
329			`CASE ry_addr IS`
330			`WHEN "0000" => ry_read_next <= regy_0;`
331			`WHEN "0001" => ry_read_next <= regy_1;`
332			`WHEN "0010" => ry_read_next <= regy_2;`
333			`WHEN "0011" => ry_read_next <= regy_3;`
334			`WHEN "0100" => ry_read_next <= regy_4;`
335			`WHEN "0101" => ry_read_next <= regy_5;`
336			`WHEN "0110" => ry_read_next <= regy_6;`
337			`WHEN "0111" => ry_read_next <= regy_7;`
338			`WHEN "1000" => ry_read_next <= regy_8;`
339			`WHEN "1001" => ry_read_next <= regy_9;`
340			`WHEN "1010" => ry_read_next <= regy_10;`
341			`WHEN "1011" => ry_read_next <= regy_11;`
342			`WHEN "1100" => ry_read_next <= regy_12;`
343			`WHEN "1101" => ry_read_next <= regy_13;`
344			`WHEN "1110" => ry_read_next <= regy_14;`
345			`WHEN "1111" => ry_read_next <= regy_15;`
346			`WHEN OTHERS => ry_read_next <= "XXXXXXXXXXXXXXXX";`
347			`END CASE;`
348
349			`end if;`
350
351			`end process RY_READ_PROC;`
352
353
354
355			`RZ_READ_PROC: process(reset, rz_addr,`
356			`regz_0, regz_1, regz_2, regz_3, regz_4, regz_5, regz_6, regz_7,`
357			`regz_8, regz_9, regz_10, regz_11, regz_12, regz_13, regz_14, regz_15)`
358			`begin`
359
360			`if reset = '0' then`
361
362			`rz_read_next <= (others => '0');`
363			`else`
364
365			`CASE rz_addr IS`
366			`WHEN "0000" => rz_read_next <= regz_0;`
367			`WHEN "0001" => rz_read_next <= regz_1;`
368			`WHEN "0010" => rz_read_next <= regz_2;`
369			`WHEN "0011" => rz_read_next <= regz_3;`
370			`WHEN "0100" => rz_read_next <= regz_4;`
371			`WHEN "0101" => rz_read_next <= regz_5;`
372			`WHEN "0110" => rz_read_next <= regz_6;`
373			`WHEN "0111" => rz_read_next <= regz_7;`
374			`WHEN "1000" => rz_read_next <= regz_8;`
375			`WHEN "1001" => rz_read_next <= regz_9;`
376			`WHEN "1010" => rz_read_next <= regz_10;`
377			`WHEN "1011" => rz_read_next <= regz_11;`
378			`WHEN "1100" => rz_read_next <= regz_12;`
379			`WHEN "1101" => rz_read_next <= regz_13;`
380			`WHEN "1110" => rz_read_next <= regz_14;`
381			`WHEN "1111" => rz_read_next <= regz_15;`
382			`WHEN OTHERS => rz_read_next <= "XXXXXXXXXXXXXXXX";`
383			`END CASE;`
384
385			`end if;`
386
387			`end process RZ_READ_PROC;`
388
389	2	jlechner
390
391			`end register_file_rtl;`
392	19	ustadler