URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [rise.vhd] - Blame information for rev 148

Details | Compare with Previous | View Log


-------------------------------------------------------------------------------
-- File: rise.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Top-Level entity of RISE CPU
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
 
use WORK.RISE_PACK.all;
use work.RISE_PACK_SPECIFIC.all;
 
entity rise is
 
  port (
    clk         : in  std_logic;
    reset       : in std_logic;
    -- uart
    rx          : in  std_logic;
    tx          : out std_logic);
 
end rise;
 
 
architecture rise_rtl of rise is
 
  -- if_stage signals
  signal if_id_register_sig        : IF_ID_REGISTER_T;
  signal branch_sig             : std_logic;
  signal branch_target_sig         : PC_REGISTER_T;
  signal stall_in_if_sig           : std_logic;
  signal clear_in_if_sig           : std_logic;
  signal pc_if_sig                 : PC_REGISTER_T;
  signal pc_next_if_sig            : PC_REGISTER_T;
  signal imem_addr_sig             : MEM_ADDR_T;
  signal imem_data_sig             : MEM_DATA_T;
  -- id_stage signals
  signal id_ex_register_sig        : ID_EX_REGISTER_T;
  signal rx_addr_sig               : REGISTER_ADDR_T;
  signal ry_addr_sig               : REGISTER_ADDR_T;
  signal rz_addr_sig               : REGISTER_ADDR_T;
  signal rx_sig                    : REGISTER_T;
  signal ry_sig                    : REGISTER_T;
  signal rz_sig                    : REGISTER_T;
  signal sr_id_sig                 : SR_REGISTER_T;
  signal lock_register_sig         : LOCK_REGISTER_T;
  signal stall_in_id_sig           : std_logic;
  signal stall_out_id_sig          : std_logic;
  signal clear_in_id_sig           : std_logic;
  -- ex_stage signals
  signal ex_mem_register_sig       :  EX_MEM_REGISTER_T;
  signal stall_in_ex_sig           : std_logic;
  signal clear_in_ex_sig           : std_logic;
  signal clear_out_ex_sig          : std_logic;
  signal clear_locks_sig           : std_logic;
  -- mem_stage signals
  signal mem_wb_register_sig       : MEM_WB_REGISTER_T;
  signal dmem_addr_sig             : MEM_ADDR_T;
  signal dmem_data_in_sig          : MEM_DATA_T;
  signal dmem_data_out_sig         : MEM_DATA_T;
  signal stall_out_mem_sig         : std_logic;
  signal clear_in_mem_sig          : std_logic;
  signal clear_out_mem_sig         : std_logic;
  -- wb_stage signals
  signal dreg_addr_sig             : REGISTER_ADDR_T;
  signal dreg_sig                  : REGISTER_T;
  signal dreg_enable_sig           : std_logic;
  signal lr_sig                    : PC_REGISTER_T;
  signal lr_enable_sig             : std_logic;
  signal sr_wb_sig                 : SR_REGISTER_T;
  signal sr_enable_sig             : std_logic;
  signal clear_out_wb_sig          : std_logic;
  -- imem signals
  signal data_in_imem_sig          : MEM_DATA_T;  -- unused at the moment
  signal wr_enable_imem_sig        : std_logic;   -- unused at the moment
  -- dmem signals
  signal wr_enable_dmem_sig        : std_logic;
  signal dmem_rxd_sig                     : std_logic;
  signal dmem_txd_sig                     : std_logic;
  -- rlu signals
  signal clear_lock0_sig      : std_logic := '0';
  signal clear_lock_addr0_sig : REGISTER_ADDR_T;
 
  signal clear_lock1_sig      : std_logic := '0';
  signal clear_lock_addr1_sig : REGISTER_ADDR_T;
 
  signal set_lock0_sig      : std_logic := '0';
  signal set_lock_addr0_sig : REGISTER_ADDR_T;
 
  signal set_lock1_sig      : std_logic := '0';
  signal set_lock_addr1_sig : REGISTER_ADDR_T;
 
  component if_stage
    port (
      clk            : in std_logic;
      reset          : in std_logic;
 
      if_id_register : out IF_ID_REGISTER_T;
 
      branch         : in std_logic;
      branch_target  : in PC_REGISTER_T;
      clear_in       : in std_logic;
      stall_in       : in std_logic;
 
      pc             : in PC_REGISTER_T;
      pc_next        : out PC_REGISTER_T;
 
      imem_addr      : out MEM_ADDR_T;
      imem_data      : in MEM_DATA_T);
  end component;
 
  component id_stage
    port (
      clk            : in std_logic;
      reset          : in std_logic;
 
      if_id_register : in IF_ID_REGISTER_T;
      id_ex_register : out ID_EX_REGISTER_T;
 
      rx_addr        : out REGISTER_ADDR_T;
      ry_addr        : out REGISTER_ADDR_T;
      rz_addr        : out REGISTER_ADDR_T;
 
      rx             : in REGISTER_T;
      ry             : in REGISTER_T;
      rz             : in REGISTER_T;
      sr             : in SR_REGISTER_T;
 
      lock_register  : in LOCK_REGISTER_T;
      set_reg_lock0  : out std_logic;
      lock_reg_addr0 : out REGISTER_ADDR_T;
      set_reg_lock1  : out std_logic;
      lock_reg_addr1 : out REGISTER_ADDR_T;
 
      stall_in       : in std_logic;
      stall_out      : out std_logic;
      clear_in       : in std_logic);
  end component;
 
  component ex_stage
    port (
      clk                 : in std_logic;
      reset               : in std_logic;
 
      id_ex_register      : in ID_EX_REGISTER_T;
      ex_mem_register     : out EX_MEM_REGISTER_T;
 
      branch              : out std_logic;
      stall_in            : in std_logic;
      clear_in            : in std_logic;
      clear_out           : out std_logic;
      clear_locks         : out std_logic);
  end component;
 
  component mem_stage
    port (
      clk                 : in std_logic;
      reset               : in std_logic;
 
      ex_mem_register     : in EX_MEM_REGISTER_T;
      mem_wb_register     : out MEM_WB_REGISTER_T;
 
      dmem_addr           : out MEM_ADDR_T;
      dmem_data_in        : in MEM_DATA_T;
      dmem_data_out       : out MEM_DATA_T;
      dmem_wr_enable      : out std_logic;
 
      stall_out           : out std_logic;
      clear_in            : in std_logic;
      clear_out           : out std_logic);
  end component;
 
  component wb_stage
    port (
      clk                 : in std_logic;
      reset               : in std_logic;
 
      mem_wb_register     : in MEM_WB_REGISTER_T;
 
      dreg_addr           : out REGISTER_ADDR_T;
      dreg                : out REGISTER_T;
      dreg_enable         : out std_logic;
 
      lr                  : out PC_REGISTER_T;
      lr_enable           : out std_logic;
 
      sr                  : out SR_REGISTER_T;
      sr_enable           : out std_logic;
 
      clear_out           : out std_logic;
 
      clear_reg_lock0     : out std_logic;
      lock_reg_addr0      : out REGISTER_ADDR_T;
      clear_reg_lock1     : out std_logic;
      lock_reg_addr1      : out REGISTER_ADDR_T);
  end component;
 
  component register_file
    port (
      clk            : in std_logic;
      reset          : in std_logic;
 
      rx_addr        : in REGISTER_ADDR_T;
      ry_addr        : in REGISTER_ADDR_T;
      rz_addr        : in REGISTER_ADDR_T;
 
      rx_read        : out REGISTER_T;
      ry_read        : out REGISTER_T;
      rz_read        : out REGISTER_T;
 
      dreg_addr      : in REGISTER_ADDR_T;
      dreg_write     : in REGISTER_T;
      dreg_enable    : in std_logic;
 
      sr_read        : out SR_REGISTER_T;
      sr_write       : in SR_REGISTER_T;
      sr_enable      : in std_logic;
 
      lr_write       : in PC_REGISTER_T;
      lr_enable      : in std_logic;
 
      pc_write       : in PC_REGISTER_T;
      pc_read        : out PC_REGISTER_T);
  end component;
 
  component imem
    port (
      clk            : in std_logic;
      reset          : in std_logic;
      wr_enable      : in std_logic;
      addr           : in MEM_ADDR_T;
      data_in        : in MEM_DATA_T;
      data_out       : out MEM_DATA_T);
  end component;
 
  component dmem
    port (
      clk            : in std_logic;
      reset          : in std_logic;
      wr_enable    : in std_logic;
      addr           : in MEM_ADDR_T;
      data_in        : in MEM_DATA_T;
      data_out       : out MEM_DATA_T;
                uart_txd                : out std_logic;
                uart_rxd                : in std_logic);
  end component;
 
  component rlu
    port (
      clk   : in std_logic;
      reset : in std_logic;
      clear_locks : in std_logic;
 
      lock_register       : out LOCK_REGISTER_T;
 
      set_lock0           : in std_logic;
      set_lock_addr0      : in REGISTER_ADDR_T;
 
      set_lock1           : in std_logic;
      set_lock_addr1      : in REGISTER_ADDR_T;
 
      clear_lock0         : in std_logic;
      clear_lock_addr0    : in REGISTER_ADDR_T;
 
      clear_lock1         : in std_logic;
      clear_lock_addr1    : in REGISTER_ADDR_T);
 
  end component;
 
begin  -- rise_rtl
 
  if_stage_unit : if_stage
    port map (
      clk            => clk,
      reset          => reset,
 
      if_id_register => if_id_register_sig,
 
      branch         => branch_sig,
      branch_target  => branch_target_sig,
      clear_in       => clear_in_if_sig,
      stall_in       => stall_in_if_sig,
 
      pc             => pc_if_sig,
      pc_next        => pc_next_if_sig,
 
      imem_addr      => imem_addr_sig,
      imem_data      => imem_data_sig);
 
  id_stage_unit : id_stage
    port map (
      clk            => clk,
      reset          => reset,
 
      if_id_register => if_id_register_sig,
      id_ex_register => id_ex_register_sig,
 
      rx_addr        => rx_addr_sig,
      ry_addr        => ry_addr_sig,
      rz_addr        => rz_addr_sig,
 
      rx             => rx_sig,
      ry             => ry_sig,
      rz             => rz_sig,
      sr             => sr_id_sig,
 
      lock_register  => lock_register_sig,
 
      set_reg_lock0  => set_lock0_sig,
      lock_reg_addr0 => set_lock_addr0_sig,
      set_reg_lock1  => set_lock1_sig,
      lock_reg_addr1 => set_lock_addr1_sig,
 
      stall_in       => stall_in_id_sig,
      stall_out      => stall_out_id_sig,
      clear_in       => clear_in_id_sig);
 
  ex_stage_unit : ex_stage
    port map (
      clk                 => clk,
      reset               => reset,
 
      id_ex_register      => id_ex_register_sig,
      ex_mem_register     => ex_mem_register_sig,
 
      branch              => branch_sig,
      stall_in            => stall_in_ex_sig,
      clear_in            => clear_in_ex_sig,
      clear_out           => clear_out_ex_sig,
      clear_locks         => clear_locks_sig);
 
  mem_stage_unit : mem_stage
    port map (
      clk                 => clk,
      reset               => reset,
 
      ex_mem_register     => ex_mem_register_sig,
      mem_wb_register     => mem_wb_register_sig,
 
      dmem_addr           => dmem_addr_sig,
      dmem_data_in        => dmem_data_in_sig,
      dmem_data_out       => dmem_data_out_sig,
      dmem_wr_enable      => wr_enable_dmem_sig,
 
      stall_out           => stall_out_mem_sig,
      clear_in            => clear_in_mem_sig,
      clear_out           => clear_out_mem_sig);
 
  wb_stage_unit : wb_stage
    port map (
      clk                 => clk,
      reset               => reset,
 
      mem_wb_register     => mem_wb_register_sig,
 
      dreg_addr           => dreg_addr_sig,
      dreg                => dreg_sig,
      dreg_enable         => dreg_enable_sig,
 
      lr                  => lr_sig,
      lr_enable           => lr_enable_sig,
 
      sr                  => sr_wb_sig,
      sr_enable           => sr_enable_sig,
 
      clear_out           => clear_out_wb_sig,
 
      clear_reg_lock0     => clear_lock0_sig,
      lock_reg_addr0      => clear_lock_addr0_sig,
      clear_reg_lock1     => clear_lock1_sig,
      lock_reg_addr1      => clear_lock_addr1_sig);
 
  register_file_unit : register_file
    port map (
      clk            => clk,
      reset          => reset,
 
      rx_addr        => rx_addr_sig,
      ry_addr        => ry_addr_sig,
      rz_addr        => rz_addr_sig,
 
      rx_read        => rx_sig,
      ry_read        => ry_sig,
      rz_read        => rz_sig,
 
      dreg_addr      => dreg_addr_sig,
      dreg_write     => dreg_sig,
      dreg_enable    => dreg_enable_sig,
 
      sr_read        => sr_id_sig,
      sr_write       => sr_wb_sig,
      sr_enable      => sr_enable_sig,
 
      lr_write       => lr_sig,
      lr_enable      => lr_enable_sig,
 
      pc_write       => pc_next_if_sig,
      pc_read        => pc_if_sig);
 
  imem_unit : imem
    port map (
      clk            => clk,
      reset          => reset,
      wr_enable      => wr_enable_imem_sig,
      addr           => imem_addr_sig,
      data_in        => data_in_imem_sig,
      data_out       => imem_data_sig);
 
  dmem_unit : dmem
    port map (
      clk            => clk,
      reset          => reset,
      wr_enable      => wr_enable_dmem_sig,
      addr           => dmem_addr_sig,
      data_in        => dmem_data_out_sig,
      data_out       => dmem_data_in_sig,
                uart_txd                => dmem_txd_sig,
                uart_rxd                => dmem_rxd_sig);
 
  rlu_unit : rlu port map(
    clk                 => clk,
    reset               => reset,
    clear_locks         => clear_locks_sig,
 
    lock_register       => lock_register_sig,
 
    set_lock0           => set_lock0_sig,
    set_lock_addr0      => set_lock_addr0_sig,
 
    set_lock1           => set_lock1_sig,
    set_lock_addr1      => set_lock_addr1_sig,
 
    clear_lock0         => clear_lock0_sig,
    clear_lock_addr0    => clear_lock_addr0_sig,
 
    clear_lock1         => clear_lock1_sig,
    clear_lock_addr1    => clear_lock_addr1_sig);
 
 
  clear_in_if_sig       <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;
  clear_in_id_sig       <= clear_in_if_sig;
  clear_in_ex_sig       <= clear_out_mem_sig or clear_out_wb_sig;
  clear_in_mem_sig      <= clear_out_wb_sig;
 
  stall_in_if_sig       <= stall_out_id_sig or stall_out_mem_sig;
  stall_in_id_sig       <= stall_out_mem_sig;
  stall_in_ex_sig       <= stall_out_mem_sig;
 
  branch_target_sig     <= ex_mem_register_sig.alu;
 
  data_in_imem_sig      <= (others => '-');  -- unused at the moment
  wr_enable_imem_sig    <= '-';  -- unused at the moment
 
  --  ports of top level entity
  tx                                    <= dmem_txd_sig;
  dmem_rxd_sig          <= rx;
 
end rise_rtl;

Line No.	Rev	Author	Line
1	2	jlechner	`-------------------------------------------------------------------------------`
2			`-- File: rise.vhd`
3			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
4			`-- Created: 2006-11-29`
5			`-- Last updated: 2006-11-29`
6
7			`-- Description:`
8			`-- Top-Level entity of RISE CPU`
9			`-------------------------------------------------------------------------------`
10
11			`library IEEE;`
12			`use IEEE.STD_LOGIC_1164.all;`
13			`use IEEE.STD_LOGIC_ARITH.all;`
14
15			`use WORK.RISE_PACK.all;`
16	71	jlechner	`use work.RISE_PACK_SPECIFIC.all;`
17	2	jlechner
18			`entity rise is`
19
20			`port (`
21			`clk : in std_logic;`
22			`reset : in std_logic;`
23			`-- uart`
24			`rx : in std_logic;`
25			`tx : out std_logic);`
26
27			`end rise;`
28
29
30			`architecture rise_rtl of rise is`
31
32			`-- if_stage signals`
33			`signal if_id_register_sig : IF_ID_REGISTER_T;`
34			`signal branch_sig : std_logic;`
35			`signal branch_target_sig : PC_REGISTER_T;`
36			`signal stall_in_if_sig : std_logic;`
37			`signal clear_in_if_sig : std_logic;`
38			`signal pc_if_sig : PC_REGISTER_T;`
39			`signal pc_next_if_sig : PC_REGISTER_T;`
40			`signal imem_addr_sig : MEM_ADDR_T;`
41			`signal imem_data_sig : MEM_DATA_T;`
42			`-- id_stage signals`
43			`signal id_ex_register_sig : ID_EX_REGISTER_T;`
44			`signal rx_addr_sig : REGISTER_ADDR_T;`
45			`signal ry_addr_sig : REGISTER_ADDR_T;`
46			`signal rz_addr_sig : REGISTER_ADDR_T;`
47			`signal rx_sig : REGISTER_T;`
48			`signal ry_sig : REGISTER_T;`
49			`signal rz_sig : REGISTER_T;`
50			`signal sr_id_sig : SR_REGISTER_T;`
51			`signal lock_register_sig : LOCK_REGISTER_T;`
52			`signal stall_in_id_sig : std_logic;`
53			`signal stall_out_id_sig : std_logic;`
54			`signal clear_in_id_sig : std_logic;`
55			`-- ex_stage signals`
56			`signal ex_mem_register_sig : EX_MEM_REGISTER_T;`
57			`signal stall_in_ex_sig : std_logic;`
58			`signal clear_in_ex_sig : std_logic;`
59			`signal clear_out_ex_sig : std_logic;`
60	94	jlechner	`signal clear_locks_sig : std_logic;`
61	2	jlechner	`-- mem_stage signals`
62			`signal mem_wb_register_sig : MEM_WB_REGISTER_T;`
63			`signal dmem_addr_sig : MEM_ADDR_T;`
64			`signal dmem_data_in_sig : MEM_DATA_T;`
65			`signal dmem_data_out_sig : MEM_DATA_T;`
66	39	jlechner	`signal stall_out_mem_sig : std_logic;`
67	2	jlechner	`signal clear_in_mem_sig : std_logic;`
68			`signal clear_out_mem_sig : std_logic;`
69			`-- wb_stage signals`
70			`signal dreg_addr_sig : REGISTER_ADDR_T;`
71			`signal dreg_sig : REGISTER_T;`
72	27	jlechner	`signal dreg_enable_sig : std_logic;`
73			`signal lr_sig : PC_REGISTER_T;`
74			`signal lr_enable_sig : std_logic;`
75	2	jlechner	`signal sr_wb_sig : SR_REGISTER_T;`
76	27	jlechner	`signal sr_enable_sig : std_logic;`
77	2	jlechner	`signal clear_out_wb_sig : std_logic;`
78			`-- imem signals`
79			`signal data_in_imem_sig : MEM_DATA_T; -- unused at the moment`
80	39	jlechner	`signal wr_enable_imem_sig : std_logic; -- unused at the moment`
81			`-- dmem signals`
82	124	trinklhar	`signal wr_enable_dmem_sig : std_logic;`
83			`signal dmem_rxd_sig : std_logic;`
84			`signal dmem_txd_sig : std_logic;`
85	39	jlechner	`-- rlu signals`
86			`signal clear_lock0_sig : std_logic := '0';`
87			`signal clear_lock_addr0_sig : REGISTER_ADDR_T;`
88
89			`signal clear_lock1_sig : std_logic := '0';`
90			`signal clear_lock_addr1_sig : REGISTER_ADDR_T;`
91
92			`signal set_lock0_sig : std_logic := '0';`
93			`signal set_lock_addr0_sig : REGISTER_ADDR_T;`
94
95			`signal set_lock1_sig : std_logic := '0';`
96			`signal set_lock_addr1_sig : REGISTER_ADDR_T;`
97	2	jlechner
98			`component if_stage`
99			`port (`
100			`clk : in std_logic;`
101			`reset : in std_logic;`
102
103			`if_id_register : out IF_ID_REGISTER_T;`
104
105			`branch : in std_logic;`
106			`branch_target : in PC_REGISTER_T;`
107			`clear_in : in std_logic;`
108			`stall_in : in std_logic;`
109
110			`pc : in PC_REGISTER_T;`
111			`pc_next : out PC_REGISTER_T;`
112
113			`imem_addr : out MEM_ADDR_T;`
114			`imem_data : in MEM_DATA_T);`
115			`end component;`
116
117			`component id_stage`
118			`port (`
119			`clk : in std_logic;`
120			`reset : in std_logic;`
121
122			`if_id_register : in IF_ID_REGISTER_T;`
123			`id_ex_register : out ID_EX_REGISTER_T;`
124
125			`rx_addr : out REGISTER_ADDR_T;`
126			`ry_addr : out REGISTER_ADDR_T;`
127			`rz_addr : out REGISTER_ADDR_T;`
128	16	cwalter
129	2	jlechner	`rx : in REGISTER_T;`
130			`ry : in REGISTER_T;`
131			`rz : in REGISTER_T;`
132			`sr : in SR_REGISTER_T;`
133
134			`lock_register : in LOCK_REGISTER_T;`
135	16	cwalter	`set_reg_lock0 : out std_logic;`
136			`lock_reg_addr0 : out REGISTER_ADDR_T;`
137			`set_reg_lock1 : out std_logic;`
138			`lock_reg_addr1 : out REGISTER_ADDR_T;`
139
140	2	jlechner	`stall_in : in std_logic;`
141			`stall_out : out std_logic;`
142			`clear_in : in std_logic);`
143			`end component;`
144
145			`component ex_stage`
146			`port (`
147			`clk : in std_logic;`
148			`reset : in std_logic;`
149
150			`id_ex_register : in ID_EX_REGISTER_T;`
151			`ex_mem_register : out EX_MEM_REGISTER_T;`
152
153			`branch : out std_logic;`
154			`stall_in : in std_logic;`
155			`clear_in : in std_logic;`
156	94	jlechner	`clear_out : out std_logic;`
157			`clear_locks : out std_logic);`
158	2	jlechner	`end component;`
159
160			`component mem_stage`
161			`port (`
162			`clk : in std_logic;`
163			`reset : in std_logic;`
164
165			`ex_mem_register : in EX_MEM_REGISTER_T;`
166			`mem_wb_register : out MEM_WB_REGISTER_T;`
167
168			`dmem_addr : out MEM_ADDR_T;`
169			`dmem_data_in : in MEM_DATA_T;`
170			`dmem_data_out : out MEM_DATA_T;`
171	39	jlechner	`dmem_wr_enable : out std_logic;`
172	2	jlechner
173			`stall_out : out std_logic;`
174			`clear_in : in std_logic;`
175			`clear_out : out std_logic);`
176			`end component;`
177	16	cwalter
178	2	jlechner	`component wb_stage`
179			`port (`
180			`clk : in std_logic;`
181			`reset : in std_logic;`
182
183			`mem_wb_register : in MEM_WB_REGISTER_T;`
184	16	cwalter
185	2	jlechner	`dreg_addr : out REGISTER_ADDR_T;`
186			`dreg : out REGISTER_T;`
187	27	jlechner	`dreg_enable : out std_logic;`
188	16	cwalter
189	27	jlechner	`lr : out PC_REGISTER_T;`
190	58	cwalter	`lr_enable : out std_logic;`
191	27	jlechner
192	2	jlechner	`sr : out SR_REGISTER_T;`
193	27	jlechner	`sr_enable : out std_logic;`
194	16	cwalter
195	2	jlechner	`clear_out : out std_logic;`
196	16	cwalter
197	39	jlechner	`clear_reg_lock0 : out std_logic;`
198			`lock_reg_addr0 : out REGISTER_ADDR_T;`
199			`clear_reg_lock1 : out std_logic;`
200			`lock_reg_addr1 : out REGISTER_ADDR_T);`
201	2	jlechner	`end component;`
202
203			`component register_file`
204			`port (`
205			`clk : in std_logic;`
206			`reset : in std_logic;`
207
208			`rx_addr : in REGISTER_ADDR_T;`
209			`ry_addr : in REGISTER_ADDR_T;`
210			`rz_addr : in REGISTER_ADDR_T;`
211
212			`rx_read : out REGISTER_T;`
213			`ry_read : out REGISTER_T;`
214			`rz_read : out REGISTER_T;`
215	27	jlechner
216			`dreg_addr : in REGISTER_ADDR_T;`
217			`dreg_write : in REGISTER_T;`
218			`dreg_enable : in std_logic;`
219
220			`sr_read : out SR_REGISTER_T;`
221	2	jlechner	`sr_write : in SR_REGISTER_T;`
222	27	jlechner	`sr_enable : in std_logic;`
223
224	2	jlechner	`lr_write : in PC_REGISTER_T;`
225	27	jlechner	`lr_enable : in std_logic;`
226
227	2	jlechner	`pc_write : in PC_REGISTER_T;`
228			`pc_read : out PC_REGISTER_T);`
229			`end component;`
230
231			`component imem`
232			`port (`
233			`clk : in std_logic;`
234			`reset : in std_logic;`
235	39	jlechner	`wr_enable : in std_logic;`
236	2	jlechner	`addr : in MEM_ADDR_T;`
237			`data_in : in MEM_DATA_T;`
238			`data_out : out MEM_DATA_T);`
239			`end component;`
240
241			`component dmem`
242			`port (`
243			`clk : in std_logic;`
244			`reset : in std_logic;`
245	124	trinklhar	`wr_enable : in std_logic;`
246	2	jlechner	`addr : in MEM_ADDR_T;`
247			`data_in : in MEM_DATA_T;`
248	124	trinklhar	`data_out : out MEM_DATA_T;`
249			`uart_txd : out std_logic;`
250			`uart_rxd : in std_logic);`
251	2	jlechner	`end component;`
252	39	jlechner
253			`component rlu`
254	2	jlechner	`port (`
255	39	jlechner	`clk : in std_logic;`
256			`reset : in std_logic;`
257	94	jlechner	`clear_locks : in std_logic;`
258
259	2	jlechner	`lock_register : out LOCK_REGISTER_T;`
260
261	39	jlechner	`set_lock0 : in std_logic;`
262			`set_lock_addr0 : in REGISTER_ADDR_T;`
263
264			`set_lock1 : in std_logic;`
265			`set_lock_addr1 : in REGISTER_ADDR_T;`
266	16	cwalter
267	39	jlechner	`clear_lock0 : in std_logic;`
268			`clear_lock_addr0 : in REGISTER_ADDR_T;`
269
270			`clear_lock1 : in std_logic;`
271			`clear_lock_addr1 : in REGISTER_ADDR_T);`
272
273	2	jlechner	`end component;`
274
275			`begin -- rise_rtl`
276
277			`if_stage_unit : if_stage`
278			`port map (`
279			`clk => clk,`
280			`reset => reset,`
281
282			`if_id_register => if_id_register_sig,`
283
284			`branch => branch_sig,`
285			`branch_target => branch_target_sig,`
286			`clear_in => clear_in_if_sig,`
287			`stall_in => stall_in_if_sig,`
288
289			`pc => pc_if_sig,`
290			`pc_next => pc_next_if_sig,`
291
292			`imem_addr => imem_addr_sig,`
293			`imem_data => imem_data_sig);`
294
295			`id_stage_unit : id_stage`
296			`port map (`
297			`clk => clk,`
298			`reset => reset,`
299
300			`if_id_register => if_id_register_sig,`
301			`id_ex_register => id_ex_register_sig,`
302
303			`rx_addr => rx_addr_sig,`
304			`ry_addr => ry_addr_sig,`
305			`rz_addr => rz_addr_sig,`
306	16	cwalter
307	2	jlechner	`rx => rx_sig,`
308			`ry => ry_sig,`
309			`rz => rz_sig,`
310			`sr => sr_id_sig,`
311
312			`lock_register => lock_register_sig,`
313	16	cwalter
314	39	jlechner	`set_reg_lock0 => set_lock0_sig,`
315			`lock_reg_addr0 => set_lock_addr0_sig,`
316			`set_reg_lock1 => set_lock1_sig,`
317			`lock_reg_addr1 => set_lock_addr1_sig,`
318
319	2	jlechner	`stall_in => stall_in_id_sig,`
320			`stall_out => stall_out_id_sig,`
321			`clear_in => clear_in_id_sig);`
322
323			`ex_stage_unit : ex_stage`
324			`port map (`
325			`clk => clk,`
326			`reset => reset,`
327
328			`id_ex_register => id_ex_register_sig,`
329			`ex_mem_register => ex_mem_register_sig,`
330
331			`branch => branch_sig,`
332			`stall_in => stall_in_ex_sig,`
333			`clear_in => clear_in_ex_sig,`
334	94	jlechner	`clear_out => clear_out_ex_sig,`
335			`clear_locks => clear_locks_sig);`
336	2	jlechner
337			`mem_stage_unit : mem_stage`
338			`port map (`
339			`clk => clk,`
340			`reset => reset,`
341
342			`ex_mem_register => ex_mem_register_sig,`
343			`mem_wb_register => mem_wb_register_sig,`
344
345			`dmem_addr => dmem_addr_sig,`
346			`dmem_data_in => dmem_data_in_sig,`
347			`dmem_data_out => dmem_data_out_sig,`
348	39	jlechner	`dmem_wr_enable => wr_enable_dmem_sig,`
349
350	2	jlechner	`stall_out => stall_out_mem_sig,`
351			`clear_in => clear_in_mem_sig,`
352			`clear_out => clear_out_mem_sig);`
353	16	cwalter
354	2	jlechner	`wb_stage_unit : wb_stage`
355			`port map (`
356			`clk => clk,`
357			`reset => reset,`
358
359			`mem_wb_register => mem_wb_register_sig,`
360	16	cwalter
361	2	jlechner	`dreg_addr => dreg_addr_sig,`
362			`dreg => dreg_sig,`
363	27	jlechner	`dreg_enable => dreg_enable_sig,`
364	16	cwalter
365	2	jlechner	`lr => lr_sig,`
366	27	jlechner	`lr_enable => lr_enable_sig,`
367
368	2	jlechner	`sr => sr_wb_sig,`
369	27	jlechner	`sr_enable => sr_enable_sig,`
370	16	cwalter
371	2	jlechner	`clear_out => clear_out_wb_sig,`
372	16	cwalter
373	39	jlechner	`clear_reg_lock0 => clear_lock0_sig,`
374			`lock_reg_addr0 => clear_lock_addr0_sig,`
375			`clear_reg_lock1 => clear_lock1_sig,`
376			`lock_reg_addr1 => clear_lock_addr1_sig);`
377	2	jlechner
378			`register_file_unit : register_file`
379			`port map (`
380			`clk => clk,`
381			`reset => reset,`
382
383			`rx_addr => rx_addr_sig,`
384			`ry_addr => ry_addr_sig,`
385			`rz_addr => rz_addr_sig,`
386	27	jlechner
387	2	jlechner	`rx_read => rx_sig,`
388			`ry_read => ry_sig,`
389			`rz_read => rz_sig,`
390	27	jlechner
391			`dreg_addr => dreg_addr_sig,`
392			`dreg_write => dreg_sig,`
393			`dreg_enable => dreg_enable_sig,`
394
395			`sr_read => sr_id_sig,`
396	2	jlechner	`sr_write => sr_wb_sig,`
397	27	jlechner	`sr_enable => sr_enable_sig,`
398
399	2	jlechner	`lr_write => lr_sig,`
400	27	jlechner	`lr_enable => lr_enable_sig,`
401
402	2	jlechner	`pc_write => pc_next_if_sig,`
403			`pc_read => pc_if_sig);`
404
405			`imem_unit : imem`
406			`port map (`
407			`clk => clk,`
408			`reset => reset,`
409	39	jlechner	`wr_enable => wr_enable_imem_sig,`
410	2	jlechner	`addr => imem_addr_sig,`
411			`data_in => data_in_imem_sig,`
412			`data_out => imem_data_sig);`
413	16	cwalter
414	2	jlechner	`dmem_unit : dmem`
415			`port map (`
416			`clk => clk,`
417			`reset => reset,`
418	39	jlechner	`wr_enable => wr_enable_dmem_sig,`
419	2	jlechner	`addr => dmem_addr_sig,`
420			`data_in => dmem_data_out_sig,`
421	124	trinklhar	`data_out => dmem_data_in_sig,`
422			`uart_txd => dmem_txd_sig,`
423			`uart_rxd => dmem_rxd_sig);`
424	16	cwalter
425	39	jlechner	`rlu_unit : rlu port map(`
426			`clk => clk,`
427			`reset => reset,`
428	94	jlechner	`clear_locks => clear_locks_sig,`
429
430	39	jlechner	`lock_register => lock_register_sig,`
431	2	jlechner
432	39	jlechner	`set_lock0 => set_lock0_sig,`
433			`set_lock_addr0 => set_lock_addr0_sig,`
434	2	jlechner
435	39	jlechner	`set_lock1 => set_lock1_sig,`
436			`set_lock_addr1 => set_lock_addr1_sig,`
437
438			`clear_lock0 => clear_lock0_sig,`
439			`clear_lock_addr0 => clear_lock_addr0_sig,`
440
441			`clear_lock1 => clear_lock1_sig,`
442			`clear_lock_addr1 => clear_lock_addr1_sig);`
443
444
445	2	jlechner	`clear_in_if_sig <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;`
446			`clear_in_id_sig <= clear_in_if_sig;`
447			`clear_in_ex_sig <= clear_out_mem_sig or clear_out_wb_sig;`
448			`clear_in_mem_sig <= clear_out_wb_sig;`
449
450			`stall_in_if_sig <= stall_out_id_sig or stall_out_mem_sig;`
451			`stall_in_id_sig <= stall_out_mem_sig;`
452			`stall_in_ex_sig <= stall_out_mem_sig;`
453
454			`branch_target_sig <= ex_mem_register_sig.alu;`
455	39	jlechner
456			`data_in_imem_sig <= (others => '-'); -- unused at the moment`
457			`wr_enable_imem_sig <= '-'; -- unused at the moment`
458
459	124	trinklhar	`-- ports of top level entity`
460			`tx <= dmem_txd_sig;`
461			`dmem_rxd_sig <= rx;`
462
463	2	jlechner	`end rise_rtl;`

Browse

Tools

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [rise.vhd] - Blame information for rev 148