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-------------------------------------------------------------------------------
-- File: rise.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Top-Level entity of RISE CPU
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
 
use WORK.RISE_PACK.all;
 
entity rise is
 
  port (
    clk         : in  std_logic;
    reset       : in std_logic;
    -- uart
    rx          : in  std_logic;
    tx          : out std_logic);
 
end rise;
 
 
architecture rise_rtl of rise is
 
  -- if_stage signals
  signal if_id_register_sig        : IF_ID_REGISTER_T;
  signal branch_sig             : std_logic;
  signal branch_target_sig         : PC_REGISTER_T;
  signal stall_in_if_sig           : std_logic;
  signal clear_in_if_sig           : std_logic;
  signal pc_if_sig                 : PC_REGISTER_T;
  signal pc_next_if_sig            : PC_REGISTER_T;
  signal imem_addr_sig             : MEM_ADDR_T;
  signal imem_data_sig             : MEM_DATA_T;
  -- id_stage signals
  signal id_ex_register_sig        : ID_EX_REGISTER_T;
  signal rx_addr_sig               : REGISTER_ADDR_T;
  signal ry_addr_sig               : REGISTER_ADDR_T;
  signal rz_addr_sig               : REGISTER_ADDR_T;
  signal rx_sig                    : REGISTER_T;
  signal ry_sig                    : REGISTER_T;
  signal rz_sig                    : REGISTER_T;
  signal sr_id_sig                 : SR_REGISTER_T;
  signal lock_register_sig         : LOCK_REGISTER_T;
  signal stall_in_id_sig           : std_logic;
  signal stall_out_id_sig          : std_logic;
  signal clear_in_id_sig           : std_logic;
  -- ex_stage signals
  signal ex_mem_register_sig       :  EX_MEM_REGISTER_T;
  signal stall_in_ex_sig           : std_logic;
  signal clear_in_ex_sig           : std_logic;
  signal clear_out_ex_sig          : std_logic;
  -- mem_stage signals
  signal mem_wb_register_sig       : MEM_WB_REGISTER_T;
  signal dmem_addr_sig             : MEM_ADDR_T;
  signal dmem_data_in_sig          : MEM_DATA_T;
  signal dmem_data_out_sig         : MEM_DATA_T;
  signal stall_out_mem_sig         : std_logic;
  signal clear_in_mem_sig          : std_logic;
  signal clear_out_mem_sig         : std_logic;
  -- wb_stage signals
  signal dreg_addr_sig             : REGISTER_ADDR_T;
  signal dreg_sig                  : REGISTER_T;
  signal dreg_enable_sig           : std_logic;
  signal lr_sig                    : PC_REGISTER_T;
  signal lr_enable_sig             : std_logic;
  signal sr_wb_sig                 : SR_REGISTER_T;
  signal sr_enable_sig             : std_logic;
  signal clear_out_wb_sig          : std_logic;
  -- imem signals
  signal data_in_imem_sig          : MEM_DATA_T;  -- unused at the moment
  signal wr_enable_imem_sig        : std_logic;   -- unused at the moment
  -- dmem signals
  signal wr_enable_dmem_sig        : std_logic;
  -- rlu signals
  signal clear_lock0_sig      : std_logic := '0';
  signal clear_lock_addr0_sig : REGISTER_ADDR_T;
 
  signal clear_lock1_sig      : std_logic := '0';
  signal clear_lock_addr1_sig : REGISTER_ADDR_T;
 
  signal set_lock0_sig      : std_logic := '0';
  signal set_lock_addr0_sig : REGISTER_ADDR_T;
 
  signal set_lock1_sig      : std_logic := '0';
  signal set_lock_addr1_sig : REGISTER_ADDR_T;
 
  component if_stage
    port (
      clk            : in std_logic;
      reset          : in std_logic;
 
      if_id_register : out IF_ID_REGISTER_T;
 
      branch         : in std_logic;
      branch_target  : in PC_REGISTER_T;
      clear_in       : in std_logic;
      stall_in       : in std_logic;
 
      pc             : in PC_REGISTER_T;
      pc_next        : out PC_REGISTER_T;
 
      imem_addr      : out MEM_ADDR_T;
      imem_data      : in MEM_DATA_T);
  end component;
 
  component id_stage
    port (
      clk            : in std_logic;
      reset          : in std_logic;
 
      if_id_register : in IF_ID_REGISTER_T;
      id_ex_register : out ID_EX_REGISTER_T;
 
      rx_addr        : out REGISTER_ADDR_T;
      ry_addr        : out REGISTER_ADDR_T;
      rz_addr        : out REGISTER_ADDR_T;
 
      rx             : in REGISTER_T;
      ry             : in REGISTER_T;
      rz             : in REGISTER_T;
      sr             : in SR_REGISTER_T;
 
      lock_register  : in LOCK_REGISTER_T;
      set_reg_lock0  : out std_logic;
      lock_reg_addr0 : out REGISTER_ADDR_T;
      set_reg_lock1  : out std_logic;
      lock_reg_addr1 : out REGISTER_ADDR_T;
 
      stall_in       : in std_logic;
      stall_out      : out std_logic;
      clear_in       : in std_logic);
  end component;
 
  component ex_stage
    port (
      clk                 : in std_logic;
      reset               : in std_logic;
 
      id_ex_register      : in ID_EX_REGISTER_T;
      ex_mem_register     : out EX_MEM_REGISTER_T;
 
      branch              : out std_logic;
      stall_in            : in std_logic;
      clear_in            : in std_logic;
      clear_out           : out std_logic);
  end component;
 
  component mem_stage
    port (
      clk                 : in std_logic;
      reset               : in std_logic;
 
      ex_mem_register     : in EX_MEM_REGISTER_T;
      mem_wb_register     : out MEM_WB_REGISTER_T;
 
      dmem_addr           : out MEM_ADDR_T;
      dmem_data_in        : in MEM_DATA_T;
      dmem_data_out       : out MEM_DATA_T;
      dmem_wr_enable      : out std_logic;
 
      stall_out           : out std_logic;
      clear_in            : in std_logic;
      clear_out           : out std_logic);
  end component;
 
  component wb_stage
    port (
      clk                 : in std_logic;
      reset               : in std_logic;
 
      mem_wb_register     : in MEM_WB_REGISTER_T;
 
      dreg_addr           : out REGISTER_ADDR_T;
      dreg                : out REGISTER_T;
      dreg_enable         : out std_logic;
 
      lr                  : out PC_REGISTER_T;
      lr_enable           : in std_logic;
 
      sr                  : out SR_REGISTER_T;
      sr_enable           : out std_logic;
 
      clear_out           : out std_logic;
 
      clear_reg_lock0     : out std_logic;
      lock_reg_addr0      : out REGISTER_ADDR_T;
      clear_reg_lock1     : out std_logic;
      lock_reg_addr1      : out REGISTER_ADDR_T);
  end component;
 
  component register_file
    port (
      clk            : in std_logic;
      reset          : in std_logic;
 
      rx_addr        : in REGISTER_ADDR_T;
      ry_addr        : in REGISTER_ADDR_T;
      rz_addr        : in REGISTER_ADDR_T;
 
      rx_read        : out REGISTER_T;
      ry_read        : out REGISTER_T;
      rz_read        : out REGISTER_T;
 
      dreg_addr      : in REGISTER_ADDR_T;
      dreg_write     : in REGISTER_T;
      dreg_enable    : in std_logic;
 
      sr_read        : out SR_REGISTER_T;
      sr_write       : in SR_REGISTER_T;
      sr_enable      : in std_logic;
 
      lr_write       : in PC_REGISTER_T;
      lr_enable      : in std_logic;
 
      pc_write       : in PC_REGISTER_T;
      pc_read        : out PC_REGISTER_T);
  end component;
 
  component imem
    port (
      clk            : in std_logic;
      reset          : in std_logic;
      wr_enable      : in std_logic;
      addr           : in MEM_ADDR_T;
      data_in        : in MEM_DATA_T;
      data_out       : out MEM_DATA_T);
  end component;
 
  component dmem
    port (
      clk            : in std_logic;
      reset          : in std_logic;
      wr_enable      : in std_logic;
      addr           : in MEM_ADDR_T;
      data_in        : in MEM_DATA_T;
      data_out       : out MEM_DATA_T);
  end component;
 
  component rlu
    port (
      clk   : in std_logic;
      reset : in std_logic;
 
      lock_register       : out LOCK_REGISTER_T;
 
      set_lock0           : in std_logic;
      set_lock_addr0      : in REGISTER_ADDR_T;
 
      set_lock1           : in std_logic;
      set_lock_addr1      : in REGISTER_ADDR_T;
 
      clear_lock0         : in std_logic;
      clear_lock_addr0    : in REGISTER_ADDR_T;
 
      clear_lock1         : in std_logic;
      clear_lock_addr1    : in REGISTER_ADDR_T);
 
  end component;
 
begin  -- rise_rtl
 
  if_stage_unit : if_stage
    port map (
      clk            => clk,
      reset          => reset,
 
      if_id_register => if_id_register_sig,
 
      branch         => branch_sig,
      branch_target  => branch_target_sig,
      clear_in       => clear_in_if_sig,
      stall_in       => stall_in_if_sig,
 
      pc             => pc_if_sig,
      pc_next        => pc_next_if_sig,
 
      imem_addr      => imem_addr_sig,
      imem_data      => imem_data_sig);
 
  id_stage_unit : id_stage
    port map (
      clk            => clk,
      reset          => reset,
 
      if_id_register => if_id_register_sig,
      id_ex_register => id_ex_register_sig,
 
      rx_addr        => rx_addr_sig,
      ry_addr        => ry_addr_sig,
      rz_addr        => rz_addr_sig,
 
      rx             => rx_sig,
      ry             => ry_sig,
      rz             => rz_sig,
      sr             => sr_id_sig,
 
      lock_register  => lock_register_sig,
 
      set_reg_lock0  => set_lock0_sig,
      lock_reg_addr0 => set_lock_addr0_sig,
      set_reg_lock1  => set_lock1_sig,
      lock_reg_addr1 => set_lock_addr1_sig,
 
      stall_in       => stall_in_id_sig,
      stall_out      => stall_out_id_sig,
      clear_in       => clear_in_id_sig);
 
  ex_stage_unit : ex_stage
    port map (
      clk                 => clk,
      reset               => reset,
 
      id_ex_register      => id_ex_register_sig,
      ex_mem_register     => ex_mem_register_sig,
 
      branch              => branch_sig,
      stall_in            => stall_in_ex_sig,
      clear_in            => clear_in_ex_sig,
      clear_out           => clear_out_ex_sig);
 
  mem_stage_unit : mem_stage
    port map (
      clk                 => clk,
      reset               => reset,
 
      ex_mem_register     => ex_mem_register_sig,
      mem_wb_register     => mem_wb_register_sig,
 
      dmem_addr           => dmem_addr_sig,
      dmem_data_in        => dmem_data_in_sig,
      dmem_data_out       => dmem_data_out_sig,
      dmem_wr_enable      => wr_enable_dmem_sig,
 
      stall_out           => stall_out_mem_sig,
      clear_in            => clear_in_mem_sig,
      clear_out           => clear_out_mem_sig);
 
  wb_stage_unit : wb_stage
    port map (
      clk                 => clk,
      reset               => reset,
 
      mem_wb_register     => mem_wb_register_sig,
 
      dreg_addr           => dreg_addr_sig,
      dreg                => dreg_sig,
      dreg_enable         => dreg_enable_sig,
 
      lr                  => lr_sig,
      lr_enable           => lr_enable_sig,
 
      sr                  => sr_wb_sig,
      sr_enable           => sr_enable_sig,
 
      clear_out           => clear_out_wb_sig,
 
      clear_reg_lock0     => clear_lock0_sig,
      lock_reg_addr0      => clear_lock_addr0_sig,
      clear_reg_lock1     => clear_lock1_sig,
      lock_reg_addr1      => clear_lock_addr1_sig);
 
  register_file_unit : register_file
    port map (
      clk            => clk,
      reset          => reset,
 
      rx_addr        => rx_addr_sig,
      ry_addr        => ry_addr_sig,
      rz_addr        => rz_addr_sig,
 
      rx_read        => rx_sig,
      ry_read        => ry_sig,
      rz_read        => rz_sig,
 
      dreg_addr      => dreg_addr_sig,
      dreg_write     => dreg_sig,
      dreg_enable    => dreg_enable_sig,
 
      sr_read        => sr_id_sig,
      sr_write       => sr_wb_sig,
      sr_enable      => sr_enable_sig,
 
      lr_write       => lr_sig,
      lr_enable      => lr_enable_sig,
 
      pc_write       => pc_next_if_sig,
      pc_read        => pc_if_sig);
 
  imem_unit : imem
    port map (
      clk            => clk,
      reset          => reset,
      wr_enable      => wr_enable_imem_sig,
      addr           => imem_addr_sig,
      data_in        => data_in_imem_sig,
      data_out       => imem_data_sig);
 
  dmem_unit : dmem
    port map (
      clk            => clk,
      reset          => reset,
      wr_enable      => wr_enable_dmem_sig,
      addr           => dmem_addr_sig,
      data_in        => dmem_data_out_sig,
      data_out       => dmem_data_in_sig);
 
  rlu_unit : rlu port map(
    clk                 => clk,
    reset               => reset,
 
    lock_register       => lock_register_sig,
 
    set_lock0           => set_lock0_sig,
    set_lock_addr0      => set_lock_addr0_sig,
 
    set_lock1           => set_lock1_sig,
    set_lock_addr1      => set_lock_addr1_sig,
 
    clear_lock0         => clear_lock0_sig,
    clear_lock_addr0    => clear_lock_addr0_sig,
 
    clear_lock1         => clear_lock1_sig,
    clear_lock_addr1    => clear_lock_addr1_sig);
 
 
  clear_in_if_sig       <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;
  clear_in_id_sig       <= clear_in_if_sig;
  clear_in_ex_sig       <= clear_out_mem_sig or clear_out_wb_sig;
  clear_in_mem_sig      <= clear_out_wb_sig;
 
  stall_in_if_sig       <= stall_out_id_sig or stall_out_mem_sig;
  stall_in_id_sig       <= stall_out_mem_sig;
  stall_in_ex_sig       <= stall_out_mem_sig;
 
  branch_target_sig     <= ex_mem_register_sig.alu;
 
  data_in_imem_sig      <= (others => '-');  -- unused at the moment
  wr_enable_imem_sig    <= '-';  -- unused at the moment
 
end rise_rtl;

Line No.	Rev	Author	Line
1	2	jlechner	`-------------------------------------------------------------------------------`
2			`-- File: rise.vhd`
3			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
4			`-- Created: 2006-11-29`
5			`-- Last updated: 2006-11-29`
6
7			`-- Description:`
8			`-- Top-Level entity of RISE CPU`
9			`-------------------------------------------------------------------------------`
10
11			`library IEEE;`
12			`use IEEE.STD_LOGIC_1164.all;`
13			`use IEEE.STD_LOGIC_ARITH.all;`
14
15			`use WORK.RISE_PACK.all;`
16
17			`entity rise is`
18
19			`port (`
20			`clk : in std_logic;`
21			`reset : in std_logic;`
22			`-- uart`
23			`rx : in std_logic;`
24			`tx : out std_logic);`
25
26			`end rise;`
27
28
29			`architecture rise_rtl of rise is`
30
31			`-- if_stage signals`
32			`signal if_id_register_sig : IF_ID_REGISTER_T;`
33			`signal branch_sig : std_logic;`
34			`signal branch_target_sig : PC_REGISTER_T;`
35			`signal stall_in_if_sig : std_logic;`
36			`signal clear_in_if_sig : std_logic;`
37			`signal pc_if_sig : PC_REGISTER_T;`
38			`signal pc_next_if_sig : PC_REGISTER_T;`
39			`signal imem_addr_sig : MEM_ADDR_T;`
40			`signal imem_data_sig : MEM_DATA_T;`
41			`-- id_stage signals`
42			`signal id_ex_register_sig : ID_EX_REGISTER_T;`
43			`signal rx_addr_sig : REGISTER_ADDR_T;`
44			`signal ry_addr_sig : REGISTER_ADDR_T;`
45			`signal rz_addr_sig : REGISTER_ADDR_T;`
46			`signal rx_sig : REGISTER_T;`
47			`signal ry_sig : REGISTER_T;`
48			`signal rz_sig : REGISTER_T;`
49			`signal sr_id_sig : SR_REGISTER_T;`
50			`signal lock_register_sig : LOCK_REGISTER_T;`
51			`signal stall_in_id_sig : std_logic;`
52			`signal stall_out_id_sig : std_logic;`
53			`signal clear_in_id_sig : std_logic;`
54			`-- ex_stage signals`
55			`signal ex_mem_register_sig : EX_MEM_REGISTER_T;`
56			`signal stall_in_ex_sig : std_logic;`
57			`signal clear_in_ex_sig : std_logic;`
58			`signal clear_out_ex_sig : std_logic;`
59			`-- mem_stage signals`
60			`signal mem_wb_register_sig : MEM_WB_REGISTER_T;`
61			`signal dmem_addr_sig : MEM_ADDR_T;`
62			`signal dmem_data_in_sig : MEM_DATA_T;`
63			`signal dmem_data_out_sig : MEM_DATA_T;`
64	39	jlechner	`signal stall_out_mem_sig : std_logic;`
65	2	jlechner	`signal clear_in_mem_sig : std_logic;`
66			`signal clear_out_mem_sig : std_logic;`
67			`-- wb_stage signals`
68			`signal dreg_addr_sig : REGISTER_ADDR_T;`
69			`signal dreg_sig : REGISTER_T;`
70	27	jlechner	`signal dreg_enable_sig : std_logic;`
71			`signal lr_sig : PC_REGISTER_T;`
72			`signal lr_enable_sig : std_logic;`
73	2	jlechner	`signal sr_wb_sig : SR_REGISTER_T;`
74	27	jlechner	`signal sr_enable_sig : std_logic;`
75	2	jlechner	`signal clear_out_wb_sig : std_logic;`
76			`-- imem signals`
77			`signal data_in_imem_sig : MEM_DATA_T; -- unused at the moment`
78	39	jlechner	`signal wr_enable_imem_sig : std_logic; -- unused at the moment`
79			`-- dmem signals`
80			`signal wr_enable_dmem_sig : std_logic;`
81			`-- rlu signals`
82			`signal clear_lock0_sig : std_logic := '0';`
83			`signal clear_lock_addr0_sig : REGISTER_ADDR_T;`
84
85			`signal clear_lock1_sig : std_logic := '0';`
86			`signal clear_lock_addr1_sig : REGISTER_ADDR_T;`
87
88			`signal set_lock0_sig : std_logic := '0';`
89			`signal set_lock_addr0_sig : REGISTER_ADDR_T;`
90
91			`signal set_lock1_sig : std_logic := '0';`
92			`signal set_lock_addr1_sig : REGISTER_ADDR_T;`
93	2	jlechner
94			`component if_stage`
95			`port (`
96			`clk : in std_logic;`
97			`reset : in std_logic;`
98
99			`if_id_register : out IF_ID_REGISTER_T;`
100
101			`branch : in std_logic;`
102			`branch_target : in PC_REGISTER_T;`
103			`clear_in : in std_logic;`
104			`stall_in : in std_logic;`
105
106			`pc : in PC_REGISTER_T;`
107			`pc_next : out PC_REGISTER_T;`
108
109			`imem_addr : out MEM_ADDR_T;`
110			`imem_data : in MEM_DATA_T);`
111			`end component;`
112
113			`component id_stage`
114			`port (`
115			`clk : in std_logic;`
116			`reset : in std_logic;`
117
118			`if_id_register : in IF_ID_REGISTER_T;`
119			`id_ex_register : out ID_EX_REGISTER_T;`
120
121			`rx_addr : out REGISTER_ADDR_T;`
122			`ry_addr : out REGISTER_ADDR_T;`
123			`rz_addr : out REGISTER_ADDR_T;`
124	16	cwalter
125	2	jlechner	`rx : in REGISTER_T;`
126			`ry : in REGISTER_T;`
127			`rz : in REGISTER_T;`
128			`sr : in SR_REGISTER_T;`
129
130			`lock_register : in LOCK_REGISTER_T;`
131	16	cwalter	`set_reg_lock0 : out std_logic;`
132			`lock_reg_addr0 : out REGISTER_ADDR_T;`
133			`set_reg_lock1 : out std_logic;`
134			`lock_reg_addr1 : out REGISTER_ADDR_T;`
135
136	2	jlechner	`stall_in : in std_logic;`
137			`stall_out : out std_logic;`
138			`clear_in : in std_logic);`
139			`end component;`
140
141			`component ex_stage`
142			`port (`
143			`clk : in std_logic;`
144			`reset : in std_logic;`
145
146			`id_ex_register : in ID_EX_REGISTER_T;`
147			`ex_mem_register : out EX_MEM_REGISTER_T;`
148
149			`branch : out std_logic;`
150			`stall_in : in std_logic;`
151			`clear_in : in std_logic;`
152			`clear_out : out std_logic);`
153			`end component;`
154
155			`component mem_stage`
156			`port (`
157			`clk : in std_logic;`
158			`reset : in std_logic;`
159
160			`ex_mem_register : in EX_MEM_REGISTER_T;`
161			`mem_wb_register : out MEM_WB_REGISTER_T;`
162
163			`dmem_addr : out MEM_ADDR_T;`
164			`dmem_data_in : in MEM_DATA_T;`
165			`dmem_data_out : out MEM_DATA_T;`
166	39	jlechner	`dmem_wr_enable : out std_logic;`
167	2	jlechner
168			`stall_out : out std_logic;`
169			`clear_in : in std_logic;`
170			`clear_out : out std_logic);`
171			`end component;`
172	16	cwalter
173	2	jlechner	`component wb_stage`
174			`port (`
175			`clk : in std_logic;`
176			`reset : in std_logic;`
177
178			`mem_wb_register : in MEM_WB_REGISTER_T;`
179	16	cwalter
180	2	jlechner	`dreg_addr : out REGISTER_ADDR_T;`
181			`dreg : out REGISTER_T;`
182	27	jlechner	`dreg_enable : out std_logic;`
183	16	cwalter
184	27	jlechner	`lr : out PC_REGISTER_T;`
185			`lr_enable : in std_logic;`
186
187	2	jlechner	`sr : out SR_REGISTER_T;`
188	27	jlechner	`sr_enable : out std_logic;`
189	16	cwalter
190	2	jlechner	`clear_out : out std_logic;`
191	16	cwalter
192	39	jlechner	`clear_reg_lock0 : out std_logic;`
193			`lock_reg_addr0 : out REGISTER_ADDR_T;`
194			`clear_reg_lock1 : out std_logic;`
195			`lock_reg_addr1 : out REGISTER_ADDR_T);`
196	2	jlechner	`end component;`
197
198			`component register_file`
199			`port (`
200			`clk : in std_logic;`
201			`reset : in std_logic;`
202
203			`rx_addr : in REGISTER_ADDR_T;`
204			`ry_addr : in REGISTER_ADDR_T;`
205			`rz_addr : in REGISTER_ADDR_T;`
206
207			`rx_read : out REGISTER_T;`
208			`ry_read : out REGISTER_T;`
209			`rz_read : out REGISTER_T;`
210	27	jlechner
211			`dreg_addr : in REGISTER_ADDR_T;`
212			`dreg_write : in REGISTER_T;`
213			`dreg_enable : in std_logic;`
214
215			`sr_read : out SR_REGISTER_T;`
216	2	jlechner	`sr_write : in SR_REGISTER_T;`
217	27	jlechner	`sr_enable : in std_logic;`
218
219	2	jlechner	`lr_write : in PC_REGISTER_T;`
220	27	jlechner	`lr_enable : in std_logic;`
221
222	2	jlechner	`pc_write : in PC_REGISTER_T;`
223			`pc_read : out PC_REGISTER_T);`
224			`end component;`
225
226			`component imem`
227			`port (`
228			`clk : in std_logic;`
229			`reset : in std_logic;`
230	39	jlechner	`wr_enable : in std_logic;`
231	2	jlechner	`addr : in MEM_ADDR_T;`
232			`data_in : in MEM_DATA_T;`
233			`data_out : out MEM_DATA_T);`
234			`end component;`
235
236			`component dmem`
237			`port (`
238			`clk : in std_logic;`
239			`reset : in std_logic;`
240	39	jlechner	`wr_enable : in std_logic;`
241	2	jlechner	`addr : in MEM_ADDR_T;`
242			`data_in : in MEM_DATA_T;`
243			`data_out : out MEM_DATA_T);`
244			`end component;`
245	39	jlechner
246			`component rlu`
247	2	jlechner	`port (`
248	39	jlechner	`clk : in std_logic;`
249			`reset : in std_logic;`
250	2	jlechner
251			`lock_register : out LOCK_REGISTER_T;`
252
253	39	jlechner	`set_lock0 : in std_logic;`
254			`set_lock_addr0 : in REGISTER_ADDR_T;`
255
256			`set_lock1 : in std_logic;`
257			`set_lock_addr1 : in REGISTER_ADDR_T;`
258	16	cwalter
259	39	jlechner	`clear_lock0 : in std_logic;`
260			`clear_lock_addr0 : in REGISTER_ADDR_T;`
261
262			`clear_lock1 : in std_logic;`
263			`clear_lock_addr1 : in REGISTER_ADDR_T);`
264
265	2	jlechner	`end component;`
266
267			`begin -- rise_rtl`
268
269			`if_stage_unit : if_stage`
270			`port map (`
271			`clk => clk,`
272			`reset => reset,`
273
274			`if_id_register => if_id_register_sig,`
275
276			`branch => branch_sig,`
277			`branch_target => branch_target_sig,`
278			`clear_in => clear_in_if_sig,`
279			`stall_in => stall_in_if_sig,`
280
281			`pc => pc_if_sig,`
282			`pc_next => pc_next_if_sig,`
283
284			`imem_addr => imem_addr_sig,`
285			`imem_data => imem_data_sig);`
286
287			`id_stage_unit : id_stage`
288			`port map (`
289			`clk => clk,`
290			`reset => reset,`
291
292			`if_id_register => if_id_register_sig,`
293			`id_ex_register => id_ex_register_sig,`
294
295			`rx_addr => rx_addr_sig,`
296			`ry_addr => ry_addr_sig,`
297			`rz_addr => rz_addr_sig,`
298	16	cwalter
299	2	jlechner	`rx => rx_sig,`
300			`ry => ry_sig,`
301			`rz => rz_sig,`
302			`sr => sr_id_sig,`
303
304			`lock_register => lock_register_sig,`
305	16	cwalter
306	39	jlechner	`set_reg_lock0 => set_lock0_sig,`
307			`lock_reg_addr0 => set_lock_addr0_sig,`
308			`set_reg_lock1 => set_lock1_sig,`
309			`lock_reg_addr1 => set_lock_addr1_sig,`
310
311	2	jlechner	`stall_in => stall_in_id_sig,`
312			`stall_out => stall_out_id_sig,`
313			`clear_in => clear_in_id_sig);`
314
315			`ex_stage_unit : ex_stage`
316			`port map (`
317			`clk => clk,`
318			`reset => reset,`
319
320			`id_ex_register => id_ex_register_sig,`
321			`ex_mem_register => ex_mem_register_sig,`
322
323			`branch => branch_sig,`
324			`stall_in => stall_in_ex_sig,`
325			`clear_in => clear_in_ex_sig,`
326			`clear_out => clear_out_ex_sig);`
327
328			`mem_stage_unit : mem_stage`
329			`port map (`
330			`clk => clk,`
331			`reset => reset,`
332
333			`ex_mem_register => ex_mem_register_sig,`
334			`mem_wb_register => mem_wb_register_sig,`
335
336			`dmem_addr => dmem_addr_sig,`
337			`dmem_data_in => dmem_data_in_sig,`
338			`dmem_data_out => dmem_data_out_sig,`
339	39	jlechner	`dmem_wr_enable => wr_enable_dmem_sig,`
340
341	2	jlechner	`stall_out => stall_out_mem_sig,`
342			`clear_in => clear_in_mem_sig,`
343			`clear_out => clear_out_mem_sig);`
344	16	cwalter
345	2	jlechner	`wb_stage_unit : wb_stage`
346			`port map (`
347			`clk => clk,`
348			`reset => reset,`
349
350			`mem_wb_register => mem_wb_register_sig,`
351	16	cwalter
352	2	jlechner	`dreg_addr => dreg_addr_sig,`
353			`dreg => dreg_sig,`
354	27	jlechner	`dreg_enable => dreg_enable_sig,`
355	16	cwalter
356	2	jlechner	`lr => lr_sig,`
357	27	jlechner	`lr_enable => lr_enable_sig,`
358
359	2	jlechner	`sr => sr_wb_sig,`
360	27	jlechner	`sr_enable => sr_enable_sig,`
361	16	cwalter
362	2	jlechner	`clear_out => clear_out_wb_sig,`
363	16	cwalter
364	39	jlechner	`clear_reg_lock0 => clear_lock0_sig,`
365			`lock_reg_addr0 => clear_lock_addr0_sig,`
366			`clear_reg_lock1 => clear_lock1_sig,`
367			`lock_reg_addr1 => clear_lock_addr1_sig);`
368	2	jlechner
369			`register_file_unit : register_file`
370			`port map (`
371			`clk => clk,`
372			`reset => reset,`
373
374			`rx_addr => rx_addr_sig,`
375			`ry_addr => ry_addr_sig,`
376			`rz_addr => rz_addr_sig,`
377	27	jlechner
378	2	jlechner	`rx_read => rx_sig,`
379			`ry_read => ry_sig,`
380			`rz_read => rz_sig,`
381	27	jlechner
382			`dreg_addr => dreg_addr_sig,`
383			`dreg_write => dreg_sig,`
384			`dreg_enable => dreg_enable_sig,`
385
386			`sr_read => sr_id_sig,`
387	2	jlechner	`sr_write => sr_wb_sig,`
388	27	jlechner	`sr_enable => sr_enable_sig,`
389
390	2	jlechner	`lr_write => lr_sig,`
391	27	jlechner	`lr_enable => lr_enable_sig,`
392
393	2	jlechner	`pc_write => pc_next_if_sig,`
394			`pc_read => pc_if_sig);`
395
396			`imem_unit : imem`
397			`port map (`
398			`clk => clk,`
399			`reset => reset,`
400	39	jlechner	`wr_enable => wr_enable_imem_sig,`
401	2	jlechner	`addr => imem_addr_sig,`
402			`data_in => data_in_imem_sig,`
403			`data_out => imem_data_sig);`
404	16	cwalter
405	2	jlechner	`dmem_unit : dmem`
406			`port map (`
407			`clk => clk,`
408			`reset => reset,`
409	39	jlechner	`wr_enable => wr_enable_dmem_sig,`
410	2	jlechner	`addr => dmem_addr_sig,`
411			`data_in => dmem_data_out_sig,`
412			`data_out => dmem_data_in_sig);`
413	16	cwalter
414	39	jlechner	`rlu_unit : rlu port map(`
415			`clk => clk,`
416			`reset => reset,`
417	2	jlechner
418	39	jlechner	`lock_register => lock_register_sig,`
419	2	jlechner
420	39	jlechner	`set_lock0 => set_lock0_sig,`
421			`set_lock_addr0 => set_lock_addr0_sig,`
422	2	jlechner
423	39	jlechner	`set_lock1 => set_lock1_sig,`
424			`set_lock_addr1 => set_lock_addr1_sig,`
425
426			`clear_lock0 => clear_lock0_sig,`
427			`clear_lock_addr0 => clear_lock_addr0_sig,`
428
429			`clear_lock1 => clear_lock1_sig,`
430			`clear_lock_addr1 => clear_lock_addr1_sig);`
431
432
433	2	jlechner	`clear_in_if_sig <= clear_out_ex_sig or clear_out_mem_sig or clear_out_wb_sig;`
434			`clear_in_id_sig <= clear_in_if_sig;`
435			`clear_in_ex_sig <= clear_out_mem_sig or clear_out_wb_sig;`
436			`clear_in_mem_sig <= clear_out_wb_sig;`
437
438			`stall_in_if_sig <= stall_out_id_sig or stall_out_mem_sig;`
439			`stall_in_id_sig <= stall_out_mem_sig;`
440			`stall_in_ex_sig <= stall_out_mem_sig;`
441
442			`branch_target_sig <= ex_mem_register_sig.alu;`
443	39	jlechner
444			`data_in_imem_sig <= (others => '-'); -- unused at the moment`
445			`wr_enable_imem_sig <= '-'; -- unused at the moment`
446
447	2	jlechner	`end rise_rtl;`

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