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jlechner |
-------------------------------------------------------------------------------
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-- File: rise_pack.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Package for RISE project.
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package RISE_PACK is
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constant ARCHITECTURE_WIDTH : integer := 16;
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constant REGISTER_COUNT : integer := 16;
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constant PC_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant IR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant SR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant OPCODE_WIDTH : integer := 5;
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constant COND_WIDTH : integer := 3;
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constant MEM_DATA_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant MEM_ADDR_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant REGISTER_WIDTH : integer := ARCHITECTURE_WIDTH;
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cwalter |
constant REGISTER_ADDR_WIDTH : integer := 4;
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constant IMMEDIATE_WIDTH : integer := ARCHITECTURE_WIDTH;
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constant LOCK_WIDTH : integer := REGISTER_COUNT;
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subtype PC_REGISTER_T is std_logic_vector(PC_WIDTH-1 downto 0);
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subtype IR_REGISTER_T is std_logic_vector(IR_WIDTH-1 downto 0);
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subtype SR_REGISTER_T is std_logic_vector(SR_WIDTH-1 downto 0);
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subtype REGISTER_T is std_logic_vector(REGISTER_WIDTH-1 downto 0);
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subtype REGISTER_ADDR_T is std_logic_vector(REGISTER_ADDR_WIDTH-1 downto 0);
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subtype MEM_DATA_T is std_logic_vector(MEM_DATA_WIDTH-1 downto 0);
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subtype MEM_ADDR_T is std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
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subtype LOCK_REGISTER_T is std_logic_vector(LOCK_WIDTH-1 downto 0);
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subtype IMMEDIATE_T is std_logic_vector(IMMEDIATE_WIDTH-1 downto 0);
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subtype OPCODE_T is std_logic_vector(OPCODE_WIDTH-1 downto 0);
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subtype COND_T is std_logic_vector(COND_WIDTH-1 downto 0);
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--
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constant SR_REGISTER_DI : INTEGER := 15;
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constant SR_REGISTER_IP_MASK : INTEGER := 12;
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constant SR_REGISTER_OVERFLOW : INTEGER := 3;
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constant SR_REGISTER_NEGATIVE : INTEGER := 2;
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constant SR_REGISTER_CARRY : INTEGER := 1;
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constant SR_REGISTER_ZERO : INTEGER := 0;
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constant RESET_PC_VALUE : PC_REGISTER_T := ( others => '0' );
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constant RESET_SR_VALUE : PC_REGISTER_T := ( others => '0' );
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constant COND_NONE : COND_T := "000";
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-- RISE OPCODES --
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constant OPCODE_LD_IMM : OPCODE_T := "10000";
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constant OPCODE_LD_DISP : OPCODE_T := "10100";
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constant OPCODE_LD_DISP_MS : OPCODE_T := "11000";
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constant OPCODE_LD_REG : OPCODE_T := "00001";
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constant OPCODE_NOP : OPCODE_T := "00000";
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jlechner |
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type IF_ID_REGISTER_T is record
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pc : PC_REGISTER_T;
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ir : IR_REGISTER_T;
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end record;
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type ID_EX_REGISTER_T is record
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sr : SR_REGISTER_T;
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pc : PC_REGISTER_T;
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opcode : OPCODE_T;
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cond : COND_T;
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rX_addr : REGISTER_ADDR_T;
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rX : REGISTER_T;
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rY : REGISTER_T;
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rZ : REGISTER_T;
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immediate : IMMEDIATE_T;
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end record;
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type EX_MEM_REGISTER_T is record
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aluop1 : std_logic_vector(2 downto 0);
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aluop2 : std_logic_vector(2 downto 0);
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reg : REGISTER_T;
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alu : REGISTER_T;
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dreg_addr : REGISTER_ADDR_T;
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lr : PC_REGISTER_T;
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end record;
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type MEM_WB_REGISTER_T is record
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aluop1 : std_logic_vector(2 downto 0);
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aluop2 : std_logic_vector(2 downto 0);
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reg : REGISTER_T;
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dreg_addr : REGISTER_ADDR_T;
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lr : PC_REGISTER_T;
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end record;
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end RISE_PACK;
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