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jlechner |
-------------------------------------------------------------------------------
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-- File: ex_stage.vhd
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-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
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-- Created: 2006-11-29
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-- Last updated: 2006-11-29
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-- Description:
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-- Execute stage
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use work.rise_pack.all;
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71 |
jlechner |
use work.RISE_PACK_SPECIFIC.all;
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8 |
jlechner |
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entity tb_ex_stage_unit_vhd is
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end tb_ex_stage_unit_vhd;
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architecture behavior of tb_ex_stage_unit_vhd is
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-- component Declaration for the Unit Under Test (UUT)
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component ex_stage is
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port (
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clk : in std_logic;
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reset : in std_logic;
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id_ex_register : in ID_EX_REGISTER_T;
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ex_mem_register : out EX_MEM_REGISTER_T;
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branch : out std_logic;
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stall_in : in std_logic;
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clear_in : in std_logic;
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clear_out : out std_logic);
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end component;
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constant clk_period : time := 10 ns;
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--inputs
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal id_ex_register : ID_EX_REGISTER_T;
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signal stall_in : std_logic := '0';
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signal clear_in : std_logic := '0';
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--Outputs
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signal ex_mem_register : EX_MEM_REGISTER_T;
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signal branch : std_logic;
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signal clear_out : std_logic;
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begin
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-- instantiate the Unit Under Test (UUT)
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uut : ex_stage port map(
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clk => clk,
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reset => reset,
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id_ex_register => id_ex_register,
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ex_mem_register => ex_mem_register,
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branch => branch,
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stall_in => stall_in,
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clear_in => clear_in,
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clear_out => clear_out);
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cg : process
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begin
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clk <= '1';
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wait for clk_period/2;
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clk <= '0';
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wait for clk_period/2;
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end process;
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tb : process
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begin
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reset <= '0';
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wait for 10 * clk_period;
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reset <= '1';
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id_ex_register.sr <= (others => '0');
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id_ex_register.pc <= CONV_STD_LOGIC_VECTOR(3, PC_WIDTH);
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id_ex_register.opcode <= OPCODE_NOP;
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id_ex_register.cond <= COND_UNCONDITIONAL;
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id_ex_register.rX_addr <= CONV_STD_LOGIC_VECTOR(2, REGISTER_ADDR_WIDTH);
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH);
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id_ex_register.rZ <= CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH);
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(0, IMMEDIATE_WIDTH);
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---------------------------------------------------------------------------
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-- test computation results
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---------------------------------------------------------------------------
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-- load/store
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_LD_IMM;
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(1, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_LD_IMM_HB;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(1, REGISTER_WIDTH);
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_LD_DISP;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rZ <= CONV_STD_LOGIC_VECTOR(1, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_LD_DISP_MS;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rZ <= CONV_STD_LOGIC_VECTOR(1, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_LD_REG;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(6, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ST_DISP;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rZ <= CONV_STD_LOGIC_VECTOR(1, REGISTER_WIDTH);
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wait for clk_period;
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-- arithmetic opcodes
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id_ex_register.opcode <= OPCODE_ADD;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(8, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(3, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ADD;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(-8, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ADD_IMM;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(3, REGISTER_WIDTH);
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ADD_IMM;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(3, REGISTER_WIDTH);
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(-2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_SUB;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_SUB;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(6, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_SUB_IMM;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(-4, REGISTER_WIDTH);
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(6, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_SUB_IMM;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.immediate <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_NEG;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ARS;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ALS;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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-- als with overflow
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ALS;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(30000, REGISTER_WIDTH);
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-- als with overflow
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_ALS;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(-30000, REGISTER_WIDTH);
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-- logical opcodes
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_AND;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_NOT;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_EOR;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(4, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_LS;
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cwalter |
id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(3, REGISTER_WIDTH);
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jlechner |
id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_RS;
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cwalter |
id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(73, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(1, REGISTER_WIDTH);
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8 |
jlechner |
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-- other
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wait for clk_period;
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id_ex_register.opcode <= OPCODE_JMP;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(8, REGISTER_WIDTH);
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---------------------------------------------------------------------------
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-- test stall/clear
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---------------------------------------------------------------------------
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wait for clk_period;
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stall_in <= '1';
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id_ex_register.opcode <= OPCODE_JMP;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(8, REGISTER_WIDTH);
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wait for clk_period;
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stall_in <= '0';
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id_ex_register.rX_addr <= CONV_STD_LOGIC_VECTOR(6, REGISTER_ADDR_WIDTH);
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id_ex_register.opcode <= OPCODE_LD_REG;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(6, REGISTER_WIDTH);
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wait for clk_period;
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clear_in <= '1';
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wait for clk_period;
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clear_in <= '0';
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---------------------------------------------------------------------------
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-- branch (i.e. load instruction with PC as destination)
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---------------------------------------------------------------------------
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wait for clk_period;
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id_ex_register.rX_addr <= PC_ADDR;
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id_ex_register.opcode <= OPCODE_LD_REG;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(6, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.rX_addr <= CONV_STD_LOGIC_VECTOR(6, REGISTER_ADDR_WIDTH);
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id_ex_register.opcode <= OPCODE_LD_REG;
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(6, REGISTER_WIDTH);
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---------------------------------------------------------------------------
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-- test conditionals
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---------------------------------------------------------------------------
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wait for clk_period;
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id_ex_register.cond <= COND_ZERO;
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id_ex_register.sr <= (SR_ZERO_BIT => '0', others => '0');
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id_ex_register.opcode <= OPCODE_ADD;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(8, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(3, REGISTER_WIDTH);
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wait for clk_period;
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id_ex_register.cond <= COND_UNCONDITIONAL;
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id_ex_register.opcode <= OPCODE_ADD;
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id_ex_register.rX <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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id_ex_register.rY <= CONV_STD_LOGIC_VECTOR(2, REGISTER_WIDTH);
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wait; -- will wait forever
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end process;
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end;
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