URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [tb_id_stage_unit.vhd] - Blame information for rev 148

Details | Compare with Previous | View Log


-- File: ex_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Execute stage
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.rise_pack.all;
use work.RISE_PACK_SPECIFIC.all;
 
entity tb_id_stage_unit_vhd is
end tb_id_stage_unit_vhd;
 
architecture behavior of tb_id_stage_unit_vhd is
 
  -- component Declaration for the Unit Under Test (UUT)
  component id_stage
    port(
      clk   : in std_logic;
      reset : in std_logic;
 
      if_id_register : in  IF_ID_REGISTER_T;
      id_ex_register : out ID_EX_REGISTER_T;
 
      rx_addr : out REGISTER_ADDR_T;
      ry_addr : out REGISTER_ADDR_T;
      rz_addr : out REGISTER_ADDR_T;
 
      rx : in REGISTER_T;
      ry : in REGISTER_T;
      rz : in REGISTER_T;
      sr : in SR_REGISTER_T;
 
      lock_register  : in  LOCK_REGISTER_T;
      set_reg_lock0  : out std_logic;
      lock_reg_addr0 : out REGISTER_ADDR_T;
      set_reg_lock1  : out std_logic;
      lock_reg_addr1 : out REGISTER_ADDR_T;
 
      stall_in  : in  std_logic;
      stall_out : out std_logic;
      clear_in  : in  std_logic
      );
  end component;
 
  --inputs
  signal clk            : std_logic := '0';
  signal reset          : std_logic := '0';
  signal if_id_register : IF_ID_REGISTER_T;
 
  signal stall_in       : std_logic := '0';
  signal clear_in       : std_logic := '0';
  signal rx             : REGISTER_T;
  signal ry             : REGISTER_T;
  signal rz             : REGISTER_T;
  signal sr             : SR_REGISTER_T;
  signal lock_register  : LOCK_REGISTER_T := ( others => '0' );
  --Outputs
  signal id_ex_register : ID_EX_REGISTER_T;
  signal rx_addr        : REGISTER_ADDR_T;
  signal ry_addr        : REGISTER_ADDR_T;
  signal rz_addr        : REGISTER_ADDR_T;
  signal set_reg_lock0  : std_logic;
  signal lock_reg_addr0 : REGISTER_ADDR_T;
  signal set_reg_lock1  : std_logic;
  signal lock_reg_addr1 : REGISTER_ADDR_T;
  signal stall_out      : std_logic;
 
  constant TB_COND_TEST_VALUE : COND_T := COND_UNCONDITIONAL;
 
  constant TB_R1_TEST_VALUE : REGISTER_T := x"0001";
  constant TB_R2_TEST_VALUE : REGISTER_T := x"0002";
  constant TB_R3_TEST_VALUE : REGISTER_T := x"0003";
 
  constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
  constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
 
  constant TB_CLOCK : time := 20 ns;
begin
 
  -- instantiate the Unit Under Test (UUT)
  uut : id_stage port map(
    clk            => clk,
    reset          => reset,
    if_id_register => if_id_register,
    id_ex_register => id_ex_register,
    rx_addr        => rx_addr,
    ry_addr        => ry_addr,
    rz_addr        => rz_addr,
    rx             => rx,
    ry             => ry,
    rz             => rz,
    sr             => sr,
    lock_register  => lock_register,
    set_reg_lock0  => set_reg_lock0,
    lock_reg_addr0 => lock_reg_addr0,
    set_reg_lock1  => set_reg_lock1,
    lock_reg_addr1 => lock_reg_addr1,
    stall_in       => stall_in,
    stall_out      => stall_out,
    clear_in       => clear_in
    );
 
  cg : process
  begin
    clk <= '0';
    wait for TB_CLOCK/2;
    clk <= '1';
    wait for TB_CLOCK/2;
  end process;
 
  regfile : process(rx_addr, ry_addr, rz_addr)
  begin
    case rx_addr is
      when x"1"   => rx <= TB_R1_TEST_VALUE;
      when x"2"   => rx <= TB_R2_TEST_VALUE;
      when x"3"   => rx <= TB_R3_TEST_VALUE;
      when others => rz <= (others => 'X');
    end case;
 
    case ry_addr is
      when x"1"   => ry <= TB_R1_TEST_VALUE;
      when x"2"   => ry <= TB_R2_TEST_VALUE;
      when x"3"   => ry <= TB_R3_TEST_VALUE;
      when others => rz <= (others => 'X');
    end case;
 
    case rz_addr is
      when x"1"   => rz <= TB_R1_TEST_VALUE;
      when x"2"   => rz <= TB_R2_TEST_VALUE;
      when x"3"   => rz <= TB_R3_TEST_VALUE;
      when others => rz <= (others => 'X');
    end case;
 
    sr <= TB_SR_TEST_VALUE;
 
  end process;
 
  tb : process
  begin
    reset <= '0';
    wait for 100 ns;
    reset <= '1';
 
    -- test case: basic functionallity
    if_id_register.pc <= TB_PC_TEST_VALUE;
    wait for TB_CLOCK;
 
    -- test case: OPCODE_LD_IMM 
    if_id_register.ir <= "100"& "0" & x"1" & x"55";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_IMM;
    assert id_ex_register.immediate = x"0055";
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"1";
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_IMM_HB
    if_id_register.ir <= "100"& "1" & x"1" & x"55";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
    assert id_ex_register.immediate = x"5500";
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"1";
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_IMM_HB
    if_id_register.ir <= "100"& "1" & x"1" & x"55";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
    assert id_ex_register.immediate = x"5500";
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"1";
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_DISP
    if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_DISP;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
    assert id_ex_register.cond = TB_COND_TEST_VALUE;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert rz_addr = x"3";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_DISP_MS
    if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_DISP_MS;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
    assert id_ex_register.cond = TB_COND_TEST_VALUE;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert rz_addr = x"3";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_REG
    if_id_register.ir <= "00001" & "001" & x"2" & x"1";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_REG;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
    assert id_ex_register.cond = COND_NOT_ZERO;
    assert rx_addr = x"2";
    assert ry_addr = x"1";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_REG WITH STALL
    lock_register(1) <= '1';
    if_id_register.ir <= "00001" & "001" & x"2" & x"1";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_REG;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
    assert id_ex_register.cond = COND_NOT_ZERO;
    assert rx_addr = x"2";
    assert ry_addr = x"1";
    assert stall_out = '1';
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
    lock_register(1) <= '0';
 
    -- test case: OPCODE_ST_DISP
    if_id_register.ir <= "111" & "100" & "11" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ST_DISP;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
    assert id_ex_register.cond = COND_NEGATIVE;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert rz_addr = x"3";
 
    -- test case: OPCODE_ADD
    if_id_register.ir <= "00010" & "000" & x"3" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ADD;
    assert id_ex_register.rX_addr = x"3";
    assert id_ex_register.rX = TB_R3_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"3";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_ADD_IMM
    if_id_register.ir <= "00011" & "010" & x"2" & x"5";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ADD_IMM;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.immediate = x"0005";
    assert id_ex_register.cond = COND_ZERO;
    assert rx_addr = x"2";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_SUB
    if_id_register.ir <= "00100" & "011" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_SUB;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_CARRY;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_SUB_IMM
    if_id_register.ir <= "00101" & "100" & x"1" & x"A";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_SUB_IMM;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.immediate = x"000A";
    assert id_ex_register.cond = COND_NEGATIVE;
    assert rx_addr = x"1";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_NEG
    if_id_register.ir <= "00110" & "101" & x"2" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_NEG;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_OVERFLOW;
    assert rx_addr = x"2";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_ARS
    if_id_register.ir <= "00111" & "110" & x"3" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ARS;
    assert id_ex_register.rX_addr = x"3";
    assert id_ex_register.rX = TB_R3_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_ZERO_NEGATIVE;
    assert rx_addr = x"3";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_ALS
    if_id_register.ir <= "01000" & "000" & x"2" & x"1";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ALS;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"2";
    assert ry_addr = x"1";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
 
    wait;
  end process;
 
end;

Line No.	Rev	Author	Line
1	7	cwalter	`-- File: ex_stage.vhd`
2			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
3			`-- Created: 2006-11-29`
4			`-- Last updated: 2006-11-29`
5
6			`-- Description:`
7			`-- Execute stage`
8			`-------------------------------------------------------------------------------`
9
10			`library ieee;`
11			`use ieee.std_logic_1164.all;`
12			`use ieee.std_logic_unsigned.all;`
13			`use ieee.numeric_std.all;`
14			`use work.rise_pack.all;`
15	71	jlechner	`use work.RISE_PACK_SPECIFIC.all;`
16	7	cwalter
17			`entity tb_id_stage_unit_vhd is`
18			`end tb_id_stage_unit_vhd;`
19
20			`architecture behavior of tb_id_stage_unit_vhd is`
21
22			`-- component Declaration for the Unit Under Test (UUT)`
23			`component id_stage`
24			`port(`
25			`clk : in std_logic;`
26			`reset : in std_logic;`
27
28			`if_id_register : in IF_ID_REGISTER_T;`
29			`id_ex_register : out ID_EX_REGISTER_T;`
30
31			`rx_addr : out REGISTER_ADDR_T;`
32			`ry_addr : out REGISTER_ADDR_T;`
33			`rz_addr : out REGISTER_ADDR_T;`
34
35			`rx : in REGISTER_T;`
36			`ry : in REGISTER_T;`
37			`rz : in REGISTER_T;`
38			`sr : in SR_REGISTER_T;`
39
40	17	cwalter	`lock_register : in LOCK_REGISTER_T;`
41			`set_reg_lock0 : out std_logic;`
42			`lock_reg_addr0 : out REGISTER_ADDR_T;`
43			`set_reg_lock1 : out std_logic;`
44			`lock_reg_addr1 : out REGISTER_ADDR_T;`
45
46	7	cwalter	`stall_in : in std_logic;`
47			`stall_out : out std_logic;`
48			`clear_in : in std_logic`
49			`);`
50			`end component;`
51
52			`--inputs`
53			`signal clk : std_logic := '0';`
54			`signal reset : std_logic := '0';`
55			`signal if_id_register : IF_ID_REGISTER_T;`
56
57	13	cwalter	`signal stall_in : std_logic := '0';`
58			`signal clear_in : std_logic := '0';`
59	10	cwalter	`signal rx : REGISTER_T;`
60			`signal ry : REGISTER_T;`
61			`signal rz : REGISTER_T;`
62			`signal sr : SR_REGISTER_T;`
63	17	cwalter	`signal lock_register : LOCK_REGISTER_T := ( others => '0' );`
64	7	cwalter	`--Outputs`
65			`signal id_ex_register : ID_EX_REGISTER_T;`
66	17	cwalter	`signal rx_addr : REGISTER_ADDR_T;`
67			`signal ry_addr : REGISTER_ADDR_T;`
68			`signal rz_addr : REGISTER_ADDR_T;`
69			`signal set_reg_lock0 : std_logic;`
70			`signal lock_reg_addr0 : REGISTER_ADDR_T;`
71			`signal set_reg_lock1 : std_logic;`
72			`signal lock_reg_addr1 : REGISTER_ADDR_T;`
73	7	cwalter	`signal stall_out : std_logic;`
74
75	71	jlechner	`constant TB_COND_TEST_VALUE : COND_T := COND_UNCONDITIONAL;`
76	13	cwalter
77			`constant TB_R1_TEST_VALUE : REGISTER_T := x"0001";`
78			`constant TB_R2_TEST_VALUE : REGISTER_T := x"0002";`
79			`constant TB_R3_TEST_VALUE : REGISTER_T := x"0003";`
80
81	10	cwalter	`constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";`
82			`constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";`
83	13	cwalter
84	10	cwalter	`constant TB_CLOCK : time := 20 ns;`
85	7	cwalter	`begin`
86
87			`-- instantiate the Unit Under Test (UUT)`
88			`uut : id_stage port map(`
89			`clk => clk,`
90			`reset => reset,`
91			`if_id_register => if_id_register,`
92			`id_ex_register => id_ex_register,`
93			`rx_addr => rx_addr,`
94			`ry_addr => ry_addr,`
95			`rz_addr => rz_addr,`
96			`rx => rx,`
97			`ry => ry,`
98			`rz => rz,`
99			`sr => sr,`
100			`lock_register => lock_register,`
101	17	cwalter	`set_reg_lock0 => set_reg_lock0,`
102			`lock_reg_addr0 => lock_reg_addr0,`
103			`set_reg_lock1 => set_reg_lock1,`
104			`lock_reg_addr1 => lock_reg_addr1,`
105	7	cwalter	`stall_in => stall_in,`
106			`stall_out => stall_out,`
107			`clear_in => clear_in`
108			`);`
109
110			`cg : process`
111			`begin`
112			`clk <= '0';`
113	10	cwalter	`wait for TB_CLOCK/2;`
114	7	cwalter	`clk <= '1';`
115	10	cwalter	`wait for TB_CLOCK/2;`
116	7	cwalter	`end process;`
117
118	13	cwalter	`regfile : process(rx_addr, ry_addr, rz_addr)`
119			`begin`
120			`case rx_addr is`
121			`when x"1" => rx <= TB_R1_TEST_VALUE;`
122			`when x"2" => rx <= TB_R2_TEST_VALUE;`
123			`when x"3" => rx <= TB_R3_TEST_VALUE;`
124			`when others => rz <= (others => 'X');`
125			`end case;`
126
127			`case ry_addr is`
128			`when x"1" => ry <= TB_R1_TEST_VALUE;`
129			`when x"2" => ry <= TB_R2_TEST_VALUE;`
130			`when x"3" => ry <= TB_R3_TEST_VALUE;`
131			`when others => rz <= (others => 'X');`
132			`end case;`
133
134			`case rz_addr is`
135			`when x"1" => rz <= TB_R1_TEST_VALUE;`
136			`when x"2" => rz <= TB_R2_TEST_VALUE;`
137			`when x"3" => rz <= TB_R3_TEST_VALUE;`
138			`when others => rz <= (others => 'X');`
139			`end case;`
140
141			`sr <= TB_SR_TEST_VALUE;`
142
143			`end process;`
144
145	7	cwalter	`tb : process`
146			`begin`
147			`reset <= '0';`
148			`wait for 100 ns;`
149			`reset <= '1';`
150
151	10	cwalter	`-- test case: basic functionallity`
152			`if_id_register.pc <= TB_PC_TEST_VALUE;`
153			`wait for TB_CLOCK;`
154	13	cwalter
155	10	cwalter	`-- test case: OPCODE_LD_IMM`
156	13	cwalter	`if_id_register.ir <= "100"& "0" & x"1" & x"55";`
157	10	cwalter	`wait for TB_CLOCK;`
158			`assert id_ex_register.opcode = OPCODE_LD_IMM;`
159			`assert id_ex_register.immediate = x"0055";`
160			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
161	13	cwalter	`assert rx_addr = x"1";`
162			`assert id_ex_register.rX_addr = x"1";`
163			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
164	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
165
166	10	cwalter	`-- test case: OPCODE_LD_IMM_HB`
167	13	cwalter	`if_id_register.ir <= "100"& "1" & x"1" & x"55";`
168	10	cwalter	`wait for TB_CLOCK;`
169			`assert id_ex_register.opcode = OPCODE_LD_IMM_HB;`
170			`assert id_ex_register.immediate = x"5500";`
171			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
172	13	cwalter	`assert rx_addr = x"1";`
173			`assert id_ex_register.rX_addr = x"1";`
174			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
175	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
176	13	cwalter
177			`-- test case: OPCODE_LD_IMM_HB`
178			`if_id_register.ir <= "100"& "1" & x"1" & x"55";`
179			`wait for TB_CLOCK;`
180			`assert id_ex_register.opcode = OPCODE_LD_IMM_HB;`
181			`assert id_ex_register.immediate = x"5500";`
182			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
183			`assert rx_addr = x"1";`
184			`assert id_ex_register.rX_addr = x"1";`
185			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
186	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
187	13	cwalter
188			`-- test case: OPCODE_LD_DISP`
189			`if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";`
190			`wait for TB_CLOCK;`
191			`assert id_ex_register.opcode = OPCODE_LD_DISP;`
192			`assert id_ex_register.rX_addr = x"1";`
193			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
194			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
195			`assert id_ex_register.rZ = TB_R3_TEST_VALUE;`
196			`assert id_ex_register.cond = TB_COND_TEST_VALUE;`
197			`assert rx_addr = x"1";`
198			`assert ry_addr = x"2";`
199			`assert rz_addr = x"3";`
200	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
201	13	cwalter
202			`-- test case: OPCODE_LD_DISP_MS`
203			`if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";`
204			`wait for TB_CLOCK;`
205			`assert id_ex_register.opcode = OPCODE_LD_DISP_MS;`
206			`assert id_ex_register.rX_addr = x"1";`
207			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
208			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
209			`assert id_ex_register.rZ = TB_R3_TEST_VALUE;`
210			`assert id_ex_register.cond = TB_COND_TEST_VALUE;`
211			`assert rx_addr = x"1";`
212			`assert ry_addr = x"2";`
213			`assert rz_addr = x"3";`
214	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
215	13	cwalter
216			`-- test case: OPCODE_LD_REG`
217			`if_id_register.ir <= "00001" & "001" & x"2" & x"1";`
218			`wait for TB_CLOCK;`
219			`assert id_ex_register.opcode = OPCODE_LD_REG;`
220			`assert id_ex_register.rX_addr = x"2";`
221			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
222			`assert id_ex_register.rY = TB_R1_TEST_VALUE;`
223			`assert id_ex_register.cond = COND_NOT_ZERO;`
224			`assert rx_addr = x"2";`
225			`assert ry_addr = x"1";`
226	17	cwalter	`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
227
228			`-- test case: OPCODE_LD_REG WITH STALL`
229			`lock_register(1) <= '1';`
230			`if_id_register.ir <= "00001" & "001" & x"2" & x"1";`
231			`wait for TB_CLOCK;`
232			`assert id_ex_register.opcode = OPCODE_LD_REG;`
233			`assert id_ex_register.rX_addr = x"2";`
234			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
235			`assert id_ex_register.rY = TB_R1_TEST_VALUE;`
236			`assert id_ex_register.cond = COND_NOT_ZERO;`
237			`assert rx_addr = x"2";`
238			`assert ry_addr = x"1";`
239			`assert stall_out = '1';`
240			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
241			`lock_register(1) <= '0';`
242
243			`-- test case: OPCODE_ST_DISP`
244			`if_id_register.ir <= "111" & "100" & "11" & x"1" & x"2";`
245			`wait for TB_CLOCK;`
246			`assert id_ex_register.opcode = OPCODE_ST_DISP;`
247			`assert id_ex_register.rX_addr = x"1";`
248			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
249			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
250			`assert id_ex_register.rZ = TB_R3_TEST_VALUE;`
251			`assert id_ex_register.cond = COND_NEGATIVE;`
252			`assert rx_addr = x"1";`
253			`assert ry_addr = x"2";`
254			`assert rz_addr = x"3";`
255
256			`-- test case: OPCODE_ADD`
257			`if_id_register.ir <= "00010" & "000" & x"3" & x"2";`
258			`wait for TB_CLOCK;`
259			`assert id_ex_register.opcode = OPCODE_ADD;`
260			`assert id_ex_register.rX_addr = x"3";`
261			`assert id_ex_register.rX = TB_R3_TEST_VALUE;`
262			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
263			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
264			`assert rx_addr = x"3";`
265			`assert ry_addr = x"2";`
266			`assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );`
267
268			`-- test case: OPCODE_ADD_IMM`
269			`if_id_register.ir <= "00011" & "010" & x"2" & x"5";`
270			`wait for TB_CLOCK;`
271			`assert id_ex_register.opcode = OPCODE_ADD_IMM;`
272			`assert id_ex_register.rX_addr = x"2";`
273			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
274			`assert id_ex_register.immediate = x"0005";`
275			`assert id_ex_register.cond = COND_ZERO;`
276			`assert rx_addr = x"2";`
277			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
278
279			`-- test case: OPCODE_SUB`
280			`if_id_register.ir <= "00100" & "011" & x"1" & x"2";`
281			`wait for TB_CLOCK;`
282			`assert id_ex_register.opcode = OPCODE_SUB;`
283			`assert id_ex_register.rX_addr = x"1";`
284			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
285			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
286			`assert id_ex_register.cond = COND_CARRY;`
287			`assert rx_addr = x"1";`
288			`assert ry_addr = x"2";`
289			`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
290
291			`-- test case: OPCODE_SUB_IMM`
292			`if_id_register.ir <= "00101" & "100" & x"1" & x"A";`
293			`wait for TB_CLOCK;`
294			`assert id_ex_register.opcode = OPCODE_SUB_IMM;`
295			`assert id_ex_register.rX_addr = x"1";`
296			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
297			`assert id_ex_register.immediate = x"000A";`
298			`assert id_ex_register.cond = COND_NEGATIVE;`
299			`assert rx_addr = x"1";`
300			`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
301
302			`-- test case: OPCODE_NEG`
303			`if_id_register.ir <= "00110" & "101" & x"2" & x"2";`
304			`wait for TB_CLOCK;`
305			`assert id_ex_register.opcode = OPCODE_NEG;`
306			`assert id_ex_register.rX_addr = x"2";`
307			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
308			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
309			`assert id_ex_register.cond = COND_OVERFLOW;`
310			`assert rx_addr = x"2";`
311			`assert ry_addr = x"2";`
312			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
313
314			`-- test case: OPCODE_ARS`
315			`if_id_register.ir <= "00111" & "110" & x"3" & x"2";`
316			`wait for TB_CLOCK;`
317			`assert id_ex_register.opcode = OPCODE_ARS;`
318			`assert id_ex_register.rX_addr = x"3";`
319			`assert id_ex_register.rX = TB_R3_TEST_VALUE;`
320			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
321			`assert id_ex_register.cond = COND_ZERO_NEGATIVE;`
322			`assert rx_addr = x"3";`
323			`assert ry_addr = x"2";`
324			`assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );`
325
326			`-- test case: OPCODE_ALS`
327			`if_id_register.ir <= "01000" & "000" & x"2" & x"1";`
328			`wait for TB_CLOCK;`
329			`assert id_ex_register.opcode = OPCODE_ALS;`
330			`assert id_ex_register.rX_addr = x"2";`
331			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
332			`assert id_ex_register.rY = TB_R1_TEST_VALUE;`
333			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
334			`assert rx_addr = x"2";`
335			`assert ry_addr = x"1";`
336			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
337
338
339			`wait;`
340	7	cwalter	`end process;`
341
342			`end;`

Browse

Tools

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [tb_id_stage_unit.vhd] - Blame information for rev 148