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-- File: ex_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Execute stage
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.rise_pack.all;
 
entity tb_id_stage_unit_vhd is
end tb_id_stage_unit_vhd;
 
architecture behavior of tb_id_stage_unit_vhd is
 
  -- component Declaration for the Unit Under Test (UUT)
  component id_stage
    port(
      clk   : in std_logic;
      reset : in std_logic;
 
      if_id_register : in  IF_ID_REGISTER_T;
      id_ex_register : out ID_EX_REGISTER_T;
 
      rx_addr : out REGISTER_ADDR_T;
      ry_addr : out REGISTER_ADDR_T;
      rz_addr : out REGISTER_ADDR_T;
 
      rx : in REGISTER_T;
      ry : in REGISTER_T;
      rz : in REGISTER_T;
      sr : in SR_REGISTER_T;
 
      lock_register  : in  LOCK_REGISTER_T;
      set_reg_lock0  : out std_logic;
      lock_reg_addr0 : out REGISTER_ADDR_T;
      set_reg_lock1  : out std_logic;
      lock_reg_addr1 : out REGISTER_ADDR_T;
 
      stall_in  : in  std_logic;
      stall_out : out std_logic;
      clear_in  : in  std_logic
      );
  end component;
 
  --inputs
  signal clk            : std_logic := '0';
  signal reset          : std_logic := '0';
  signal if_id_register : IF_ID_REGISTER_T;
 
  signal stall_in       : std_logic := '0';
  signal clear_in       : std_logic := '0';
  signal rx             : REGISTER_T;
  signal ry             : REGISTER_T;
  signal rz             : REGISTER_T;
  signal sr             : SR_REGISTER_T;
  signal lock_register  : LOCK_REGISTER_T := ( others => '0' );
  --Outputs
  signal id_ex_register : ID_EX_REGISTER_T;
  signal rx_addr        : REGISTER_ADDR_T;
  signal ry_addr        : REGISTER_ADDR_T;
  signal rz_addr        : REGISTER_ADDR_T;
  signal set_reg_lock0  : std_logic;
  signal lock_reg_addr0 : REGISTER_ADDR_T;
  signal set_reg_lock1  : std_logic;
  signal lock_reg_addr1 : REGISTER_ADDR_T;
  signal stall_out      : std_logic;
 
  constant TB_COND_TEST_VALUE : COND_T := COND_NONE;
 
  constant TB_R1_TEST_VALUE : REGISTER_T := x"0001";
  constant TB_R2_TEST_VALUE : REGISTER_T := x"0002";
  constant TB_R3_TEST_VALUE : REGISTER_T := x"0003";
 
  constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
  constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
 
  constant TB_CLOCK : time := 20 ns;
begin
 
  -- instantiate the Unit Under Test (UUT)
  uut : id_stage port map(
    clk            => clk,
    reset          => reset,
    if_id_register => if_id_register,
    id_ex_register => id_ex_register,
    rx_addr        => rx_addr,
    ry_addr        => ry_addr,
    rz_addr        => rz_addr,
    rx             => rx,
    ry             => ry,
    rz             => rz,
    sr             => sr,
    lock_register  => lock_register,
    set_reg_lock0  => set_reg_lock0,
    lock_reg_addr0 => lock_reg_addr0,
    set_reg_lock1  => set_reg_lock1,
    lock_reg_addr1 => lock_reg_addr1,
    stall_in       => stall_in,
    stall_out      => stall_out,
    clear_in       => clear_in
    );
 
  cg : process
  begin
    clk <= '0';
    wait for TB_CLOCK/2;
    clk <= '1';
    wait for TB_CLOCK/2;
  end process;
 
  regfile : process(rx_addr, ry_addr, rz_addr)
  begin
    case rx_addr is
      when x"1"   => rx <= TB_R1_TEST_VALUE;
      when x"2"   => rx <= TB_R2_TEST_VALUE;
      when x"3"   => rx <= TB_R3_TEST_VALUE;
      when others => rz <= (others => 'X');
    end case;
 
    case ry_addr is
      when x"1"   => ry <= TB_R1_TEST_VALUE;
      when x"2"   => ry <= TB_R2_TEST_VALUE;
      when x"3"   => ry <= TB_R3_TEST_VALUE;
      when others => rz <= (others => 'X');
    end case;
 
    case rz_addr is
      when x"1"   => rz <= TB_R1_TEST_VALUE;
      when x"2"   => rz <= TB_R2_TEST_VALUE;
      when x"3"   => rz <= TB_R3_TEST_VALUE;
      when others => rz <= (others => 'X');
    end case;
 
    sr <= TB_SR_TEST_VALUE;
 
  end process;
 
  tb : process
  begin
    reset <= '0';
    wait for 100 ns;
    reset <= '1';
 
    -- test case: basic functionallity
    if_id_register.pc <= TB_PC_TEST_VALUE;
    wait for TB_CLOCK;
 
    -- test case: OPCODE_LD_IMM 
    if_id_register.ir <= "100"& "0" & x"1" & x"55";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_IMM;
    assert id_ex_register.immediate = x"0055";
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"1";
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_IMM_HB
    if_id_register.ir <= "100"& "1" & x"1" & x"55";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
    assert id_ex_register.immediate = x"5500";
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"1";
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_IMM_HB
    if_id_register.ir <= "100"& "1" & x"1" & x"55";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
    assert id_ex_register.immediate = x"5500";
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"1";
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_DISP
    if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_DISP;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
    assert id_ex_register.cond = TB_COND_TEST_VALUE;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert rz_addr = x"3";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_DISP_MS
    if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_DISP_MS;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
    assert id_ex_register.cond = TB_COND_TEST_VALUE;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert rz_addr = x"3";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_REG
    if_id_register.ir <= "00001" & "001" & x"2" & x"1";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_REG;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
    assert id_ex_register.cond = COND_NOT_ZERO;
    assert rx_addr = x"2";
    assert ry_addr = x"1";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_LD_REG WITH STALL
    lock_register(1) <= '1';
    if_id_register.ir <= "00001" & "001" & x"2" & x"1";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_LD_REG;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
    assert id_ex_register.cond = COND_NOT_ZERO;
    assert rx_addr = x"2";
    assert ry_addr = x"1";
    assert stall_out = '1';
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
    lock_register(1) <= '0';
 
    -- test case: OPCODE_ST_DISP
    if_id_register.ir <= "111" & "100" & "11" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ST_DISP;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.rZ = TB_R3_TEST_VALUE;
    assert id_ex_register.cond = COND_NEGATIVE;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert rz_addr = x"3";
 
    -- test case: OPCODE_ADD
    if_id_register.ir <= "00010" & "000" & x"3" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ADD;
    assert id_ex_register.rX_addr = x"3";
    assert id_ex_register.rX = TB_R3_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"3";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_ADD_IMM
    if_id_register.ir <= "00011" & "010" & x"2" & x"5";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ADD_IMM;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.immediate = x"0005";
    assert id_ex_register.cond = COND_ZERO;
    assert rx_addr = x"2";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_SUB
    if_id_register.ir <= "00100" & "011" & x"1" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_SUB;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_CARRY;
    assert rx_addr = x"1";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_SUB_IMM
    if_id_register.ir <= "00101" & "100" & x"1" & x"A";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_SUB_IMM;
    assert id_ex_register.rX_addr = x"1";
    assert id_ex_register.rX = TB_R1_TEST_VALUE;
    assert id_ex_register.immediate = x"000A";
    assert id_ex_register.cond = COND_NEGATIVE;
    assert rx_addr = x"1";
    assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_NEG
    if_id_register.ir <= "00110" & "101" & x"2" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_NEG;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_OVERFLOW;
    assert rx_addr = x"2";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_ARS
    if_id_register.ir <= "00111" & "110" & x"3" & x"2";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ARS;
    assert id_ex_register.rX_addr = x"3";
    assert id_ex_register.rX = TB_R3_TEST_VALUE;
    assert id_ex_register.rY = TB_R2_TEST_VALUE;
    assert id_ex_register.cond = COND_ZERO_NEGATIVE;
    assert rx_addr = x"3";
    assert ry_addr = x"2";
    assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );
 
    -- test case: OPCODE_ALS
    if_id_register.ir <= "01000" & "000" & x"2" & x"1";
    wait for TB_CLOCK;
    assert id_ex_register.opcode = OPCODE_ALS;
    assert id_ex_register.rX_addr = x"2";
    assert id_ex_register.rX = TB_R2_TEST_VALUE;
    assert id_ex_register.rY = TB_R1_TEST_VALUE;
    assert id_ex_register.cond = COND_UNCONDITIONAL;
    assert rx_addr = x"2";
    assert ry_addr = x"1";
    assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
 
 
    wait;
  end process;
 
end;

Line No.	Rev	Author	Line
1	7	cwalter	`-- File: ex_stage.vhd`
2			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
3			`-- Created: 2006-11-29`
4			`-- Last updated: 2006-11-29`
5
6			`-- Description:`
7			`-- Execute stage`
8			`-------------------------------------------------------------------------------`
9
10			`library ieee;`
11			`use ieee.std_logic_1164.all;`
12			`use ieee.std_logic_unsigned.all;`
13			`use ieee.numeric_std.all;`
14			`use work.rise_pack.all;`
15
16			`entity tb_id_stage_unit_vhd is`
17			`end tb_id_stage_unit_vhd;`
18
19			`architecture behavior of tb_id_stage_unit_vhd is`
20
21			`-- component Declaration for the Unit Under Test (UUT)`
22			`component id_stage`
23			`port(`
24			`clk : in std_logic;`
25			`reset : in std_logic;`
26
27			`if_id_register : in IF_ID_REGISTER_T;`
28			`id_ex_register : out ID_EX_REGISTER_T;`
29
30			`rx_addr : out REGISTER_ADDR_T;`
31			`ry_addr : out REGISTER_ADDR_T;`
32			`rz_addr : out REGISTER_ADDR_T;`
33
34			`rx : in REGISTER_T;`
35			`ry : in REGISTER_T;`
36			`rz : in REGISTER_T;`
37			`sr : in SR_REGISTER_T;`
38
39	17	cwalter	`lock_register : in LOCK_REGISTER_T;`
40			`set_reg_lock0 : out std_logic;`
41			`lock_reg_addr0 : out REGISTER_ADDR_T;`
42			`set_reg_lock1 : out std_logic;`
43			`lock_reg_addr1 : out REGISTER_ADDR_T;`
44
45	7	cwalter	`stall_in : in std_logic;`
46			`stall_out : out std_logic;`
47			`clear_in : in std_logic`
48			`);`
49			`end component;`
50
51			`--inputs`
52			`signal clk : std_logic := '0';`
53			`signal reset : std_logic := '0';`
54			`signal if_id_register : IF_ID_REGISTER_T;`
55
56	13	cwalter	`signal stall_in : std_logic := '0';`
57			`signal clear_in : std_logic := '0';`
58	10	cwalter	`signal rx : REGISTER_T;`
59			`signal ry : REGISTER_T;`
60			`signal rz : REGISTER_T;`
61			`signal sr : SR_REGISTER_T;`
62	17	cwalter	`signal lock_register : LOCK_REGISTER_T := ( others => '0' );`
63	7	cwalter	`--Outputs`
64			`signal id_ex_register : ID_EX_REGISTER_T;`
65	17	cwalter	`signal rx_addr : REGISTER_ADDR_T;`
66			`signal ry_addr : REGISTER_ADDR_T;`
67			`signal rz_addr : REGISTER_ADDR_T;`
68			`signal set_reg_lock0 : std_logic;`
69			`signal lock_reg_addr0 : REGISTER_ADDR_T;`
70			`signal set_reg_lock1 : std_logic;`
71			`signal lock_reg_addr1 : REGISTER_ADDR_T;`
72	7	cwalter	`signal stall_out : std_logic;`
73
74	13	cwalter	`constant TB_COND_TEST_VALUE : COND_T := COND_NONE;`
75
76			`constant TB_R1_TEST_VALUE : REGISTER_T := x"0001";`
77			`constant TB_R2_TEST_VALUE : REGISTER_T := x"0002";`
78			`constant TB_R3_TEST_VALUE : REGISTER_T := x"0003";`
79
80	10	cwalter	`constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";`
81			`constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";`
82	13	cwalter
83	10	cwalter	`constant TB_CLOCK : time := 20 ns;`
84	7	cwalter	`begin`
85
86			`-- instantiate the Unit Under Test (UUT)`
87			`uut : id_stage port map(`
88			`clk => clk,`
89			`reset => reset,`
90			`if_id_register => if_id_register,`
91			`id_ex_register => id_ex_register,`
92			`rx_addr => rx_addr,`
93			`ry_addr => ry_addr,`
94			`rz_addr => rz_addr,`
95			`rx => rx,`
96			`ry => ry,`
97			`rz => rz,`
98			`sr => sr,`
99			`lock_register => lock_register,`
100	17	cwalter	`set_reg_lock0 => set_reg_lock0,`
101			`lock_reg_addr0 => lock_reg_addr0,`
102			`set_reg_lock1 => set_reg_lock1,`
103			`lock_reg_addr1 => lock_reg_addr1,`
104	7	cwalter	`stall_in => stall_in,`
105			`stall_out => stall_out,`
106			`clear_in => clear_in`
107			`);`
108
109			`cg : process`
110			`begin`
111			`clk <= '0';`
112	10	cwalter	`wait for TB_CLOCK/2;`
113	7	cwalter	`clk <= '1';`
114	10	cwalter	`wait for TB_CLOCK/2;`
115	7	cwalter	`end process;`
116
117	13	cwalter	`regfile : process(rx_addr, ry_addr, rz_addr)`
118			`begin`
119			`case rx_addr is`
120			`when x"1" => rx <= TB_R1_TEST_VALUE;`
121			`when x"2" => rx <= TB_R2_TEST_VALUE;`
122			`when x"3" => rx <= TB_R3_TEST_VALUE;`
123			`when others => rz <= (others => 'X');`
124			`end case;`
125
126			`case ry_addr is`
127			`when x"1" => ry <= TB_R1_TEST_VALUE;`
128			`when x"2" => ry <= TB_R2_TEST_VALUE;`
129			`when x"3" => ry <= TB_R3_TEST_VALUE;`
130			`when others => rz <= (others => 'X');`
131			`end case;`
132
133			`case rz_addr is`
134			`when x"1" => rz <= TB_R1_TEST_VALUE;`
135			`when x"2" => rz <= TB_R2_TEST_VALUE;`
136			`when x"3" => rz <= TB_R3_TEST_VALUE;`
137			`when others => rz <= (others => 'X');`
138			`end case;`
139
140			`sr <= TB_SR_TEST_VALUE;`
141
142			`end process;`
143
144	7	cwalter	`tb : process`
145			`begin`
146			`reset <= '0';`
147			`wait for 100 ns;`
148			`reset <= '1';`
149
150	10	cwalter	`-- test case: basic functionallity`
151			`if_id_register.pc <= TB_PC_TEST_VALUE;`
152			`wait for TB_CLOCK;`
153	13	cwalter
154	10	cwalter	`-- test case: OPCODE_LD_IMM`
155	13	cwalter	`if_id_register.ir <= "100"& "0" & x"1" & x"55";`
156	10	cwalter	`wait for TB_CLOCK;`
157			`assert id_ex_register.opcode = OPCODE_LD_IMM;`
158			`assert id_ex_register.immediate = x"0055";`
159			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
160	13	cwalter	`assert rx_addr = x"1";`
161			`assert id_ex_register.rX_addr = x"1";`
162			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
163	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
164
165	10	cwalter	`-- test case: OPCODE_LD_IMM_HB`
166	13	cwalter	`if_id_register.ir <= "100"& "1" & x"1" & x"55";`
167	10	cwalter	`wait for TB_CLOCK;`
168			`assert id_ex_register.opcode = OPCODE_LD_IMM_HB;`
169			`assert id_ex_register.immediate = x"5500";`
170			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
171	13	cwalter	`assert rx_addr = x"1";`
172			`assert id_ex_register.rX_addr = x"1";`
173			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
174	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
175	13	cwalter
176			`-- test case: OPCODE_LD_IMM_HB`
177			`if_id_register.ir <= "100"& "1" & x"1" & x"55";`
178			`wait for TB_CLOCK;`
179			`assert id_ex_register.opcode = OPCODE_LD_IMM_HB;`
180			`assert id_ex_register.immediate = x"5500";`
181			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
182			`assert rx_addr = x"1";`
183			`assert id_ex_register.rX_addr = x"1";`
184			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
185	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
186	13	cwalter
187			`-- test case: OPCODE_LD_DISP`
188			`if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";`
189			`wait for TB_CLOCK;`
190			`assert id_ex_register.opcode = OPCODE_LD_DISP;`
191			`assert id_ex_register.rX_addr = x"1";`
192			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
193			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
194			`assert id_ex_register.rZ = TB_R3_TEST_VALUE;`
195			`assert id_ex_register.cond = TB_COND_TEST_VALUE;`
196			`assert rx_addr = x"1";`
197			`assert ry_addr = x"2";`
198			`assert rz_addr = x"3";`
199	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
200	13	cwalter
201			`-- test case: OPCODE_LD_DISP_MS`
202			`if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";`
203			`wait for TB_CLOCK;`
204			`assert id_ex_register.opcode = OPCODE_LD_DISP_MS;`
205			`assert id_ex_register.rX_addr = x"1";`
206			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
207			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
208			`assert id_ex_register.rZ = TB_R3_TEST_VALUE;`
209			`assert id_ex_register.cond = TB_COND_TEST_VALUE;`
210			`assert rx_addr = x"1";`
211			`assert ry_addr = x"2";`
212			`assert rz_addr = x"3";`
213	17	cwalter	`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
214	13	cwalter
215			`-- test case: OPCODE_LD_REG`
216			`if_id_register.ir <= "00001" & "001" & x"2" & x"1";`
217			`wait for TB_CLOCK;`
218			`assert id_ex_register.opcode = OPCODE_LD_REG;`
219			`assert id_ex_register.rX_addr = x"2";`
220			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
221			`assert id_ex_register.rY = TB_R1_TEST_VALUE;`
222			`assert id_ex_register.cond = COND_NOT_ZERO;`
223			`assert rx_addr = x"2";`
224			`assert ry_addr = x"1";`
225	17	cwalter	`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
226
227			`-- test case: OPCODE_LD_REG WITH STALL`
228			`lock_register(1) <= '1';`
229			`if_id_register.ir <= "00001" & "001" & x"2" & x"1";`
230			`wait for TB_CLOCK;`
231			`assert id_ex_register.opcode = OPCODE_LD_REG;`
232			`assert id_ex_register.rX_addr = x"2";`
233			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
234			`assert id_ex_register.rY = TB_R1_TEST_VALUE;`
235			`assert id_ex_register.cond = COND_NOT_ZERO;`
236			`assert rx_addr = x"2";`
237			`assert ry_addr = x"1";`
238			`assert stall_out = '1';`
239			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
240			`lock_register(1) <= '0';`
241
242			`-- test case: OPCODE_ST_DISP`
243			`if_id_register.ir <= "111" & "100" & "11" & x"1" & x"2";`
244			`wait for TB_CLOCK;`
245			`assert id_ex_register.opcode = OPCODE_ST_DISP;`
246			`assert id_ex_register.rX_addr = x"1";`
247			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
248			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
249			`assert id_ex_register.rZ = TB_R3_TEST_VALUE;`
250			`assert id_ex_register.cond = COND_NEGATIVE;`
251			`assert rx_addr = x"1";`
252			`assert ry_addr = x"2";`
253			`assert rz_addr = x"3";`
254
255			`-- test case: OPCODE_ADD`
256			`if_id_register.ir <= "00010" & "000" & x"3" & x"2";`
257			`wait for TB_CLOCK;`
258			`assert id_ex_register.opcode = OPCODE_ADD;`
259			`assert id_ex_register.rX_addr = x"3";`
260			`assert id_ex_register.rX = TB_R3_TEST_VALUE;`
261			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
262			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
263			`assert rx_addr = x"3";`
264			`assert ry_addr = x"2";`
265			`assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );`
266
267			`-- test case: OPCODE_ADD_IMM`
268			`if_id_register.ir <= "00011" & "010" & x"2" & x"5";`
269			`wait for TB_CLOCK;`
270			`assert id_ex_register.opcode = OPCODE_ADD_IMM;`
271			`assert id_ex_register.rX_addr = x"2";`
272			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
273			`assert id_ex_register.immediate = x"0005";`
274			`assert id_ex_register.cond = COND_ZERO;`
275			`assert rx_addr = x"2";`
276			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
277
278			`-- test case: OPCODE_SUB`
279			`if_id_register.ir <= "00100" & "011" & x"1" & x"2";`
280			`wait for TB_CLOCK;`
281			`assert id_ex_register.opcode = OPCODE_SUB;`
282			`assert id_ex_register.rX_addr = x"1";`
283			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
284			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
285			`assert id_ex_register.cond = COND_CARRY;`
286			`assert rx_addr = x"1";`
287			`assert ry_addr = x"2";`
288			`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
289
290			`-- test case: OPCODE_SUB_IMM`
291			`if_id_register.ir <= "00101" & "100" & x"1" & x"A";`
292			`wait for TB_CLOCK;`
293			`assert id_ex_register.opcode = OPCODE_SUB_IMM;`
294			`assert id_ex_register.rX_addr = x"1";`
295			`assert id_ex_register.rX = TB_R1_TEST_VALUE;`
296			`assert id_ex_register.immediate = x"000A";`
297			`assert id_ex_register.cond = COND_NEGATIVE;`
298			`assert rx_addr = x"1";`
299			`assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );`
300
301			`-- test case: OPCODE_NEG`
302			`if_id_register.ir <= "00110" & "101" & x"2" & x"2";`
303			`wait for TB_CLOCK;`
304			`assert id_ex_register.opcode = OPCODE_NEG;`
305			`assert id_ex_register.rX_addr = x"2";`
306			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
307			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
308			`assert id_ex_register.cond = COND_OVERFLOW;`
309			`assert rx_addr = x"2";`
310			`assert ry_addr = x"2";`
311			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
312
313			`-- test case: OPCODE_ARS`
314			`if_id_register.ir <= "00111" & "110" & x"3" & x"2";`
315			`wait for TB_CLOCK;`
316			`assert id_ex_register.opcode = OPCODE_ARS;`
317			`assert id_ex_register.rX_addr = x"3";`
318			`assert id_ex_register.rX = TB_R3_TEST_VALUE;`
319			`assert id_ex_register.rY = TB_R2_TEST_VALUE;`
320			`assert id_ex_register.cond = COND_ZERO_NEGATIVE;`
321			`assert rx_addr = x"3";`
322			`assert ry_addr = x"2";`
323			`assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );`
324
325			`-- test case: OPCODE_ALS`
326			`if_id_register.ir <= "01000" & "000" & x"2" & x"1";`
327			`wait for TB_CLOCK;`
328			`assert id_ex_register.opcode = OPCODE_ALS;`
329			`assert id_ex_register.rX_addr = x"2";`
330			`assert id_ex_register.rX = TB_R2_TEST_VALUE;`
331			`assert id_ex_register.rY = TB_R1_TEST_VALUE;`
332			`assert id_ex_register.cond = COND_UNCONDITIONAL;`
333			`assert rx_addr = x"2";`
334			`assert ry_addr = x"1";`
335			`assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );`
336
337
338			`wait;`
339	7	cwalter	`end process;`
340
341			`end;`

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