URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [tb_rise_uart.vhd] - Blame information for rev 151

Go to most recent revision | Details | Compare with Previous | View Log


-- File: ex_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Execute stage
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.rise_pack.all;
use work.RISE_PACK_SPECIFIC.all;
 
entity tb_rise_vhd is
end tb_rise_vhd;
 
architecture behavior of tb_rise_vhd is
 
  component rise
    port(
      clk   : in  std_logic;
      reset : in  std_logic;
      rx    : in  std_logic;
      tx    : out std_logic
      );
  end component;
 
  --Inputs
  signal clk   : std_logic := '0';
  signal reset : std_logic := '0';
  signal rx    : std_logic := '1';
 
  --Outputs
  signal tx : std_logic;
 
begin
 
  -- Instantiate the Unit Under Test (UUT)
  uut : rise port map(
    clk   => clk,
    reset => reset,
    rx    => rx,
    tx    => tx
    );
 
  clk_gen : process
  begin
    clk <= '1';
    wait for 10 ns;
    clk <= '0';
    wait for 10 ns;
  end process;
 
  tb : process
  begin
 
    wait for 5 ns;
 
    -- Place stimulus here
    reset <= '1';
 
    -- Let the simulation run for 200 ns;
    wait for 200 ns;
 
    rx <= '0';                          --startbit
    wait for 8600 ns;                   -- zellenzeit 8,6 us
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 stopbit
    wait for 8600ns;
 
    wait for 20us;
 
    -- send a 'CR' = 0x0A
    rx <= '0';                          -- 8 startbit
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '0';                          -- 8 datenbits
    wait for 8600ns;
    rx <= '1';                          -- 8 stopbit
    wait for 8600ns;
 
    wait;
  end process;
 
end;

Line No.	Rev	Author	Line
1	140	cwalter	`-- File: ex_stage.vhd`
2			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
3			`-- Created: 2006-11-29`
4			`-- Last updated: 2006-11-29`
5
6			`-- Description:`
7			`-- Execute stage`
8			`-------------------------------------------------------------------------------`
9
10			`library ieee;`
11			`use ieee.std_logic_1164.all;`
12			`use ieee.std_logic_unsigned.all;`
13			`use ieee.numeric_std.all;`
14			`use work.rise_pack.all;`
15			`use work.RISE_PACK_SPECIFIC.all;`
16
17			`entity tb_rise_vhd is`
18			`end tb_rise_vhd;`
19
20			`architecture behavior of tb_rise_vhd is`
21
22			`component rise`
23			`port(`
24			`clk : in std_logic;`
25			`reset : in std_logic;`
26			`rx : in std_logic;`
27			`tx : out std_logic`
28			`);`
29			`end component;`
30
31			`--Inputs`
32			`signal clk : std_logic := '0';`
33			`signal reset : std_logic := '0';`
34			`signal rx : std_logic := '1';`
35
36			`--Outputs`
37			`signal tx : std_logic;`
38
39			`begin`
40
41			`-- Instantiate the Unit Under Test (UUT)`
42			`uut : rise port map(`
43			`clk => clk,`
44			`reset => reset,`
45			`rx => rx,`
46			`tx => tx`
47			`);`
48
49			`clk_gen : process`
50			`begin`
51			`clk <= '1';`
52			`wait for 10 ns;`
53			`clk <= '0';`
54			`wait for 10 ns;`
55			`end process;`
56
57			`tb : process`
58			`begin`
59
60			`wait for 5 ns;`
61
62			`-- Place stimulus here`
63			`reset <= '1';`
64
65			`-- Let the simulation run for 200 ns;`
66			`wait for 200 ns;`
67
68			`rx <= '0'; --startbit`
69			`wait for 8600 ns; -- zellenzeit 8,6 us`
70			`rx <= '0'; -- 8 datenbits`
71			`wait for 8600ns;`
72			`rx <= '1'; -- 8 datenbits`
73			`wait for 8600ns;`
74			`rx <= '0'; -- 8 datenbits`
75			`wait for 8600ns;`
76			`rx <= '0'; -- 8 datenbits`
77			`wait for 8600ns;`
78			`rx <= '0'; -- 8 datenbits`
79			`wait for 8600ns;`
80			`rx <= '1'; -- 8 datenbits`
81			`wait for 8600ns;`
82			`rx <= '1'; -- 8 datenbits`
83			`wait for 8600ns;`
84			`rx <= '0'; -- 8 datenbits`
85			`wait for 8600ns;`
86			`rx <= '1'; -- 8 stopbit`
87			`wait for 8600ns;`
88
89	141	cwalter	`wait for 20us;`
90
91	142	cwalter	`-- send a 'CR' = 0x0A`
92	140	cwalter	`rx <= '0'; -- 8 startbit`
93			`wait for 8600ns;`
94	142	cwalter	`rx <= '0'; -- 8 datenbits`
95			`wait for 8600ns;`
96	140	cwalter	`rx <= '1'; -- 8 datenbits`
97			`wait for 8600ns;`
98			`rx <= '0'; -- 8 datenbits`
99			`wait for 8600ns;`
100	142	cwalter	`rx <= '1'; -- 8 datenbits`
101			`wait for 8600ns;`
102	140	cwalter	`rx <= '0'; -- 8 datenbits`
103			`wait for 8600ns;`
104			`rx <= '0'; -- 8 datenbits`
105			`wait for 8600ns;`
106			`rx <= '0'; -- 8 datenbits`
107			`wait for 8600ns;`
108			`rx <= '0'; -- 8 datenbits`
109			`wait for 8600ns;`
110			`rx <= '1'; -- 8 stopbit`
111			`wait for 8600ns;`
112
113			`wait;`
114			`end process;`
115
116			`end;`

Browse

Tools

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] [tb_rise_uart.vhd] - Blame information for rev 151