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[/] [rise/] [trunk/] [vhdl/] [wb_stage.vhd] - Blame information for rev 151

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-- File: wb_stage.vhd
-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter
-- Created: 2006-11-29
-- Last updated: 2006-11-29
 
-- Description:
-- Instruction decode stage
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
 
use WORK.RISE_PACK.all;
use work.RISE_PACK_SPECIFIC.all;
 
entity wb_stage is
 
  port (
    clk   : in std_logic;
    reset : in std_logic;
 
    mem_wb_register : in MEM_WB_REGISTER_T;
 
    dreg_addr   : out REGISTER_ADDR_T;
    dreg        : out REGISTER_T;
    dreg_enable : out std_logic;
 
    lr        : out PC_REGISTER_T;
    lr_enable : out std_logic;
 
    sr        : out SR_REGISTER_T;
    sr_enable : out std_logic;
 
    clear_out : out std_logic;
 
    clear_reg_lock0 : out std_logic;
    lock_reg_addr0  : out REGISTER_ADDR_T;
    clear_reg_lock1 : out std_logic;
    lock_reg_addr1  : out REGISTER_ADDR_T);
 
 
end wb_stage;
 
architecture wb_stage_rtl of wb_stage is
 
begin  -- wb_stage_rtl
 
  clear_out <= '0';  -- clear_out output is unused at the moment.
 
  process (reset, mem_wb_register)
  begin
    if reset = '0' then
      clear_reg_lock0 <= '0';
      lock_reg_addr0  <= (others => 'X');
      clear_reg_lock1 <= '0';
      lock_reg_addr1  <= (others => 'X');
 
      dreg_enable <= '0';
      dreg_addr <= (others => 'X');
      dreg      <= (others => 'X');
      lr_enable   <= '0';
      lr        <= (others => 'X');
      sr_enable   <= '0';
      sr        <= (others => 'X');
    else
 
      -- write back of register value. --
      dreg_addr <= mem_wb_register.dreg_addr;
      if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then
        if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
          dreg <= mem_wb_register.mem_reg;
        else
          dreg <= mem_wb_register.reg;
        end if;
        dreg_enable     <= '1';
        clear_reg_lock0 <= '1';
        lock_reg_addr0  <= mem_wb_register.dreg_addr;
      else
        dreg_enable     <= '0';
        dreg            <= (others => 'X');
        clear_reg_lock0 <= '0';
        lock_reg_addr0  <= (others => 'X');
      end if;
 
      -- we have only one lock register.
      assert mem_wb_register.aluop2(ALUOP2_SR_BIT) = '0' or mem_wb_register.aluop2(ALUOP2_LR_BIT) = '0';
 
      clear_reg_lock1 <= '0';
      lock_reg_addr1  <= (others => 'X');
      -- write back of LR --
      if mem_wb_register.aluop2(ALUOP2_LR_BIT) = '1' then
        lr              <= mem_wb_register.lr;
        lr_enable       <= '1';
        clear_reg_lock1 <= '1';
        lock_reg_addr1  <= LR_REGISTER_ADDR;
      else
        lr              <= ( others => 'X' );
        lr_enable       <= '0';
      end if;
 
      -- write back of SR --
      if mem_wb_register.aluop2(ALUOP2_SR_BIT) = '1' then
        -- calculate SR value
        sr              <= mem_wb_register.sr;
        if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then
           if mem_wb_register.mem_reg = CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH) then
             sr( SR_REGISTER_ZERO ) <= '1';
           end if;
           if mem_wb_register.mem_reg( REGISTER_WIDTH - 1 ) = '1' then
             sr( SR_REGISTER_NEGATIVE ) <= '1';
           end if;
        end if;
        sr_enable       <= '1';
        clear_reg_lock1 <= '1';
        lock_reg_addr1  <= SR_REGISTER_ADDR;
      else
        sr              <= ( others => 'X' );
        sr_enable       <= '0';
      end if;
 
 
    end if;
  end process;
end wb_stage_rtl;

Line No.	Rev	Author	Line
1	2	jlechner	`-- File: wb_stage.vhd`
2			`-- Author: Jakob Lechner, Urban Stadler, Harald Trinkl, Christian Walter`
3			`-- Created: 2006-11-29`
4			`-- Last updated: 2006-11-29`
5
6			`-- Description:`
7			`-- Instruction decode stage`
8			`-------------------------------------------------------------------------------`
9
10			`library IEEE;`
11			`use IEEE.STD_LOGIC_1164.all;`
12			`use IEEE.STD_LOGIC_ARITH.all;`
13
14			`use WORK.RISE_PACK.all;`
15	71	jlechner	`use work.RISE_PACK_SPECIFIC.all;`
16	2	jlechner
17			`entity wb_stage is`
18
19			`port (`
20	61	cwalter	`clk : in std_logic;`
21			`reset : in std_logic;`
22	2	jlechner
23	61	cwalter	`mem_wb_register : in MEM_WB_REGISTER_T;`
24	2	jlechner
25	61	cwalter	`dreg_addr : out REGISTER_ADDR_T;`
26			`dreg : out REGISTER_T;`
27			`dreg_enable : out std_logic;`
28	2	jlechner
29	61	cwalter	`lr : out PC_REGISTER_T;`
30			`lr_enable : out std_logic;`
31
32			`sr : out SR_REGISTER_T;`
33			`sr_enable : out std_logic;`
34
35			`clear_out : out std_logic;`
36
37			`clear_reg_lock0 : out std_logic;`
38			`lock_reg_addr0 : out REGISTER_ADDR_T;`
39			`clear_reg_lock1 : out std_logic;`
40			`lock_reg_addr1 : out REGISTER_ADDR_T);`
41
42	122	trinklhar
43	2	jlechner	`end wb_stage;`
44
45			`architecture wb_stage_rtl of wb_stage is`
46
47			`begin -- wb_stage_rtl`
48	122	trinklhar
49	61	cwalter	`clear_out <= '0'; -- clear_out output is unused at the moment.`
50	2	jlechner
51	61	cwalter	`process (reset, mem_wb_register)`
52			`begin`
53			`if reset = '0' then`
54			`clear_reg_lock0 <= '0';`
55	76	cwalter	`lock_reg_addr0 <= (others => 'X');`
56	61	cwalter	`clear_reg_lock1 <= '0';`
57	76	cwalter	`lock_reg_addr1 <= (others => 'X');`
58	61	cwalter
59	76	cwalter	`dreg_enable <= '0';`
60			`dreg_addr <= (others => 'X');`
61			`dreg <= (others => 'X');`
62			`lr_enable <= '0';`
63			`lr <= (others => 'X');`
64			`sr_enable <= '0';`
65			`sr <= (others => 'X');`
66	122	trinklhar	`else`
67	119	trinklhar
68	61	cwalter	`-- write back of register value. --`
69			`dreg_addr <= mem_wb_register.dreg_addr;`
70			`if mem_wb_register.aluop1(ALUOP1_WB_REG_BIT) = '1' then`
71	106	cwalter	`if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then`
72			`dreg <= mem_wb_register.mem_reg;`
73			`else`
74			`dreg <= mem_wb_register.reg;`
75			`end if;`
76	61	cwalter	`dreg_enable <= '1';`
77			`clear_reg_lock0 <= '1';`
78			`lock_reg_addr0 <= mem_wb_register.dreg_addr;`
79			`else`
80			`dreg_enable <= '0';`
81	76	cwalter	`dreg <= (others => 'X');`
82	61	cwalter	`clear_reg_lock0 <= '0';`
83	76	cwalter	`lock_reg_addr0 <= (others => 'X');`
84	61	cwalter	`end if;`
85
86			`-- we have only one lock register.`
87			`assert mem_wb_register.aluop2(ALUOP2_SR_BIT) = '0' or mem_wb_register.aluop2(ALUOP2_LR_BIT) = '0';`
88
89			`clear_reg_lock1 <= '0';`
90	76	cwalter	`lock_reg_addr1 <= (others => 'X');`
91	61	cwalter	`-- write back of LR --`
92			`if mem_wb_register.aluop2(ALUOP2_LR_BIT) = '1' then`
93			`lr <= mem_wb_register.lr;`
94			`lr_enable <= '1';`
95			`clear_reg_lock1 <= '1';`
96			`lock_reg_addr1 <= LR_REGISTER_ADDR;`
97	83	cwalter	`else`
98			`lr <= ( others => 'X' );`
99			`lr_enable <= '0';`
100	61	cwalter	`end if;`
101	91	cwalter
102	61	cwalter	`-- write back of SR --`
103			`if mem_wb_register.aluop2(ALUOP2_SR_BIT) = '1' then`
104	91	cwalter	`-- calculate SR value`
105	83	cwalter	`sr <= mem_wb_register.sr;`
106	91	cwalter	`if mem_wb_register.aluop1(ALUOP1_LD_MEM_BIT) = '1' then`
107	95	cwalter	`if mem_wb_register.mem_reg = CONV_STD_LOGIC_VECTOR(0, REGISTER_WIDTH) then`
108			`sr( SR_REGISTER_ZERO ) <= '1';`
109			`end if;`
110			`if mem_wb_register.mem_reg( REGISTER_WIDTH - 1 ) = '1' then`
111			`sr( SR_REGISTER_NEGATIVE ) <= '1';`
112			`end if;`
113	91	cwalter	`end if;`
114	83	cwalter	`sr_enable <= '1';`
115	61	cwalter	`clear_reg_lock1 <= '1';`
116			`lock_reg_addr1 <= SR_REGISTER_ADDR;`
117	83	cwalter	`else`
118			`sr <= ( others => 'X' );`
119			`sr_enable <= '0';`
120	61	cwalter	`end if;`
121	91	cwalter
122
123	61	cwalter	`end if;`
124			`end process;`
125	2	jlechner	`end wb_stage_rtl;`

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[/] [rise/] [trunk/] [vhdl/] [wb_stage.vhd] - Blame information for rev 151