In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
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The RobustVerilog top source file is axi2ahb.v, it calls the top definition file named def_axi2ahb.txt.
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The default definition file def_axi2ahb.txt generates a bridge with 8 APB slaves.
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Changing the interconnect parameters should be made only in def_axi2ahb.txt in the src/base directory (changing slave num etc.).