OpenCores
URL https://opencores.org/ocsvn/robust_axi2ahb/robust_axi2ahb/trunk

Subversion Repositories robust_axi2ahb

[/] [robust_axi2ahb/] [trunk/] [src/] [base/] [axi2ahb_ctrl.v] - Blame information for rev 10

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 10 eyalhoc
<##//////////////////////////////////////////////////////////////////
2 5 eyalhoc
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28 10 eyalhoc
//////////////////////////////////////////////////////////////////##>
29 2 eyalhoc
 
30
INCLUDE def_axi2ahb.txt
31 4 eyalhoc
OUTFILE PREFIX_ctrl.v
32 2 eyalhoc
 
33 4 eyalhoc
module  PREFIX_ctrl (PORTS);
34 2 eyalhoc
 
35
 
36
   input                  clk;
37
   input                  reset;
38
 
39
   revport                GROUP_AHB;
40
 
41
   output                 ahb_finish;
42
   output                 rdata_phase;
43
   output                 wdata_phase;
44
   output                 data_last;
45
 
46
   input                  rdata_ready;
47
   input                  wdata_ready;
48
   input                  cmd_empty;
49
   input                  cmd_read;
50
   input [ADDR_BITS-1:0]  cmd_addr;
51
   input [3:0]            cmd_len;
52
   input [1:0]            cmd_size;
53
 
54
   parameter              TRANS_IDLE   = 2'b00;
55
   parameter              TRANS_BUSY   = 2'b01;
56
   parameter              TRANS_NONSEQ = 2'b10;
57
   parameter              TRANS_SEQ    = 2'b11;
58
 
59
   parameter              BURST_SINGLE = 3'b000;
60
   parameter              BURST_INCR4  = 3'b011;
61
   parameter              BURST_INCR8  = 3'b101;
62
   parameter              BURST_INCR16 = 3'b111;
63
 
64
 
65
   wire                   data_ready;
66
   wire                   ahb_idle;
67
   wire                   ahb_ack;
68
   wire                   ahb_ack_last;
69
   wire                   ahb_start;
70
   wire                   ahb_last;
71
   wire                   data_last;
72
   reg [4:0]              cmd_counter;
73
   reg                    rdata_phase;
74
   reg                    wdata_phase;
75
   wire                   data_phase;
76
   reg [1:0]              HTRANS;
77
   reg [2:0]              HBURST;
78
   reg [1:0]              HSIZE;
79
   reg                    HWRITE;
80
   reg [ADDR_BITS-1:0]    HADDR;
81
 
82
 
83
   assign                 ahb_finish   = ahb_ack_last;
84
 
85
   assign                 data_ready   = cmd_read ? rdata_ready : wdata_ready;
86
   assign                 data_phase   = wdata_phase | rdata_phase;
87
 
88
   assign                 ahb_idle     = HTRANS == TRANS_IDLE;
89
   assign                 ahb_ack      = HTRANS[1] & HREADY;
90
   assign                 ahb_ack_last = ahb_last & ahb_ack;
91
   assign                 ahb_start    = (~cmd_empty) & data_ready & ahb_idle & (HREADY | (~data_phase));
92
   assign                 data_last    = HREADY & (ahb_idle || (HTRANS == TRANS_NONSEQ));
93
 
94
   always @(posedge clk or posedge reset)
95
     if (reset)
96
       cmd_counter <= #FFD 4'd0;
97
     else if (ahb_ack_last)
98
       cmd_counter <= #FFD 4'd0;
99
     else if (ahb_ack)
100
       cmd_counter <= #FFD cmd_counter + 1'b1;
101
 
102
   assign             ahb_last = cmd_counter == cmd_len;
103
 
104
   always @(posedge clk or posedge reset)
105
     if (reset)
106
       rdata_phase <= #FFD 1'b0;
107
     else if (ahb_ack & (~HWRITE))
108
       rdata_phase <= #FFD 1'b1;
109
     else if (data_last)
110
       rdata_phase <= #FFD 1'b0;
111
 
112
   always @(posedge clk or posedge reset)
113
     if (reset)
114
       wdata_phase <= #FFD 1'b0;
115
     else if (ahb_ack & HWRITE)
116
       wdata_phase <= #FFD 1'b1;
117
     else if (data_last)
118
       wdata_phase <= #FFD 1'b0;
119
 
120
   always @(posedge clk or posedge reset)
121
     if (reset)
122
       HTRANS <= #FFD TRANS_IDLE;
123
     else if (ahb_start)
124
       HTRANS <= #FFD TRANS_NONSEQ;
125
     else if (ahb_ack_last)
126
       HTRANS <= #FFD TRANS_IDLE;
127
     else if (ahb_ack)
128
       HTRANS <= #FFD TRANS_SEQ;
129
 
130
   always @(posedge clk or posedge reset)
131
     if (reset)
132
       HBURST <= #FFD BURST_SINGLE;
133
     else if (ahb_start & (cmd_len == 4'd0))
134
       HBURST <= #FFD BURST_SINGLE;
135
     else if (ahb_start & (cmd_len == 4'd3))
136
       HBURST <= #FFD BURST_INCR4;
137
     else if (ahb_start & (cmd_len == 4'd7))
138
       HBURST <= #FFD BURST_INCR8;
139
     else if (ahb_start & (cmd_len == 4'd15))
140
       HBURST <= #FFD BURST_INCR16;
141
 
142
   always @(posedge clk or posedge reset)
143
     if (reset)
144
       HSIZE <= #FFD 2'b00;
145
     else if (ahb_start)
146
       HSIZE <= cmd_size;
147
 
148
   always @(posedge clk or posedge reset)
149
     if (reset)
150
       HWRITE <= #FFD 2'b00;
151
     else if (ahb_start)
152
       HWRITE <= (~cmd_read);
153
 
154
   always @(posedge clk or posedge reset)
155
     if (reset)
156
       HADDR <= #FFD {ADDR_BITS{1'b0}};
157
     else if (ahb_start)
158
       HADDR <= #FFD cmd_addr;
159
     else if (ahb_ack_last)
160
       HADDR <= #FFD {ADDR_BITS{1'b0}};
161
     else if (ahb_ack)
162
       HADDR <= #FFD HADDR + (
163
                              HSIZE == 2'b00 ? 4'd1 :
164
                              HSIZE == 2'b01 ? 4'd2 :
165
                              HSIZE == 2'b10 ? 4'd4 :
166
                              HSIZE == 2'b11 ? 4'd8 :
167
                              4'd0);
168
 
169
 
170
endmodule
171
 
172
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.