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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi2apb.txt
OUTFILE PREFIX_axi2apb_mux.v
 
ITER SX
module  PREFIX_axi2apb_mux (PORTS);
 
 
   input                      clk;
   input                      reset;
 
   input [ADDR_BITS-1:0]      cmd_addr;
 
   input                      psel;
   output [31:0]              prdata;
   output                     pready;
   output                     pslverr;
 
   output                     pselSX;
 
   input                      preadySX;
 
   input                      pslverrSX;
 
   input [31:0]               prdataSX;
 
 
 
   parameter                  ADDR_MSB = EXPR(ADDR_BITS-1);
   parameter                  ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);
 
   reg                        pready;
   reg                        pslverr_pre;
   reg                        pslverr;
   reg [31:0]                 prdata_pre;
   reg [31:0]                 prdata;
 
   reg [SLV_BITS-1:0]         slave_num;
 
   always @(*)
     begin
        casex (cmd_addr[ADDR_MSB:ADDR_LSB])
          DEC_ADDRSX : slave_num = SLV_BITS'dSX;
 
          default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error
        endcase
     end
 
   assign                     pselSX = psel & (slave_num == SLV_BITS'dSX);
 
   always @(*)
     begin
           case (slave_num)
             SLV_BITS'dSX: pready = preadySX;
                 default : pready = 1'b1; //decode error
           endcase
         end
 
   always @(*)
     begin
           case (slave_num)
             SLV_BITS'dSX: pslverr_pre = pslverrSX;
                 default : pslverr_pre = 1'b1; //decode error
           endcase
         end
 
   always @(*)
     begin
           case (slave_num)
             SLV_BITS'dSX: prdata_pre = prdataSX;
                 default : prdata_pre = {32{1'b0}};
           endcase
         end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
           begin
         prdata  <= #FFD {32{1'b0}};
         pslverr <= #FFD 1'b0;
           end
         else if (psel & pready)
           begin
         prdata  <= #FFD prdata_pre;
         pslverr <= #FFD pslverr_pre;
           end
         else if (~psel)
           begin
         prdata  <= #FFD {32{1'b0}};
         pslverr <= #FFD 1'b0;
           end
 
endmodule
 
 

Line No.	Rev	Author	Line
1	4	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////##>`
29
30	2	eyalhoc	`INCLUDE def_axi2apb.txt`
31			`OUTFILE PREFIX_axi2apb_mux.v`
32
33			`ITER SX`
34			`module PREFIX_axi2apb_mux (PORTS);`
35
36
37			`input clk;`
38			`input reset;`
39
40			`input [ADDR_BITS-1:0] cmd_addr;`
41
42			`input psel;`
43			`output [31:0] prdata;`
44			`output pready;`
45			`output pslverr;`
46
47			`output pselSX;`
48
49			`input preadySX;`
50
51			`input pslverrSX;`
52
53			`input [31:0] prdataSX;`
54
55
56
57			`parameter ADDR_MSB = EXPR(ADDR_BITS-1);`
58			`parameter ADDR_LSB = EXPR(ADDR_BITS-DEC_BITS);`
59
60			`reg pready;`
61			`reg pslverr_pre;`
62			`reg pslverr;`
63			`reg [31:0] prdata_pre;`
64			`reg [31:0] prdata;`
65
66			`reg [SLV_BITS-1:0] slave_num;`
67
68			`always @(*)`
69			`begin`
70			`casex (cmd_addr[ADDR_MSB:ADDR_LSB])`
71			`DEC_ADDRSX : slave_num = SLV_BITS'dSX;`
72
73			`default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error`
74			`endcase`
75			`end`
76
77			`assign pselSX = psel & (slave_num == SLV_BITS'dSX);`
78
79			`always @(*)`
80			`begin`
81			`case (slave_num)`
82			`SLV_BITS'dSX: pready = preadySX;`
83			`default : pready = 1'b1; //decode error`
84			`endcase`
85			`end`
86
87			`always @(*)`
88			`begin`
89			`case (slave_num)`
90			`SLV_BITS'dSX: pslverr_pre = pslverrSX;`
91			`default : pslverr_pre = 1'b1; //decode error`
92			`endcase`
93			`end`
94
95			`always @(*)`
96			`begin`
97			`case (slave_num)`
98			`SLV_BITS'dSX: prdata_pre = prdataSX;`
99			`default : prdata_pre = {32{1'b0}};`
100			`endcase`
101			`end`
102
103
104			`always @(posedge clk or posedge reset)`
105			`if (reset)`
106			`begin`
107			`prdata <= #FFD {32{1'b0}};`
108			`pslverr <= #FFD 1'b0;`
109			`end`
110			`else if (psel & pready)`
111			`begin`
112			`prdata <= #FFD prdata_pre;`
113			`pslverr <= #FFD pslverr_pre;`
114			`end`
115			`else if (~psel)`
116			`begin`
117			`prdata <= #FFD {32{1'b0}};`
118			`pslverr <= #FFD 1'b0;`
119			`end`
120
121			`endmodule`
122
123

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[/] [robust_axi2apb/] [trunk/] [src/] [base/] [axi2apb_mux.v] - Blame information for rev 4