Back to project
URL
https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk
[/ ] [robust_axi_fabric/ ] [trunk/ ] [README.txt ] - Blame information for rev 11
Go to most recent revision Details Compare with Previous View Log
Line No.
Rev
Author
Line
1
2 eyalhoc
2
------------------------------ Remark ----------------------------------------
3
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
4
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
5
6 eyalhoc
6
We will be very happy to receive any kind of feedback regarding our tools and cores.
7
We will also be willing to support any company intending to integrate our cores into their project.
8
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
9
2 eyalhoc
------------------------------------------------------------------------------
10
11
RobustVerilog generic AXI interconnect fabric
12
13
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
14
15
The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.
16
17
4 eyalhoc
The default definition file def_ic.txt generates a fabric with 3 masters and 6 slaves.
18
2 eyalhoc
19
Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).
20
21
22
23
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
