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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 22

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<##//////////////////////////////////////////////////////////////////
////                                                             ////
////  Author: Eyal Hochberg                                      ////
////          eyal@provartec.com                                 ////
////                                                             ////
////  Downloaded from: http://www.opencores.org                  ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2010 Provartec LTD                            ////
//// www.provartec.com                                           ////
//// info@provartec.com                                          ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
//// This source file is free software; you can redistribute it  ////
//// and/or modify it under the terms of the GNU Lesser General  ////
//// Public License as published by the Free Software Foundation.////
////                                                             ////
//// This source is distributed in the hope that it will be      ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
//// PURPOSE.  See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html              ////
////                                                             ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_ic_decerr.v
 
module PREFIX_ic_decerr(PORTS);
 
   input                          clk;
   input                          reset;
 
   input                          AWIDOK;
   input                          ARIDOK;
   port                           GROUP_IC_AXI;
 
 
   parameter                      RESP_SLVERR = 2'b10;
   parameter                      RESP_DECERR = 2'b11;
 
 
   reg                            AWREADY;
   reg [ID_BITS-1:0]               BID;
   reg [1:0]                       BRESP;
   reg                            BVALID;
   reg                            ARREADY;
   reg [ID_BITS-1:0]               RID;
   reg [1:0]                       RRESP;
   reg                            RVALID;
   reg [4-1:0]                    rvalid_cnt;
 
IFDEF TRUE (USER_BITS>0)
   assign                         BUSER = 'd0;
   assign                         RUSER = 'd0;
ENDIF TRUE (USER_BITS>0)
 
   assign                         RDATA = {DATA_BITS{1'b0}};
 
 
   //WRITE
   assign                         WREADY = 1'b1;
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          AWREADY <= #FFD 1'b1;
          BID     <= #FFD {ID_BITS{1'b0}};
          BRESP   <= #FFD 2'b00;
       end
     else if (BVALID & BREADY)
       begin
          AWREADY <= #FFD 1'b1;
       end
     else if (AWVALID & AWREADY)
       begin
          AWREADY <= #FFD 1'b0;
          BID     <= #FFD AWID;
          BRESP   <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
       end
 
   always @(posedge clk or posedge reset)
     if (reset)
       BVALID <= #FFD 1'b0;
     else if (WVALID & WREADY & WLAST)
       BVALID <= #FFD 1'b1;
     else if (BVALID & BREADY)
       BVALID <= #FFD 1'b0;
 
 
   //READ   
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          ARREADY <= #FFD 1'b1;
          RID     <= #FFD {ID_BITS{1'b0}};
          RRESP   <= #FFD 2'b00;
       end
     else if (RVALID & RREADY & RLAST)
       begin
          ARREADY <= #FFD 1'b1;
       end
     else if (ARVALID & ARREADY)
       begin
          ARREADY <= #FFD 1'b0;
          RID     <= #FFD ARID;
          RRESP   <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
       end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY & RLAST)
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY)
       rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
     else if (ARVALID & ARREADY)
       rvalid_cnt <= #FFD ARLEN;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       RVALID <= #FFD 1'b0;
     else if (RVALID & RREADY & RLAST)
       RVALID <= #FFD 1'b0;
     else if (ARVALID & ARREADY)
       RVALID <= #FFD 1'b1;
 
   assign RLAST = (rvalid_cnt == 'd0) & RVALID;
 
 
 
 
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	7	eyalhoc	`<##//////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Author: Eyal Hochberg ////`
4			`//// eyal@provartec.com ////`
5			`//// ////`
6			`//// Downloaded from: http://www.opencores.org ////`
7			`/////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// Copyright (C) 2010 Provartec LTD ////`
10			`//// www.provartec.com ////`
11			`//// info@provartec.com ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer.////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation.////`
21			`//// ////`
22			`//// This source is distributed in the hope that it will be ////`
23			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
24			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
25			`//// PURPOSE. See the GNU Lesser General Public License for more////`
26			`//// details. http://www.gnu.org/licenses/lgpl.html ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////##>`
29
30	2	eyalhoc	`OUTFILE PREFIX_ic_decerr.v`
31
32			`module PREFIX_ic_decerr(PORTS);`
33
34			`input clk;`
35			`input reset;`
36
37			`input AWIDOK;`
38			`input ARIDOK;`
39			`port GROUP_IC_AXI;`
40
41
42			`parameter RESP_SLVERR = 2'b10;`
43			`parameter RESP_DECERR = 2'b11;`
44
45
46			`reg AWREADY;`
47			`reg [ID_BITS-1:0] BID;`
48			`reg [1:0] BRESP;`
49			`reg BVALID;`
50			`reg ARREADY;`
51			`reg [ID_BITS-1:0] RID;`
52			`reg [1:0] RRESP;`
53			`reg RVALID;`
54	12	eyalhoc	`reg [4-1:0] rvalid_cnt;`
55	2	eyalhoc
56	12	eyalhoc	`IFDEF TRUE (USER_BITS>0)`
57	2	eyalhoc	`assign BUSER = 'd0;`
58			`assign RUSER = 'd0;`
59	12	eyalhoc	`ENDIF TRUE (USER_BITS>0)`
60
61	2	eyalhoc	`assign RDATA = {DATA_BITS{1'b0}};`
62
63
64			`//WRITE`
65			`assign WREADY = 1'b1;`
66
67			`always @(posedge clk or posedge reset)`
68			`if (reset)`
69			`begin`
70			`AWREADY <= #FFD 1'b1;`
71			`BID <= #FFD {ID_BITS{1'b0}};`
72			`BRESP <= #FFD 2'b00;`
73			`end`
74			`else if (BVALID & BREADY)`
75			`begin`
76			`AWREADY <= #FFD 1'b1;`
77			`end`
78			`else if (AWVALID & AWREADY)`
79			`begin`
80			`AWREADY <= #FFD 1'b0;`
81			`BID <= #FFD AWID;`
82			`BRESP <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;`
83			`end`
84
85			`always @(posedge clk or posedge reset)`
86			`if (reset)`
87			`BVALID <= #FFD 1'b0;`
88			`else if (WVALID & WREADY & WLAST)`
89			`BVALID <= #FFD 1'b1;`
90			`else if (BVALID & BREADY)`
91			`BVALID <= #FFD 1'b0;`
92
93
94			`//READ`
95			`always @(posedge clk or posedge reset)`
96			`if (reset)`
97			`begin`
98			`ARREADY <= #FFD 1'b1;`
99			`RID <= #FFD {ID_BITS{1'b0}};`
100			`RRESP <= #FFD 2'b00;`
101			`end`
102			`else if (RVALID & RREADY & RLAST)`
103			`begin`
104			`ARREADY <= #FFD 1'b1;`
105			`end`
106			`else if (ARVALID & ARREADY)`
107			`begin`
108			`ARREADY <= #FFD 1'b0;`
109			`RID <= #FFD ARID;`
110			`RRESP <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;`
111			`end`
112
113
114			`always @(posedge clk or posedge reset)`
115			`if (reset)`
116			`rvalid_cnt <= #FFD {4{1'b0}};`
117			`else if (RVALID & RREADY & RLAST)`
118			`rvalid_cnt <= #FFD {4{1'b0}};`
119			`else if (RVALID & RREADY)`
120			`rvalid_cnt <= #FFD rvalid_cnt - 1'b1;`
121			`else if (ARVALID & ARREADY)`
122			`rvalid_cnt <= #FFD ARLEN;`
123
124
125			`always @(posedge clk or posedge reset)`
126			`if (reset)`
127			`RVALID <= #FFD 1'b0;`
128			`else if (RVALID & RREADY & RLAST)`
129			`RVALID <= #FFD 1'b0;`
130			`else if (ARVALID & ARREADY)`
131			`RVALID <= #FFD 1'b1;`
132
133			`assign RLAST = (rvalid_cnt == 'd0) & RVALID;`
134
135
136
137
138
139
140			`endmodule`
141
142

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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 22