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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 5

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OUTFILE PREFIX_ic_decerr.v
 
module PREFIX_ic_decerr(PORTS);
 
   input                          clk;
   input                          reset;
 
   input                          AWIDOK;
   input                          ARIDOK;
   port                           GROUP_IC_AXI;
 
 
   parameter                      RESP_SLVERR = 2'b10;
   parameter                      RESP_DECERR = 2'b11;
 
 
   reg                            AWREADY;
   reg [ID_BITS-1:0]               BID;
   reg [1:0]                       BRESP;
   reg                            BVALID;
   reg                            ARREADY;
   reg [ID_BITS-1:0]               RID;
   reg [1:0]                       RRESP;
   reg                            RVALID;
   reg [4-1:0]             rvalid_cnt;
 
 
   assign                         BUSER = 'd0;
   assign                         RUSER = 'd0;
   assign                         RDATA = {DATA_BITS{1'b0}};
 
 
   //WRITE
   assign                         WREADY = 1'b1;
 
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          AWREADY <= #FFD 1'b1;
          BID     <= #FFD {ID_BITS{1'b0}};
          BRESP   <= #FFD 2'b00;
       end
     else if (BVALID & BREADY)
       begin
          AWREADY <= #FFD 1'b1;
       end
     else if (AWVALID & AWREADY)
       begin
          AWREADY <= #FFD 1'b0;
          BID     <= #FFD AWID;
          BRESP   <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
       end
 
   always @(posedge clk or posedge reset)
     if (reset)
       BVALID <= #FFD 1'b0;
     else if (WVALID & WREADY & WLAST)
       BVALID <= #FFD 1'b1;
     else if (BVALID & BREADY)
       BVALID <= #FFD 1'b0;
 
 
   //READ   
   always @(posedge clk or posedge reset)
     if (reset)
       begin
          ARREADY <= #FFD 1'b1;
          RID     <= #FFD {ID_BITS{1'b0}};
          RRESP   <= #FFD 2'b00;
       end
     else if (RVALID & RREADY & RLAST)
       begin
          ARREADY <= #FFD 1'b1;
       end
     else if (ARVALID & ARREADY)
       begin
          ARREADY <= #FFD 1'b0;
          RID     <= #FFD ARID;
          RRESP   <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
       end
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY & RLAST)
       rvalid_cnt <= #FFD {4{1'b0}};
     else if (RVALID & RREADY)
       rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
     else if (ARVALID & ARREADY)
       rvalid_cnt <= #FFD ARLEN;
 
 
   always @(posedge clk or posedge reset)
     if (reset)
       RVALID <= #FFD 1'b0;
     else if (RVALID & RREADY & RLAST)
       RVALID <= #FFD 1'b0;
     else if (ARVALID & ARREADY)
       RVALID <= #FFD 1'b1;
 
   assign RLAST = (rvalid_cnt == 'd0) & RVALID;
 
 
 
 
 
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`OUTFILE PREFIX_ic_decerr.v`
2
3			`module PREFIX_ic_decerr(PORTS);`
4
5			`input clk;`
6			`input reset;`
7
8			`input AWIDOK;`
9			`input ARIDOK;`
10			`port GROUP_IC_AXI;`
11
12
13			`parameter RESP_SLVERR = 2'b10;`
14			`parameter RESP_DECERR = 2'b11;`
15
16
17			`reg AWREADY;`
18			`reg [ID_BITS-1:0] BID;`
19			`reg [1:0] BRESP;`
20			`reg BVALID;`
21			`reg ARREADY;`
22			`reg [ID_BITS-1:0] RID;`
23			`reg [1:0] RRESP;`
24			`reg RVALID;`
25			`reg [4-1:0] rvalid_cnt;`
26
27
28			`assign BUSER = 'd0;`
29			`assign RUSER = 'd0;`
30			`assign RDATA = {DATA_BITS{1'b0}};`
31
32
33			`//WRITE`
34			`assign WREADY = 1'b1;`
35
36			`always @(posedge clk or posedge reset)`
37			`if (reset)`
38			`begin`
39			`AWREADY <= #FFD 1'b1;`
40			`BID <= #FFD {ID_BITS{1'b0}};`
41			`BRESP <= #FFD 2'b00;`
42			`end`
43			`else if (BVALID & BREADY)`
44			`begin`
45			`AWREADY <= #FFD 1'b1;`
46			`end`
47			`else if (AWVALID & AWREADY)`
48			`begin`
49			`AWREADY <= #FFD 1'b0;`
50			`BID <= #FFD AWID;`
51			`BRESP <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;`
52			`end`
53
54			`always @(posedge clk or posedge reset)`
55			`if (reset)`
56			`BVALID <= #FFD 1'b0;`
57			`else if (WVALID & WREADY & WLAST)`
58			`BVALID <= #FFD 1'b1;`
59			`else if (BVALID & BREADY)`
60			`BVALID <= #FFD 1'b0;`
61
62
63			`//READ`
64			`always @(posedge clk or posedge reset)`
65			`if (reset)`
66			`begin`
67			`ARREADY <= #FFD 1'b1;`
68			`RID <= #FFD {ID_BITS{1'b0}};`
69			`RRESP <= #FFD 2'b00;`
70			`end`
71			`else if (RVALID & RREADY & RLAST)`
72			`begin`
73			`ARREADY <= #FFD 1'b1;`
74			`end`
75			`else if (ARVALID & ARREADY)`
76			`begin`
77			`ARREADY <= #FFD 1'b0;`
78			`RID <= #FFD ARID;`
79			`RRESP <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;`
80			`end`
81
82
83			`always @(posedge clk or posedge reset)`
84			`if (reset)`
85			`rvalid_cnt <= #FFD {4{1'b0}};`
86			`else if (RVALID & RREADY & RLAST)`
87			`rvalid_cnt <= #FFD {4{1'b0}};`
88			`else if (RVALID & RREADY)`
89			`rvalid_cnt <= #FFD rvalid_cnt - 1'b1;`
90			`else if (ARVALID & ARREADY)`
91			`rvalid_cnt <= #FFD ARLEN;`
92
93
94			`always @(posedge clk or posedge reset)`
95			`if (reset)`
96			`RVALID <= #FFD 1'b0;`
97			`else if (RVALID & RREADY & RLAST)`
98			`RVALID <= #FFD 1'b0;`
99			`else if (ARVALID & ARREADY)`
100			`RVALID <= #FFD 1'b1;`
101
102			`assign RLAST = (rvalid_cnt == 'd0) & RVALID;`
103
104
105
106
107
108
109			`endmodule`
110
111

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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_decerr.v] - Blame information for rev 5