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[/] [robust_axi_fabric/] [trunk/] [src/] [base/] [ic_registry_wr.v] - Blame information for rev 22

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1 7 eyalhoc
<##//////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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//////////////////////////////////////////////////////////////////##>
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30 2 eyalhoc
OUTFILE PREFIX_ic_registry_wr.v
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ITER MX
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ITER SX
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module PREFIX_ic_registry_wr(PORTS);
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   input                            clk;
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   input                            reset;
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   port                             MMX_AWGROUP_IC_AXI_CMD;
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   input [ID_BITS-1:0]              MMX_WID;
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   input                            MMX_WVALID;
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   input                            MMX_WREADY;
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   input                            MMX_WLAST;
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   output [SLV_BITS-1:0]            MMX_WSLV;
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   output                           MMX_WOK;
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   input                            SSX_AWVALID;
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   input                            SSX_AWREADY;
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   input [MSTR_BITS-1:0]            SSX_AWMSTR;
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   input                            SSX_WVALID;
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   input                            SSX_WREADY;
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   input                            SSX_WLAST;
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   wire                             AWmatch_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             Wmatch_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             cmd_push_MMX;
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   wire                             cmd_push_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             cmd_pop_MMX;
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   wire                             cmd_pop_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             slave_empty_MMX;
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   wire [SLV_BITS-1:0]              slave_in_MMX_IDGROUP_MMX_ID.IDX;
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   wire [SLV_BITS-1:0]              slave_out_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             slave_empty_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             slave_full_MMX_IDGROUP_MMX_ID.IDX;
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   wire                             cmd_push_SSX;
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   wire                             cmd_pop_SSX;
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   wire [MSTR_BITS-1:0]             master_in_SSX;
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   wire [MSTR_BITS-1:0]             master_out_SSX;
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   wire                             master_empty_SSX;
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   wire                             master_full_SSX;
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   reg [SLV_BITS-1:0]               MMX_WSLV;
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   reg                              MMX_WOK;
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   reg                              MMX_pending;
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   reg                              MMX_pending_d;
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   wire                             MMX_pending_rise;
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   reg                              SSX_pending;
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   reg                              SSX_pending_d;
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   wire                             SSX_pending_rise;
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   assign                           AWmatch_MMX_IDGROUP_MMX_ID.IDX  = MMX_AWID == ID_BITS'bADD_IDGROUP_MMX_ID;
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   assign                           Wmatch_MMX_IDGROUP_MMX_ID.IDX   = MMX_WID == ID_BITS'bADD_IDGROUP_MMX_ID;
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   assign                           cmd_push_MMX           = MMX_AWVALID & (MMX_pending ? MMX_pending_rise : MMX_AWREADY);
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   assign                           cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & AWmatch_MMX_IDGROUP_MMX_ID.IDX;
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   assign                           cmd_pop_MMX            = MMX_WVALID & MMX_WREADY & MMX_WLAST;
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   assign                           cmd_pop_MMX_IDGROUP_MMX_ID.IDX  = cmd_pop_MMX & Wmatch_MMX_IDGROUP_MMX_ID.IDX;
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   assign                           cmd_push_SSX           = SSX_AWVALID & (SSX_pending ? SSX_pending_rise : SSX_AWREADY);
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   assign                           cmd_pop_SSX            = SSX_WVALID & SSX_WREADY & SSX_WLAST;
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   assign                           master_in_SSX          = SSX_AWMSTR;
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   assign                           slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_AWSLV;
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   assign                           MMX_pending_rise = MMX_pending & (~MMX_pending_d);
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   assign                           SSX_pending_rise = SSX_pending & (~SSX_pending_d);
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   always @(posedge clk or posedge reset)
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     if (reset)
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       begin
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          MMX_pending   <= #FFD 1'b0;
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          MMX_pending_d <= #FFD 1'b0;
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          SSX_pending   <= #FFD 1'b0;
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          SSX_pending_d <= #FFD 1'b0;
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       end
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     else
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       begin
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          MMX_pending   <= #FFD MMX_AWVALID & (~MMX_AWREADY);
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          MMX_pending_d <= #FFD MMX_pending;
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          SSX_pending   <= #FFD SSX_AWVALID & (~SSX_AWREADY);
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          SSX_pending_d <= #FFD SSX_pending;
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       end
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   LOOP MX
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   always @(*)
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     begin
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        case (MMX_WID)
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          ID_BITS'bADD_IDGROUP_MMX_ID : MMX_WSLV = slave_out_MMX_IDGROUP_MMX_ID.IDX;
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          default : MMX_WSLV = SERR;
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        endcase
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     end
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   always @(*)
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     begin
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        case (MMX_WSLV)
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          SLV_BITS'dSX : MMX_WOK = (master_out_SSX == MSTR_BITS'dMX) & (~slave_empty_MMX);
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          default : MMX_WOK = 1'b0;
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        endcase
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     end
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   ENDLOOP MX
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LOOP MX
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  assign slave_empty_MMX = GONCAT(slave_empty_MMX_IDGROUP_MMX_ID.IDX &);
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 LOOP IX GROUP_MMX_ID.NUM
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   prgen_fifo #(SLV_BITS, CMD_DEPTH)
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   slave_fifo_MMX_IDIX(
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                       .clk(clk),
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                       .reset(reset),
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                       .push(cmd_push_MMX_IDIX),
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                       .pop(cmd_pop_MMX_IDIX),
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                       .din(slave_in_MMX_IDIX),
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                       .dout(slave_out_MMX_IDIX),
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                       .empty(slave_empty_MMX_IDIX),
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                       .full(slave_full_MMX_IDIX)
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                       );
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 ENDLOOP IX
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ENDLOOP MX
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LOOP SX
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   prgen_fifo #(MSTR_BITS, SLV_DEPTH)
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   master_fifo_SSX(
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                   .clk(clk),
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                   .reset(reset),
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                   .push(cmd_push_SSX),
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                   .pop(cmd_pop_SSX),
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                   .din(master_in_SSX),
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                   .dout(master_out_SSX),
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                   .empty(master_empty_SSX),
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                   .full(master_full_SSX)
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                   );
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ENDLOOP SX
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endmodule
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