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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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OUTDIR fir_NAME
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OUTFILE fir_NAME.v
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INCLUDE def_fir.txt
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ITER CX COEFF_NUM
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## Expected RobustVerilog parameters:
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## SWAP ORDER val - order of FIR
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## SWAP COEFF_BITS val - precision of coeeficients (bit num)
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## SWAP DIN_BITS val - precision of input data (bit num)
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## SWAP MAC_NUM val - number of multiplayers (determines architecture)
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// Built In Parameters:
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//
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// Filter Order = ORDER
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// Input Precision = DIN_BITS
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// Coefficient Precision = COEFF_BITS
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// Number of serial FIR sons = MAC_NUM
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// Number of multiplayers = MAC_NUM
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// Architecture = ARCH
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// Sum of Products Latency = LATENCY
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module fir_NAME (PORTS);
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input clk;
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input reset;
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input [EXPR(COEFF_BITS-1):0] kCX;
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input [EXPR(DIN_BITS-1):0] data_in;
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output [EXPR(DOUT_BITS-1):0] data_out;
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input valid_in;
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output valid_out;
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IFDEF MAC_EQ(1)
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CREATE fir_serial.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
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fir_serial_TOPO fir(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
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ELSE MAC_EQ(1)
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IFDEF MAC_EQ(COEFF_NUM)
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CREATE fir_parallel.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
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fir_parallel_TOPO fir(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
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ELSE MAC_EQ(COEFF_NUM)
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CREATE fir_Nserial.v def_fir_Nserial.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS) DEFCMD(SWAP CONST(MAC_NUM) MAC_NUM)
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fir_MAC_NUMserial_TOPO fir(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
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ENDIF MAC_EQ(COEFF_NUM)
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ENDIF MAC_EQ(1)
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endmodule
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