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[/] [robust_fir/] [trunk/] [src/] [base/] [fir_parallel.v] - Blame information for rev 2

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1 2 eyalhoc
OUTFILE fir_parallel_TOPO.v
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ITER OX ORDER
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ITER CX COEFF_NUM
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ITER SX ADD_STAGES
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//  Built In Parameters:
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//  
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//    Filter Order             = ORDER
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//    Input Precision          = DIN_BITS
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//    Coefficient Precision    = COEFF_BITS
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//    Sum of Products Latency  = LATENCY
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//    Number of multiplayers   = COEFF_NUM
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module fir_parallel_TOPO (PORTS);
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        input  clk;
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        input  reset;
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        input  clken;
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        input  [EXPR(COEFF_BITS-1):0] kCX;
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        input  [EXPR(DIN_BITS-1):0] data_in;
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        output [EXPR(DOUT_BITS-1):0] data_out;
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        output valid_out;
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        wire [EXPR(DIN_BITS-1):0] data_in_d0;
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        wire [EXPR(DIN_BITS-1):0] data_in_dEXPR(OX+1);
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        reg [EXPR(MULT_BITS-1):0] multCX;
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        //delay inputs per multiplayer
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    assign data_in_d0 = data_in;
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    CREATE prgen_delayN.v DEFCMD(SWAP DELAY 1) DEFCMD(DEFINE CLKEN)
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    prgen_delay1_en #(DIN_BITS) delay_dinOX (clk, reset, clken, data_in_dOX, data_in_dEXPR(OX+1));
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        always @(posedge clk or posedge reset)
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          if (reset)
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            begin
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                  multCX <= #FFD {MULT_BITS{1'b0}};
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            end
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      else if (clken)
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            begin
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                  multCX <= #FFD kCX * data_in_dCX;
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            end
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        //Pipline the output additions
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        CREATE bintree_adder.v DEFCMD(SWAP INPUT_NUM COEFF_NUM)
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        bintree_adder_COEFF_NUM #(MULT_BITS) bintree_adder(
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                .clk(clk),
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                .reset(reset),
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                .data_inCX(multCX),
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                .data_out(data_out),
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                .valid_in(clken),
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                .valid_out(valid_out)
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        );
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endmodule
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