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[/] [robust_fir/] [trunk/] [src/] [base/] [fir_serial.v] - Blame information for rev 2

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OUTFILE fir_serial_TOPO.v
 
ITER OX ORDER
ITER CX COEFF_NUM
ITER SX ADD_STAGES
 
//  Built In Parameters:
//  
//    Filter Order             = ORDER
//    Input Precision          = DIN_BITS
//    Coefficient Precision    = COEFF_BITS
//    Sum of Products Latency  = LATENCY
 
module fir_serial_TOPO (PORTS);
 
        input  clk;
        input  reset;
    input  clken;
        input  [EXPR(COEFF_BITS-1):0] kCX;
        input  [EXPR(DIN_BITS-1):0] data_in;
        output [EXPR(DOUT_BITS-1):0] data_out;
        output valid;
 
    wire [EXPR(COEFF_BITS-1):0] k;
    wire [EXPR(MULT_BITS-1):0] mult;
    reg [EXPR(DOUT_BITS-1):0] multCX;
    wire [EXPR(DOUT_BITS-1):0] add;
        wire addCX;
        reg [EXPR(DOUT_BITS-1):0] mult_sum;
        reg [EXPR(DOUT_BITS-1):0] data_out;
        reg valid;
 
        reg active;
    reg [EXPR(ADD_STAGES-1):0] phase;
    reg [EXPR(ADD_STAGES-1):0] cycle;
 
        wire phaseCX;
        wire cycleCX;
 
        assign phaseCX = phase == 'dCX;
        assign cycleCX = cycle == 'dCX;
 
    assign k =
          phaseOX ? kOX :
          kORDER;
 
    //a single multiplayer and a single adder
    assign mult = k * data_in;
        assign add  = mult + (
                                  addOX ? multOX :
                                          multORDER);
 
 
    always @(posedge clk or posedge reset)
      if (reset)
        active <= #FFD 1'b0;
          else if (clken)
        active <= #FFD 1'b1;
          else if (phase == 'dORDER)
        active <= #FFD 1'b0;
 
    always @(posedge clk or posedge reset)
      if (reset)
        phase <= #FFD {ADD_STAGES{1'b0}};
      else if (phase == 'dORDER)
        phase <= #FFD {ADD_STAGES{1'b0}};
      else if (active)
        phase <= #FFD phase + 1'b1;
 
    always @(posedge clk or posedge reset)
      if (reset)
        cycle <= #FFD {ADD_STAGES{1'b0}};
          else if (phase == 'dORDER)
            begin
                  if (cycle == 'dORDER)
            cycle <= #FFD {ADD_STAGES{1'b0}};
                  else
            cycle <= cycle + 1'b1;
                end
 
LOOP PX COEFF_NUM
        assign addPX = active & (
            (phaseEXPR((COEFF_NUM+PX-CX)%COEFF_NUM) && cycleCX) ||
                STOMP || );
 
        always @(posedge clk or posedge reset)
          if (reset)
            multPX <= #FFD {MULT_BITS{1'b0}};
          else if (phase1 && cyclePX)
            multPX <= #FFD {MULT_BITS{1'b0}};
          else if (addPX)
            multPX <= #FFD add;
 
ENDLOOP PX
 
 
 //sample when valid
 always @(posedge clk or posedge reset)
  if (reset)
    mult_sum <= #FFD {DOUT_BITS{1'b0}};
  else if (phase1)
    begin
LOOP CX COEFF_NUM
        if (cycleCX)
    mult_sum <= #FFD multCX;
        else
STOMP NEWLINE
ENDLOOP CX
STOMP else
    end
 
 //sync to clock enable
 always @(posedge clk or posedge reset)
  if (reset)
    begin
      data_out <= #FFD {DOUT_BITS{1'b0}};
          valid <= #FFD 1'b0;
        end
  else if (clken)
    begin
      data_out <= #FFD mult_sum;
          valid <= #FFD 1'b1;
        end
  else
    begin
          valid <= #FFD 1'b0;
        end
 
 
endmodule
 
 
 
 
 

Line No.	Rev	Author	Line
1	2	eyalhoc	`OUTFILE fir_serial_TOPO.v`
2
3			`ITER OX ORDER`
4			`ITER CX COEFF_NUM`
5			`ITER SX ADD_STAGES`
6
7			`// Built In Parameters:`
8			`//`
9			`// Filter Order = ORDER`
10			`// Input Precision = DIN_BITS`
11			`// Coefficient Precision = COEFF_BITS`
12			`// Sum of Products Latency = LATENCY`
13
14			`module fir_serial_TOPO (PORTS);`
15
16			`input clk;`
17			`input reset;`
18			`input clken;`
19			`input [EXPR(COEFF_BITS-1):0] kCX;`
20			`input [EXPR(DIN_BITS-1):0] data_in;`
21			`output [EXPR(DOUT_BITS-1):0] data_out;`
22			`output valid;`
23
24			`wire [EXPR(COEFF_BITS-1):0] k;`
25			`wire [EXPR(MULT_BITS-1):0] mult;`
26			`reg [EXPR(DOUT_BITS-1):0] multCX;`
27			`wire [EXPR(DOUT_BITS-1):0] add;`
28			`wire addCX;`
29			`reg [EXPR(DOUT_BITS-1):0] mult_sum;`
30			`reg [EXPR(DOUT_BITS-1):0] data_out;`
31			`reg valid;`
32
33			`reg active;`
34			`reg [EXPR(ADD_STAGES-1):0] phase;`
35			`reg [EXPR(ADD_STAGES-1):0] cycle;`
36
37			`wire phaseCX;`
38			`wire cycleCX;`
39
40			`assign phaseCX = phase == 'dCX;`
41			`assign cycleCX = cycle == 'dCX;`
42
43			`assign k =`
44			`phaseOX ? kOX :`
45			`kORDER;`
46
47			`//a single multiplayer and a single adder`
48			`assign mult = k * data_in;`
49			`assign add = mult + (`
50			`addOX ? multOX :`
51			`multORDER);`
52
53
54			`always @(posedge clk or posedge reset)`
55			`if (reset)`
56			`active <= #FFD 1'b0;`
57			`else if (clken)`
58			`active <= #FFD 1'b1;`
59			`else if (phase == 'dORDER)`
60			`active <= #FFD 1'b0;`
61
62			`always @(posedge clk or posedge reset)`
63			`if (reset)`
64			`phase <= #FFD {ADD_STAGES{1'b0}};`
65			`else if (phase == 'dORDER)`
66			`phase <= #FFD {ADD_STAGES{1'b0}};`
67			`else if (active)`
68			`phase <= #FFD phase + 1'b1;`
69
70			`always @(posedge clk or posedge reset)`
71			`if (reset)`
72			`cycle <= #FFD {ADD_STAGES{1'b0}};`
73			`else if (phase == 'dORDER)`
74			`begin`
75			`if (cycle == 'dORDER)`
76			`cycle <= #FFD {ADD_STAGES{1'b0}};`
77			`else`
78			`cycle <= cycle + 1'b1;`
79			`end`
80
81			`LOOP PX COEFF_NUM`
82			`assign addPX = active & (`
83			`(phaseEXPR((COEFF_NUM+PX-CX)%COEFF_NUM) && cycleCX) \|\|`
84			`STOMP \|\| );`
85
86			`always @(posedge clk or posedge reset)`
87			`if (reset)`
88			`multPX <= #FFD {MULT_BITS{1'b0}};`
89			`else if (phase1 && cyclePX)`
90			`multPX <= #FFD {MULT_BITS{1'b0}};`
91			`else if (addPX)`
92			`multPX <= #FFD add;`
93
94			`ENDLOOP PX`
95
96
97			`//sample when valid`
98			`always @(posedge clk or posedge reset)`
99			`if (reset)`
100			`mult_sum <= #FFD {DOUT_BITS{1'b0}};`
101			`else if (phase1)`
102			`begin`
103			`LOOP CX COEFF_NUM`
104			`if (cycleCX)`
105			`mult_sum <= #FFD multCX;`
106			`else`
107			`STOMP NEWLINE`
108			`ENDLOOP CX`
109			`STOMP else`
110			`end`
111
112			`//sync to clock enable`
113			`always @(posedge clk or posedge reset)`
114			`if (reset)`
115			`begin`
116			`data_out <= #FFD {DOUT_BITS{1'b0}};`
117			`valid <= #FFD 1'b0;`
118			`end`
119			`else if (clken)`
120			`begin`
121			`data_out <= #FFD mult_sum;`
122			`valid <= #FFD 1'b1;`
123			`end`
124			`else`
125			`begin`
126			`valid <= #FFD 1'b0;`
127			`end`
128
129
130			`endmodule`
131
132
133
134
135

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[/] [robust_fir/] [trunk/] [src/] [base/] [fir_serial.v] - Blame information for rev 2