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[/] [robust_reg/] [trunk/] [README.txt] - Blame information for rev 12
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------------------------------ Remark ----------------------------------------
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This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
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It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
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We will be very happy to receive any kind of feedback regarding our tools and cores.
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We will also be willing to support any company intending to integrate our cores into their project.
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For any questions / remarks / suggestions / bugs please contact info@provartec.com.
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------------------------------------------------------------------------------
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RobustVerilog generic APB register file
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This register file generator uses an Excel worksheet and produces:
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1. Verilog register file
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2. C header file
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3. HTML documentation
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The Excel worksheet named Database holds the registers and their fields.
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Register and field types:
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RW - Read and Write
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RO - Read only
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WO - Write only
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The Excel worksheet automatically generates the RobustVerilog definition files in the RobustVerilog_regs and RobustVerilog_fields worksheets
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Creating the output files:
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1. Make changes as required in the Excel Database worksheet
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2. Save worksheet RobustVerilog_regs as text to def_regs.txt (space delimiters)
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3. Save worksheet RobustVerilog_fields as text to def_fields.txt (space delimiters)
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4. Run the run.sh script in the run dicertory
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5. Output files will be in run/out directory
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In order to create the design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
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