OpenCores
URL https://opencores.org/ocsvn/robust_reg/robust_reg/trunk

Subversion Repositories robust_reg

[/] [robust_reg/] [trunk/] [src/] [base/] [def_regfile.txt] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 eyalhoc
<##//////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28
//////////////////////////////////////////////////////////////////##>
29
 
30 10 eyalhoc
REQUIRE(1.3)
31
 
32 9 eyalhoc
INCLUDE def_regs.txt
33
INCLUDE def_fields.txt
34
 
35
SWAP FFD 1 ##flip-flop delay
36
 
37
## Types:
38
## RW - read / write (output from block)
39
## RO - read only (input to block)
40
## WO - write only (output to block)
41
## IW - internal write (output to block - logic is added especially)
42
## IR - internal read (no port - logic is added especially)
43
ENUM    TYPE_RW  TYPE_RO  TYPE_WO  TYPE_IW  TYPE_IR
44
 
45
SWAP    TYPE_TYPE_RW  Read and Write
46
SWAP    TYPE_TYPE_RO  Read only
47
SWAP    TYPE_TYPE_WO  Write only
48
 
49
GROUP APB is {
50
 pclken 1 input
51
 psel 1 input
52
 penable 1 input
53
 paddr ADDR_BITS input
54
 pwrite 1 input
55
 pwdata 32 input
56
 prdata 32 output
57
 pslverr 1 output
58
 pready 1 output
59
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.