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[/] [robust_reg/] [trunk/] [src/] [base/] [regfile.v] - Blame information for rev 14

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1 11 eyalhoc
/////////////////////////////////////////////////////////////////////
2 9 eyalhoc
////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
28 11 eyalhoc
/////////////////////////////////////////////////////////////////////
29 9 eyalhoc
 
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OUTFILE REGNAME_regfile.v
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INCLUDE def_regfile.txt
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ITER RX GROUP_REGS.NUM
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module REGNAME_regfile (PORTS);
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   parameter            ADDR_BITS = 16;
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   input                clk;
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   input                reset;
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   port                 GROUP_APB;
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   input                GROUP_REGRX.SON(TYPE == TYPE_RO);
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   output               GROUP_REGRX.SON(TYPE == TYPE_RW);
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   output               wr_GROUP_REGRX.SON(TYPE == TYPE_WO);
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   output               GROUP_REGRX.SON(TYPE == TYPE_IW);
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   wire                 gpwrite;
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   wire                 gpread;
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   reg [31:0]           prdata_pre;
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   reg                  pslverr_pre;
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   reg [31:0]           prdata;
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   reg                  pslverr;
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   reg                  pready;
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   wire
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   STOMP NEWLINE ;;     GONCAT(wr_regGROUP_REGS.SON(TYPE != TYPE_RO).IDX ,);
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   reg [31:0]
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   STOMP NEWLINE ;;     GONCAT(rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX ,);
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   reg                  GROUP_REGRX.SON(TYPE == TYPE_IW);
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   reg                  GROUP_REGRX.SON(TYPE == TYPE_RW);
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   wire                 wr_GROUP_REGRX.SON(TYPE == TYPE_WO);
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   wire                 wr_GROUP_REGRX.SON(TYPE == TYPE_IW);
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   //---------------------- addresses-----------------------------------
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   parameter            GROUP_REGS = 'hGROUP_REGS.ADDR;     //GROUP_REGS.DESC
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   //---------------------- gating -------------------------------------
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   assign               gpwrite     = psel & (~penable) & pwrite;
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   assign               gpread      = psel & (~penable) & (~pwrite);
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   //---------------------- Write Operations ---------------------------
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   assign            wr_regGROUP_REGS.SON(TYPE != TYPE_RO).IDX = gpwrite & (paddr == GROUP_REGS);
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   LOOP RX GROUP_REGS.NUM
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   IFDEF TRUE(GROUP_REGS[RX].TYPE == TYPE_RW)
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   //GROUP_REGS[RX].DESC
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   always @(posedge clk or posedge reset)
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     if (reset)
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           begin
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             GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD GROUP_REGRX.WIDTH'dGROUP_REGRX.DEFAULT;     //GROUP_REGRX.DESC
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           end
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     else if (wr_regRX)
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           begin
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             GROUP_REGRX.SON(TYPE==TYPE_RW) <= #FFD pwdata[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START];
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           end
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   ENDIF TRUE(GROUP_REGS[RX].TYPE == TYPE_RW)
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        assign  wr_GROUP_REGRX.SON(TYPE==TYPE_WO) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0];
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        assign  wr_GROUP_REGRX.SON(TYPE==TYPE_IW) = {GROUP_REGRX.WIDTH{wr_regRX}} & pwdata[EXPR(GROUP_REGRX.WIDTH-1):0];
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    ENDLOOP RX
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        //---------------------- Read Operations ----------------------------
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     always @(*)
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     begin
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           rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX  = {32{1'b0}};
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           rd_regRX[EXPR(GROUP_REGRX.WIDTH+GROUP_REGRX.START-1):GROUP_REGRX.START] = GROUP_REGRX.SON(TYPE != TYPE_WO);     //GROUP_REGRX.DESC
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     end
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   always @(*)
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     begin
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          prdata_pre  = {32{1'b0}};
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          case (paddr)
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           GROUP_REGS : prdata_pre = rd_regGROUP_REGS.SON(TYPE != TYPE_WO).IDX;
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           default : prdata_pre  = {32{1'b0}};
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          endcase
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     end
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 always @(paddr or gpread or gpwrite or psel)
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     begin
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          pslverr_pre = 1'b0;
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          case (paddr)
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            GROUP_REGS.SON(TYPE==TYPE_RW) : pslverr_pre = 1'b0; //read and write
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            GROUP_REGS.SON(TYPE==TYPE_RO) : pslverr_pre = gpwrite; //read only
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            GROUP_REGS.SON(TYPE==TYPE_WO) : pslverr_pre = gpread; //write only
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           default : pslverr_pre = psel;    //decode error
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          endcase
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     end
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        //---------------------- Sample outputs -----------------------------
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   always @(posedge clk or posedge reset)
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     if (reset)
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       prdata <= #FFD {32{1'b0}};
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     else if (gpread & pclken)
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       prdata <= #FFD prdata_pre;
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     else if (pclken)
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       prdata <= #FFD {32{1'b0}};
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   always @(posedge clk or posedge reset)
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     if (reset)
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          begin
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       pslverr <= #FFD 1'b0;
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       pready <= #FFD 1'b0;
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          end
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     else if ((gpread | gpwrite) & pclken)
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          begin
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       pslverr <= #FFD pslverr_pre;
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       pready <= #FFD 1'b1;
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          end
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     else if (pclken)
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          begin
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       pslverr <= #FFD 1'b0;
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       pready <= #FFD 1'b0;
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          end
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endmodule
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