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[/] [rs232_with_buffer_and_wb/] [trunk/] [bench/] [tb_uart_top.vhd] - Blame information for rev 43

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity tb_uart_top is
end tb_uart_top;
 
architecture behaviour of tb_uart_top is
        component uart_top is
        generic(address_width : integer := 3);
        port(   clk, master_rst         : in std_logic;
 
                        RST_I                           : in std_logic;
 
                        ADR_I                           : in std_logic_vector(7 downto 0);
                        DAT_I                           : in std_logic_vector(7 downto 0);
                        WE_I                            : in std_logic;
                        STB_I                           : in std_logic;
                        CYC_I                           : in std_logic;
                        DAT_O                           : out std_logic_vector(7 downto 0);
                        ACK_O                           : out std_logic;
 
                        rx                                      : in std_logic;
                        tx                                      : out std_logic;
 
                        rx_fifo_empty           : out std_logic;
                        rx_fifo_full            : out std_logic;
                        tx_fifo_empty           : out std_logic;
                        tx_fifo_full            : out std_logic;
                        parity_error            : out std_logic;
                        stop_bit_error          : out std_logic;
                        transmitting            : out std_logic);
        end component;
 
        constant clk_period : time := 2 ns;     -- 50MHz
        signal clk, RST_I : std_logic;
        signal txrx : std_logic;
        signal rx_fifo_empty, rx_fifo_full, tx_fifo_empty, tx_fifo_full : std_logic;
 
        signal ADR_I, DAT_I, DAT_O : std_logic_vector(7 downto 0);
        signal WE_I, STB_I, CYC_I, ACK_O : std_logic;
 
        type expected_output_buf_type is array (0 to 500) of std_logic_vector(7 downto 0);
        signal expected_output : expected_output_buf_type;
        signal index_in, index_in1, index_out : integer := 0;
        signal expected : std_logic_vector(7 downto 0);
 
        signal sim_word_width           : std_logic_vector(3 downto 0);
        signal sim_stop_bits            : std_logic_vector(1 downto 0);
        signal sim_idle_line_lvl, sim_use_parity_bit, sim_parity_type : std_logic;
        signal sim_baud_period          : std_logic_vector(15 downto 0);
        signal master_rst : std_logic;
 
begin
 
        uut : uart_top generic map (3) port map (clk, master_rst, RST_I, ADR_I, DAT_I, WE_I, STB_I, CYC_I, DAT_O, ACK_O, txrx, txrx, rx_fifo_empty, rx_fifo_full, tx_fifo_empty, tx_fifo_full);
 
        data_in : process
        begin
                WE_I    <= '0';
                STB_I   <= '0';
                CYC_I   <= '0';
                DAT_I   <= "00000000";
                ADR_I   <= "00000000";
 
                wait until master_rst = '1';
                wait until master_rst = '0';
                --RX_Enable
                wait until clk = '1';
                wait for 0.1 ns;
                WE_I    <= '1';
                STB_I   <= '1';
                CYC_I   <= '1';
                DAT_I   <= "00000001";
                ADR_I   <= "00000001";
 
                wait until ACK_O = '1';
                wait until clk = '0';
 
                --Send 011001100
                wait until clk = '1';
                wait for 0.1 ns;
                DAT_I   <= "01100110";
                ADR_I   <= "00000000";
 
                wait until clk = '0';
                --Send 10011001
                wait until clk = '1';
                wait for 0.1 ns;
                DAT_I   <= "10011001";
 
                wait until clk = '0';
                wait until clk = '1';
                wait for 0.1 ns;
 
                STB_I   <= '0';
                CYC_I   <= '0';
 
 
                --read data
                wait until rx_fifo_empty = '0';
                wait until clk = '0';
                wait until clk = '1';
 
                wait for 0.1 ns;
                WE_I    <= '0';
                STB_I   <= '1';
                CYC_I   <= '1';
                ADR_I   <= "00000000";
                wait until ACK_O = '1';
                wait until clk = '0';
                wait for 0.95 ns;
                wait until clk = '1';
                wait for 0.1 ns;
                STB_I   <= '0';
                CYC_I   <= '0';
                assert expected_output(0) = DAT_O'last_value
                        report "Wrong data "& integer'IMAGE(conv_integer(expected_output(0)))& " /= " & integer'IMAGE(conv_integer(DAT_O'last_value))
                                severity error;
 
 
                --read data                             
                wait until rx_fifo_empty = '0';
                wait until clk = '0';
                wait until clk = '1';
 
                wait for 0.1 ns;
                WE_I    <= '0';
                STB_I   <= '1';
                CYC_I   <= '1';
                ADR_I   <= "00000000";
                wait until ACK_O = '1';
                wait until clk = '0';
                wait until clk = '1';
                wait for 0.1 ns;
                STB_I   <= '0';
                CYC_I   <= '0';
 
                assert expected_output(1) = DAT_O'last_value
                        report "Wrong data "& integer'IMAGE(conv_integer(expected_output(1)))& " /= " & integer'IMAGE(conv_integer(DAT_O'last_value))
                                severity error;
 
 
 
                wait;
        end process;
 
 
 
 
 
        RST_I                           <= '0';
        sim_use_parity_bit      <= '0';
        sim_parity_type         <= '0';
        sim_stop_bits           <= "01";
        sim_word_width          <= "1000";
        sim_idle_line_lvl       <= '1';
        sim_baud_period <= "0000000000010000";
 
        clk_process : process
        begin
                clk <= '0';
                wait for clk_period/2;
                clk <= '1';
                wait for clk_period/2;
        end process;
 
        rst_process : process
        begin
                master_rst <= '0';
                wait for 1 ns;
                master_rst <= '1';
                wait for 5 ns;
                master_rst <= '0';
                wait;
        end process;
 
        expected_output_buffer : process
        begin
                wait until master_rst = '1';
                wait until master_rst = '0';
 
                while true loop
                        wait until CYC_I = '1' and WE_I = '1' and ADR_I = "00000000";
                        wait for 0.1 ns;
                        while CYC_I = '1' and WE_I = '1' and ADR_I = "00000000" loop
                                expected_output(index_in) <= DAT_I;
                                index_in <= index_in + 1;
                                wait for 2 ns;
                        end loop;
                end loop;
        end process;
 
        signal_intregrity_process : process
        begin
                wait until master_rst = '1';
                wait until master_rst = '0';
 
                --check each signal send
                while true loop
 
                        --wait for start bit
                        wait until txrx = not sim_idle_line_lvl;
                        expected <= expected_output(index_out);
                        index_out <= index_out + 1;
 
                        wait for 3 ns;
 
                        --bit 0
                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                        assert txrx = expected(0) report "wrong data bit0" severity error;
 
                        --bit 1
                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                        assert txrx = expected(1) report "wrong data bit1" severity error;
 
                        --bit 2
                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                        assert txrx = expected(2) report "wrong data bit2" severity error;
 
                        --bit 3
                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                        assert txrx = expected(3) report "wrong data bit3" severity error;
 
                        --bit 4
                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                        assert txrx = expected(4) report "wrong data bit4" severity error;
 
                        if sim_word_width > "0101" then
                                --bit 5
                                wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                                assert txrx = expected(5) report "wrong data bit5" severity error;
 
                                if sim_word_width > "0110" then
                                        --bit 6
                                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                                        assert txrx = expected(6) report "wrong data bit6" severity error;
 
                                        if sim_word_width > "0111" then
                                                --bit 7
                                                wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                                                assert txrx = expected(7) report "wrong data bit7" severity error;
                                        end if;
                                end if;
                        end if;
 
                        if sim_use_parity_bit = '1' then
                                --bit party_bit
                                wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                                assert txrx = expected(1) report "wrong parity bit" severity error;
                        end if;
 
                        --stop bit 1
                        wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                        assert txrx = sim_idle_line_lvl report "wrong stop bit1" severity error;
 
                        if sim_stop_bits = "10" then
                                --stop bit 2
                                wait for clk_period * conv_integer(sim_baud_period);    --wait a bit for next bits
                                assert txrx = sim_idle_line_lvl report "wrong stop bit2" severity error;
                        end if;
                end loop;
        end process;
 
end behaviour;

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Subversion Repositories rs232_with_buffer_and_wb

[/] [rs232_with_buffer_and_wb/] [trunk/] [bench/] [tb_uart_top.vhd] - Blame information for rev 43

Line No.	Rev	Author	Line
1	36	TobiasJ	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`entity tb_uart_top is`
7			`end tb_uart_top;`
8
9			`architecture behaviour of tb_uart_top is`
10			`component uart_top is`
11			`generic(address_width : integer := 3);`
12			`port( clk, master_rst : in std_logic;`
13
14			`RST_I : in std_logic;`
15
16			`ADR_I : in std_logic_vector(7 downto 0);`
17			`DAT_I : in std_logic_vector(7 downto 0);`
18			`WE_I : in std_logic;`
19			`STB_I : in std_logic;`
20			`CYC_I : in std_logic;`
21			`DAT_O : out std_logic_vector(7 downto 0);`
22			`ACK_O : out std_logic;`
23
24			`rx : in std_logic;`
25			`tx : out std_logic;`
26
27			`rx_fifo_empty : out std_logic;`
28			`rx_fifo_full : out std_logic;`
29			`tx_fifo_empty : out std_logic;`
30			`tx_fifo_full : out std_logic;`
31			`parity_error : out std_logic;`
32			`stop_bit_error : out std_logic;`
33			`transmitting : out std_logic);`
34			`end component;`
35
36			`constant clk_period : time := 2 ns; -- 50MHz`
37			`signal clk, RST_I : std_logic;`
38			`signal txrx : std_logic;`
39			`signal rx_fifo_empty, rx_fifo_full, tx_fifo_empty, tx_fifo_full : std_logic;`
40
41			`signal ADR_I, DAT_I, DAT_O : std_logic_vector(7 downto 0);`
42			`signal WE_I, STB_I, CYC_I, ACK_O : std_logic;`
43
44			`type expected_output_buf_type is array (0 to 500) of std_logic_vector(7 downto 0);`
45			`signal expected_output : expected_output_buf_type;`
46			`signal index_in, index_in1, index_out : integer := 0;`
47			`signal expected : std_logic_vector(7 downto 0);`
48
49			`signal sim_word_width : std_logic_vector(3 downto 0);`
50			`signal sim_stop_bits : std_logic_vector(1 downto 0);`
51			`signal sim_idle_line_lvl, sim_use_parity_bit, sim_parity_type : std_logic;`
52			`signal sim_baud_period : std_logic_vector(15 downto 0);`
53			`signal master_rst : std_logic;`
54
55			`begin`
56
57			`uut : uart_top generic map (3) port map (clk, master_rst, RST_I, ADR_I, DAT_I, WE_I, STB_I, CYC_I, DAT_O, ACK_O, txrx, txrx, rx_fifo_empty, rx_fifo_full, tx_fifo_empty, tx_fifo_full);`
58
59			`data_in : process`
60			`begin`
61			`WE_I <= '0';`
62			`STB_I <= '0';`
63			`CYC_I <= '0';`
64			`DAT_I <= "00000000";`
65			`ADR_I <= "00000000";`
66
67			`wait until master_rst = '1';`
68			`wait until master_rst = '0';`
69			`--RX_Enable`
70			`wait until clk = '1';`
71			`wait for 0.1 ns;`
72			`WE_I <= '1';`
73			`STB_I <= '1';`
74			`CYC_I <= '1';`
75			`DAT_I <= "00000001";`
76			`ADR_I <= "00000001";`
77
78			`wait until ACK_O = '1';`
79			`wait until clk = '0';`
80
81			`--Send 011001100`
82			`wait until clk = '1';`
83			`wait for 0.1 ns;`
84			`DAT_I <= "01100110";`
85			`ADR_I <= "00000000";`
86
87			`wait until clk = '0';`
88			`--Send 10011001`
89			`wait until clk = '1';`
90			`wait for 0.1 ns;`
91			`DAT_I <= "10011001";`
92
93			`wait until clk = '0';`
94			`wait until clk = '1';`
95			`wait for 0.1 ns;`
96
97			`STB_I <= '0';`
98			`CYC_I <= '0';`
99
100
101			`--read data`
102			`wait until rx_fifo_empty = '0';`
103			`wait until clk = '0';`
104			`wait until clk = '1';`
105
106			`wait for 0.1 ns;`
107			`WE_I <= '0';`
108			`STB_I <= '1';`
109			`CYC_I <= '1';`
110			`ADR_I <= "00000000";`
111			`wait until ACK_O = '1';`
112			`wait until clk = '0';`
113			`wait for 0.95 ns;`
114			`wait until clk = '1';`
115			`wait for 0.1 ns;`
116			`STB_I <= '0';`
117			`CYC_I <= '0';`
118			`assert expected_output(0) = DAT_O'last_value`
119			`report "Wrong data "& integer'IMAGE(conv_integer(expected_output(0)))& " /= " & integer'IMAGE(conv_integer(DAT_O'last_value))`
120			`severity error;`
121
122
123			`--read data`
124			`wait until rx_fifo_empty = '0';`
125			`wait until clk = '0';`
126			`wait until clk = '1';`
127
128			`wait for 0.1 ns;`
129			`WE_I <= '0';`
130			`STB_I <= '1';`
131			`CYC_I <= '1';`
132			`ADR_I <= "00000000";`
133			`wait until ACK_O = '1';`
134			`wait until clk = '0';`
135			`wait until clk = '1';`
136			`wait for 0.1 ns;`
137			`STB_I <= '0';`
138			`CYC_I <= '0';`
139
140			`assert expected_output(1) = DAT_O'last_value`
141			`report "Wrong data "& integer'IMAGE(conv_integer(expected_output(1)))& " /= " & integer'IMAGE(conv_integer(DAT_O'last_value))`
142			`severity error;`
143
144
145
146			`wait;`
147			`end process;`
148
149
150
151
152
153			`RST_I <= '0';`
154			`sim_use_parity_bit <= '0';`
155			`sim_parity_type <= '0';`
156			`sim_stop_bits <= "01";`
157			`sim_word_width <= "1000";`
158			`sim_idle_line_lvl <= '1';`
159			`sim_baud_period <= "0000000000010000";`
160
161			`clk_process : process`
162			`begin`
163			`clk <= '0';`
164			`wait for clk_period/2;`
165			`clk <= '1';`
166			`wait for clk_period/2;`
167			`end process;`
168
169			`rst_process : process`
170			`begin`
171			`master_rst <= '0';`
172			`wait for 1 ns;`
173			`master_rst <= '1';`
174			`wait for 5 ns;`
175			`master_rst <= '0';`
176			`wait;`
177			`end process;`
178
179			`expected_output_buffer : process`
180			`begin`
181			`wait until master_rst = '1';`
182			`wait until master_rst = '0';`
183
184			`while true loop`
185			`wait until CYC_I = '1' and WE_I = '1' and ADR_I = "00000000";`
186			`wait for 0.1 ns;`
187			`while CYC_I = '1' and WE_I = '1' and ADR_I = "00000000" loop`
188			`expected_output(index_in) <= DAT_I;`
189			`index_in <= index_in + 1;`
190			`wait for 2 ns;`
191			`end loop;`
192			`end loop;`
193			`end process;`
194
195			`signal_intregrity_process : process`
196			`begin`
197			`wait until master_rst = '1';`
198			`wait until master_rst = '0';`
199
200			`--check each signal send`
201			`while true loop`
202
203			`--wait for start bit`
204			`wait until txrx = not sim_idle_line_lvl;`
205			`expected <= expected_output(index_out);`
206			`index_out <= index_out + 1;`
207
208			`wait for 3 ns;`
209
210			`--bit 0`
211			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
212			`assert txrx = expected(0) report "wrong data bit0" severity error;`
213
214			`--bit 1`
215			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
216			`assert txrx = expected(1) report "wrong data bit1" severity error;`
217
218			`--bit 2`
219			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
220			`assert txrx = expected(2) report "wrong data bit2" severity error;`
221
222			`--bit 3`
223			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
224			`assert txrx = expected(3) report "wrong data bit3" severity error;`
225
226			`--bit 4`
227			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
228			`assert txrx = expected(4) report "wrong data bit4" severity error;`
229
230			`if sim_word_width > "0101" then`
231			`--bit 5`
232			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
233			`assert txrx = expected(5) report "wrong data bit5" severity error;`
234
235			`if sim_word_width > "0110" then`
236			`--bit 6`
237			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
238			`assert txrx = expected(6) report "wrong data bit6" severity error;`
239
240			`if sim_word_width > "0111" then`
241			`--bit 7`
242			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
243			`assert txrx = expected(7) report "wrong data bit7" severity error;`
244			`end if;`
245			`end if;`
246			`end if;`
247
248			`if sim_use_parity_bit = '1' then`
249			`--bit party_bit`
250			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
251			`assert txrx = expected(1) report "wrong parity bit" severity error;`
252			`end if;`
253
254			`--stop bit 1`
255			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
256			`assert txrx = sim_idle_line_lvl report "wrong stop bit1" severity error;`
257
258			`if sim_stop_bits = "10" then`
259			`--stop bit 2`
260			`wait for clk_period * conv_integer(sim_baud_period); --wait a bit for next bits`
261			`assert txrx = sim_idle_line_lvl report "wrong stop bit2" severity error;`
262			`end if;`
263			`end loop;`
264			`end process;`
265
266			`end behaviour;`