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1 2 soneryesil 
/////////////////////////////////////////////////////////////////////
2 
////                                                             ////
3 
////  Redd-Solomon (5,3) Codec                                   ////
4 
////                                                             ////
5 
////                                                             ////
6 
////  Author: Soner Yesil                                        ////
7 
////          soneryesil@opencores.org                           ////
8 
////                                                             ////
9 
////                                                             ////
10 
////                                                             ////
11 
/////////////////////////////////////////////////////////////////////
12 
////                                                             ////
13 
//// Copyright (C) 2004      Soner Yesil                         ////
14 
////                         soneryesil@opencores.org            ////
15 
////                                                             ////
16 
//// This source file may be used and distributed without        ////
17 
//// restriction provided that this copyright statement is not   ////
18 
//// removed from the file and that any derivative work contains ////
19 
//// the original copyright notice and the associated disclaimer.////
20 
////                                                             ////
21 
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
22 
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
23 
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
24 
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
25 
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
26 
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
27 
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
28 
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
29 
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
30 
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
31 
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
32 
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
33 
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
34 
////                                                             ////
35 
/////////////////////////////////////////////////////////////////////
36 
 
37 
// Note :       The source code for the module "gf256mult" is taken
38 
//              from Rajesh Pathak (rajesh_99@netzero.com) with permission.
39 
//              Please contact him in order to use this module.
40 
 
41 
 
42 
 
43 
/***************        z = b . alpha^51 in GF(256)     *******************/
44 
 
45 
 
46 
module MULT_BY_ALPHA51(b, z);
47 
input [7:0] b;
48 
output [7:0] z;
49 
assign z[0] = b[5]^b[7];
50 
assign z[1] = b[0]^b[6];
51 
assign z[2] = b[1]^b[5];
52 
assign z[3] = b[0]^b[2]^b[5]^b[6]^b[7];
53 
assign z[4] = b[1]^b[3]^b[5]^b[6]^b[7]^b[7];
54 
assign z[5] = b[2]^b[4]^b[6]^b[7];
55 
assign z[6] = b[3]^b[5]^b[7];
56 
assign z[7] = b[4]^b[6];
57 
endmodule
58 
 
59 
/********************   z = a . b in GF(256)    *******************/
60 
 
61 
module gf256mult(a, b, z);
62 
input [7:0] a;
63 
input [7:0] b;
64 
output [7:0] z;
65 
assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7];
66 
assign z[1] = b[0]&a[1]^b[1]&a[0]^b[2]&a[7]^b[3]&a[6]^b[4]&a[5]^b[5]&a[4]^b[6]&a[3]^b[6]&a[7]^b[7]&a[2]^b[7]&a[6]^b[7]&a[7];
67 
assign z[2] = b[0]&a[2]^b[1]&a[1]^b[1]&a[7]^b[2]&a[0]^b[2]&a[6]^b[3]&a[5]^b[3]&a[7]^b[4]&a[4]^b[4]&a[6]^b[5]&a[3]^b[5]&a[5]^b[5]&a[7]^b[6]&a[2]^b[6]&a[4]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[3]^b[7]&a[5]^b[7]&a[6];
68 
assign z[3] = b[0]&a[3]^b[1]&a[2]^b[1]&a[7]^b[2]&a[1]^b[2]&a[6]^b[2]&a[7]^b[3]&a[0]^b[3]&a[5]^b[3]&a[6]^b[4]&a[4]^b[4]&a[5]^b[4]&a[7]^b[5]&a[3]^b[5]&a[4]^b[5]&a[6]^b[5]&a[7]^b[6]&a[2]^b[6]&a[3]^b[6]&a[5]^b[6]&a[6]^b[7]&a[1]^b[7]&a[2]^b[7]&a[4]^b[7]&a[5];
69 
assign z[4] = b[0]&a[4]^b[1]&a[3]^b[1]&a[7]^b[2]&a[2]^b[2]&a[6]^b[2]&a[7]^b[3]&a[1]^b[3]&a[5]^b[3]&a[6]^b[3]&a[7]^b[4]&a[0]^b[4]&a[4]^b[4]&a[5]^b[4]&a[6]^b[5]&a[3]^b[5]&a[4]^b[5]&a[5]^b[6]&a[2]^b[6]&a[3]^b[6]&a[4]^b[7]&a[1]^b[7]&a[2]^b[7]&a[3]^b[7]&a[7];
70 
assign z[5] = b[0]&a[5]^b[1]&a[4]^b[2]&a[3]^b[2]&a[7]^b[3]&a[2]^b[3]&a[6]^b[3]&a[7]^b[4]&a[1]^b[4]&a[5]^b[4]&a[6]^b[4]&a[7]^b[5]&a[0]^b[5]&a[4]^b[5]&a[5]^b[5]&a[6]^b[6]&a[3]^b[6]&a[4]^b[6]&a[5]^b[7]&a[2]^b[7]&a[3]^b[7]&a[4];
71 
assign z[6] = b[0]&a[6]^b[1]&a[5]^b[2]&a[4]^b[3]&a[3]^b[3]&a[7]^b[4]&a[2]^b[4]&a[6]^b[4]&a[7]^b[5]&a[1]^b[5]&a[5]^b[5]&a[6]^b[5]&a[7]^b[6]&a[0]^b[6]&a[4]^b[6]&a[5]^b[6]&a[6]^b[7]&a[3]^b[7]&a[4]^b[7]&a[5];
72 
assign z[7] = b[0]&a[7]^b[1]&a[6]^b[2]&a[5]^b[3]&a[4]^b[4]&a[3]^b[4]&a[7]^b[5]&a[2]^b[5]&a[6]^b[5]&a[7]^b[6]&a[1]^b[6]&a[5]^b[6]&a[6]^b[6]&a[7]^b[7]&a[0]^b[7]&a[4]^b[7]&a[5]^b[7]&a[6];
73 
endmodule
74 
 
75 
 
76 
/******************************************************************/
77 
// LOC is combinationally determined by SYND1_ and SYND2_ signals.
78 
 
79 
module SYN2ERR(SYND1_, SYND2_, LOC);
80 
input [7:0] SYND1_, SYND2_;
81 
output [2:0] LOC;
82 
 
83 
wire [7:0] SYND2_inv;
84 
wire [7:0] mult_out;
85 
 
86 
inv_gf256       inv_(.x(SYND2_), .y(SYND2_inv));
87 
gf256mult       mult_(.a(SYND1_), .b(SYND2_inv), .z(mult_out));
88 
 
89 
assign LOC[2] = ~(mult_out[1] | mult_out[2] );
90 
assign LOC[1] = mult_out[4];
91 
assign LOC[0] = mult_out[2];
92 
 
93 
 
94 
endmodule
95 
 
96 
/********************   y = inv(x) in GF(256)   *********************/
97 
 
98 
module inv_gf256(x, y);
99 
input [7:0] x;
100 
output [7:0] y;
101 
reg [7:0] y;
102 
 
103 
always@(x)
104 
 
105 
case(x)
106 
0: y<= 0;
107 
1:      y<=     1;
108 
2:      y<=     142;
109 
4:      y<=     71;
110 
8:      y<=     173;
111 
16:     y<=     216;
112 
32:     y<=     108;
113 
64:     y<=     54;
114 
128:    y<=     27;
115 
29:     y<=     131;
116 
58:     y<=     207;
117 
116:    y<=     233;
118 
232:    y<=     250;
119 
205:    y<=     125;
120 
135:    y<=     176;
121 
19:     y<=     88;
122 
38:     y<=     44;
123 
76:     y<=     22;
124 
152:    y<=     11;
125 
45:     y<=     139;
126 
90:     y<=     203;
127 
180:    y<=     235;
128 
117:    y<=     251;
129 
234:    y<=     243;
130 
201:    y<=     247;
131 
143:    y<=     245;
132 
3:      y<=     244;
133 
6:      y<=     122;
134 
12:     y<=     61;
135 
24:     y<=     144;
136 
48:     y<=     72;
137 
96:     y<=     36;
138 
192:    y<=     18;
139 
157:    y<=     9;
140 
39:     y<=     138;
141 
78:     y<=     69;
142 
156:    y<=     172;
143 
37:     y<=     86;
144 
74:     y<=     43;
145 
148:    y<=     155;
146 
53:     y<=     195;
147 
106:    y<=     239;
148 
212:    y<=     249;
149 
181:    y<=     242;
150 
119:    y<=     121;
151 
238:    y<=     178;
152 
193:    y<=     89;
153 
159:    y<=     162;
154 
35:     y<=     81;
155 
70:     y<=     166;
156 
140:    y<=     83;
157 
5:      y<=     167;
158 
10:     y<=     221;
159 
20:     y<=     224;
160 
40:     y<=     112;
161 
80:     y<=     56;
162 
160:    y<=     28;
163 
93:     y<=     14;
164 
186:    y<=     7;
165 
105:    y<=     141;
166 
210:    y<=     200;
167 
185:    y<=     100;
168 
111:    y<=     50;
169 
222:    y<=     25;
170 
161:    y<=     130;
171 
95:     y<=     65;
172 
190:    y<=     174;
173 
97:     y<=     87;
174 
194:    y<=     165;
175 
153:    y<=     220;
176 
47:     y<=     110;
177 
94:     y<=     55;
178 
188:    y<=     149;
179 
101:    y<=     196;
180 
202:    y<=     98;
181 
137:    y<=     49;
182 
15:     y<=     150;
183 
30:     y<=     75;
184 
60:     y<=     171;
185 
120:    y<=     219;
186 
240:    y<=     227;
187 
253:    y<=     255;
188 
231:    y<=     241;
189 
211:    y<=     246;
190 
187:    y<=     123;
191 
107:    y<=     179;
192 
214:    y<=     215;
193 
177:    y<=     229;
194 
127:    y<=     252;
195 
254:    y<=     126;
196 
225:    y<=     63;
197 
223:    y<=     145;
198 
163:    y<=     198;
199 
91:     y<=     99;
200 
182:    y<=     191;
201 
113:    y<=     209;
202 
226:    y<=     230;
203 
217:    y<=     115;
204 
175:    y<=     183;
205 
67:     y<=     213;
206 
134:    y<=     228;
207 
17:     y<=     114;
208 
34:     y<=     57;
209 
68:     y<=     146;
210 
136:    y<=     73;
211 
13:     y<=     170;
212 
26:     y<=     85;
213 
52:     y<=     164;
214 
104:    y<=     82;
215 
208:    y<=     41;
216 
189:    y<=     154;
217 
103:    y<=     77;
218 
206:    y<=     168;
219 
129:    y<=     84;
220 
31:     y<=     42;
221 
62:     y<=     21;
222 
124:    y<=     132;
223 
248:    y<=     66;
224 
237:    y<=     33;
225 
199:    y<=     158;
226 
147:    y<=     79;
227 
59:     y<=     169;
228 
118:    y<=     218;
229 
236:    y<=     109;
230 
197:    y<=     184;
231 
151:    y<=     92;
232 
51:     y<=     46;
233 
102:    y<=     23;
234 
204:    y<=     133;
235 
133:    y<=     204;
236 
23:     y<=     102;
237 
46:     y<=     51;
238 
92:     y<=     151;
239 
184:    y<=     197;
240 
109:    y<=     236;
241 
218:    y<=     118;
242 
169:    y<=     59;
243 
79:     y<=     147;
244 
158:    y<=     199;
245 
33:     y<=     237;
246 
66:     y<=     248;
247 
132:    y<=     124;
248 
21:     y<=     62;
249 
42:     y<=     31;
250 
84:     y<=     129;
251 
168:    y<=     206;
252 
77:     y<=     103;
253 
154:    y<=     189;
254 
41:     y<=     208;
255 
82:     y<=     104;
256 
164:    y<=     52;
257 
85:     y<=     26;
258 
170:    y<=     13;
259 
73:     y<=     136;
260 
146:    y<=     68;
261 
57:     y<=     34;
262 
114:    y<=     17;
263 
228:    y<=     134;
264 
213:    y<=     67;
265 
183:    y<=     175;
266 
115:    y<=     217;
267 
230:    y<=     226;
268 
209:    y<=     113;
269 
191:    y<=     182;
270 
99:     y<=     91;
271 
198:    y<=     163;
272 
145:    y<=     223;
273 
63:     y<=     225;
274 
126:    y<=     254;
275 
252:    y<=     127;
276 
229:    y<=     177;
277 
215:    y<=     214;
278 
179:    y<=     107;
279 
123:    y<=     187;
280 
246:    y<=     211;
281 
241:    y<=     231;
282 
255:    y<=     253;
283 
227:    y<=     240;
284 
219:    y<=     120;
285 
171:    y<=     60;
286 
75:     y<=     30;
287 
150:    y<=     15;
288 
49:     y<=     137;
289 
98:     y<=     202;
290 
196:    y<=     101;
291 
149:    y<=     188;
292 
55:     y<=     94;
293 
110:    y<=     47;
294 
220:    y<=     153;
295 
165:    y<=     194;
296 
87:     y<=     97;
297 
174:    y<=     190;
298 
65:     y<=     95;
299 
130:    y<=     161;
300 
25:     y<=     222;
301 
50:     y<=     111;
302 
100:    y<=     185;
303 
200:    y<=     210;
304 
141:    y<=     105;
305 
7:      y<=     186;
306 
14:     y<=     93;
307 
28:     y<=     160;
308 
56:     y<=     80;
309 
112:    y<=     40;
310 
224:    y<=     20;
311 
221:    y<=     10;
312 
167:    y<=     5;
313 
83:     y<=     140;
314 
166:    y<=     70;
315 
81:     y<=     35;
316 
162:    y<=     159;
317 
89:     y<=     193;
318 
178:    y<=     238;
319 
121:    y<=     119;
320 
242:    y<=     181;
321 
249:    y<=     212;
322 
239:    y<=     106;
323 
195:    y<=     53;
324 
155:    y<=     148;
325 
43:     y<=     74;
326 
86:     y<=     37;
327 
172:    y<=     156;
328 
69:     y<=     78;
329 
138:    y<=     39;
330 
9:      y<=     157;
331 
18:     y<=     192;
332 
36:     y<=     96;
333 
72:     y<=     48;
334 
144:    y<=     24;
335 
61:     y<=     12;
336 
122:    y<=     6;
337 
244:    y<=     3;
338 
245:    y<=     143;
339 
247:    y<=     201;
340 
243:    y<=     234;
341 
251:    y<=     117;
342 
235:    y<=     180;
343 
203:    y<=     90;
344 
139:    y<=     45;
345 
11:     y<=     152;
346 
22:     y<=     76;
347 
44:     y<=     38;
348 
88:     y<=     19;
349 
176:    y<=     135;
350 
125:    y<=     205;
351 
250:    y<=     232;
352 
233:    y<=     116;
353 
207:    y<=     58;
354 
131:    y<=     29;
355 
27:     y<=     128;
356 
54:     y<=     64;
357 
108:    y<=     32;
358 
216:    y<=     16;
359 
173:    y<=     8;
360 
71:     y<=     4;
361 
142:    y<=     2;
362 
endcase
363 
 
364 
endmodule
365 
/******************************************************************/
366 
 
367 
module RS_5_3_GF256(
368 
CLK,
369 
RESET,
370 
DATA_VALID_IN,
371 
DATA_IN,
372 
E_D,
373 
DATA_VALID_OUT,
374 
DATA_OUT);
375 
 
376 
input
377 
CLK,
378 
RESET,
379 
DATA_VALID_IN,
380 
E_D;
381 
 
382 
input [7:0] DATA_IN;
383 
output DATA_VALID_OUT;
384 
output [7:0] DATA_OUT;
385 
reg DATA_VALID_OUT;
386 
reg [7:0] DATA_OUT;
387 
reg [3:0] cntr1_;
388 
reg [2:0] cntr2_;
389 
reg cntr2_en;
390 
reg [7:0] SYND1_;
391 
reg [7:0] SYND2_;
392 
reg [7:0] VAL;
393 
reg [2:0] LOC2_;
394 
 
395 
wire [7:0] MULT2_;
396 
wire [7:0] ADD3_;
397 
wire    [2:0] LOC;
398 
 
399 
reg [7:0] FIFO0_;
400 
reg [7:0] FIFO1_;
401 
reg [7:0] FIFO2_;
402 
reg [7:0] FIFO3_;
403 
reg [7:0] FIFO4_;
404 
 
405 
assign ADD3_ = (E_D) ? (SYND1_ ^ MULT2_) : MULT2_;
406 
 
407 
MULT_BY_ALPHA51 m0_(.b(SYND2_), .z(MULT2_));
408 
SYN2ERR s_( .SYND1_(SYND1_), .SYND2_(SYND2_), .LOC(LOC) );
409 
 
410 
///////////////////////////////////////////////////////////////////////
411 
 
412 
always@(posedge CLK)
413 
 
414 
if (cntr2_en)
415 
begin
416 
        VAL<=SYND1_;
417 
        LOC2_<=LOC;
418 
end
419 
 
420 
 
421 
 
422 
 
423 
 
424 
///////////////////////////////////////////////////////////////////////
425 
 
426 
always@(posedge CLK or negedge RESET)
427 
 
428 
if (!RESET)
429 
 
430 
cntr1_<=0;
431 
 
432 
else
433 
case(cntr1_)
434 
 
435 
0: if (!DATA_VALID_IN)
436 
        if (E_D)
437 
                cntr1_<=1;
438 
        else
439 
                cntr1_<=5;
440 
1: if (!DATA_VALID_IN) cntr1_<=2;
441 
2: if (!DATA_VALID_IN) cntr1_<=3;
442 
3: cntr1_<=4;
443 
4: cntr1_<=0;
444 
5: if (!DATA_VALID_IN) cntr1_<=6;
445 
6: if (!DATA_VALID_IN) cntr1_<=7;
446 
7: if (!DATA_VALID_IN) cntr1_<=8;
447 
8: cntr1_<=0;
448 
endcase
449 
 
450 
 
451 
//////////////////////////////////////////////////////////////////////
452 
 
453 
always@(posedge CLK or negedge RESET)
454 
if (!RESET)
455 
 
456 
cntr2_<=0;
457 
 
458 
else if (cntr2_==0)
459 
begin
460 
        if (cntr2_en)
461 
                cntr2_<=cntr2_+1;
462 
end
463 
else if (cntr2_==4)
464 
        cntr2_<=0;
465 
else
466 
        cntr2_<=cntr2_+1;
467 
 
468 
 
469 
 
470 
 
471 
//////////////////////////////////////////////////////////////////////
472 
 
473 
always@(posedge CLK or negedge RESET)
474 
 
475 
if (!RESET)
476 
 
477 
        DATA_VALID_OUT<=1;
478 
 
479 
else if ((cntr1_==0)&&(E_D))
480 
 
481 
        DATA_VALID_OUT<=DATA_VALID_IN;
482 
 
483 
else if ( (cntr1_==1) || (cntr1_==2) )
484 
 
485 
        DATA_VALID_OUT<=DATA_VALID_IN;
486 
 
487 
else if ((cntr1_==3) || (cntr1_==4))
488 
 
489 
        DATA_VALID_OUT<=0;
490 
 
491 
else if ((cntr2_en) || (cntr2_!=0))
492 
 
493 
        DATA_VALID_OUT<=0;
494 
else
495 
        DATA_VALID_OUT<=1;
496 
 
497 
 
498 
//////////////////////////////////////////////////////////////////////
499 
 
500 
 
501 
always@(posedge CLK or negedge RESET)
502 
 
503 
if (!RESET)
504 
 
505 
        DATA_OUT<=0;
506 
 
507 
else if ((cntr1_==0)&&(E_D))
508 
 
509 
        DATA_OUT<=DATA_IN;
510 
 
511 
else if ( (cntr1_==1) || (cntr1_==2) )
512 
 
513 
        DATA_OUT<=DATA_IN;
514 
 
515 
else if ((cntr1_==3) || (cntr1_==4))
516 
 
517 
        DATA_OUT<=ADD3_;
518 
 
519 
else if (cntr2_en)
520 
begin
521 
        if(LOC==0)
522 
                DATA_OUT<=FIFO4_ ^ SYND1_;
523 
        else
524 
                DATA_OUT<=FIFO4_;
525 
 
526 
end
527 
else if (cntr2_==LOC2_)
528 
 
529 
        DATA_OUT<=FIFO4_ ^ VAL;
530 
 
531 
else
532 
 
533 
        DATA_OUT<=FIFO4_;
534 
 
535 
//////////////////////////////////////////////////////////////////////
536 
 
537 
 
538 
always@(posedge CLK or negedge RESET)
539 
 
540 
if (!RESET)
541 
begin
542 
 
543 
        FIFO0_<=0;
544 
        FIFO1_<=0;
545 
        FIFO2_<=0;
546 
        FIFO3_<=0;
547 
        FIFO4_<=0;
548 
 
549 
end
550 
else if (((!DATA_VALID_OUT) && (!E_D)) || (cntr1_>=5) || (cntr1_<=8) || (cntr2_en) || (cntr2_!=0) )
551 
begin
552 
        FIFO4_<=FIFO3_;
553 
        FIFO3_<=FIFO2_;
554 
        FIFO2_<=FIFO1_;
555 
        FIFO1_<=FIFO0_;
556 
        FIFO0_<=DATA_IN;
557 
end
558 
 
559 
//////////////////////////////////////////////////////////////////////
560 
 
561 
always@(posedge CLK or negedge RESET)
562 
 
563 
if (!RESET)
564 
begin
565 
 
566 
        SYND1_<=0;
567 
        SYND2_<=0;
568 
 
569 
end
570 
 
571 
else if ( !DATA_VALID_IN )
572 
begin
573 
        if (cntr1_==0)
574 
        begin
575 
                SYND1_<=DATA_IN;
576 
                SYND2_<=DATA_IN;
577 
        end
578 
        else
579 
        begin
580 
                SYND1_<=SYND1_^ DATA_IN;
581 
                SYND2_<=ADD3_^ DATA_IN;
582 
        end
583 
end
584 
else if ( (cntr1_==3) || (cntr1_==4) )
585 
 
586 
        begin
587 
                SYND1_<=SYND1_^ ADD3_;
588 
                SYND2_<=0;
589 
        end
590 
 
591 
 
592 
//////////////////////////////////////////////////////////////////////
593 
 
594 
always@(posedge CLK or negedge RESET)
595 
 
596 
if (!RESET)
597 
 
598 
        cntr2_en<=0;
599 
 
600 
else if (cntr1_==8)
601 
 
602 
        cntr2_en<=1;
603 
 
604 
else
605 
 
606 
        cntr2_en<=0;
607 
 
608 
 
609 
 
610 
endmodule

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