OpenCores
URL https://opencores.org/ocsvn/rs_5_3_gf256/rs_5_3_gf256/trunk

Subversion Repositories rs_5_3_gf256

[/] [rs_5_3_gf256/] [branches/] [avendor/] [rtl/] [stimulus1.v] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 soneryesil 
 
2 2 soneryesil 
module MULT_BY_ALPHA51(b, z);
3 
input [7:0] b;
4 
output [7:0] z;
5 
assign z[0] = b[5]^b[7];
6 
assign z[1] = b[0]^b[6];
7 
assign z[2] = b[1]^b[5];
8 
assign z[3] = b[0]^b[2]^b[5]^b[6]^b[7];
9 
assign z[4] = b[1]^b[3]^b[5]^b[6]^b[7]^b[7];
10 
assign z[5] = b[2]^b[4]^b[6]^b[7];
11 
assign z[6] = b[3]^b[5]^b[7];
12 
assign z[7] = b[4]^b[6];
13 
endmodule
14 
 
15 
module SYN2ERR(SYND1_, SYND2_, LOC);
16 
 
17 
 
18 
input [7:0] SYND1_, SYND2_;
19 
output [2:0] LOC;
20 
 
21 
 
22 
 
23 
 
24 
wire [7:0] SYND2_inv;
25 
wire [7:0] mult_out;
26 
 
27 
inv_gf256       inv_(.x(SYND2_), .y(SYND2_inv));
28 
gf256mult       mult_(.a(SYND1_), .b(SYND2_inv), .z(mult_out));
29 
 
30 
assign LOC[2] = ~(mult_out[1] | mult_out[2] );
31 
assign LOC[1] = mult_out[4];
32 
assign LOC[0] = mult_out[2];
33 
 
34 
 
35 
endmodule
36 
 
37 
/******************************************************************/
38 
 
39 
module gf256mult(a, b, z);
40 
input [7:0] a;
41 
input [7:0] b;
42 
output [7:0] z;
43 
assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7];
44 
assign z[1] = b[0]&a[1]^b[1]&a[0]^b[2]&a[7]^b[3]&a[6]^b[4]&a[5]^b[5]&a[4]^b[6]&a[3]^b[6]&a[7]^b[7]&a[2]^b[7]&a[6]^b[7]&a[7];
45 
assign z[2] = b[0]&a[2]^b[1]&a[1]^b[1]&a[7]^b[2]&a[0]^b[2]&a[6]^b[3]&a[5]^b[3]&a[7]^b[4]&a[4]^b[4]&a[6]^b[5]&a[3]^b[5]&a[5]^b[5]&a[7]^b[6]&a[2]^b[6]&a[4]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[3]^b[7]&a[5]^b[7]&a[6];
46 
assign z[3] = b[0]&a[3]^b[1]&a[2]^b[1]&a[7]^b[2]&a[1]^b[2]&a[6]^b[2]&a[7]^b[3]&a[0]^b[3]&a[5]^b[3]&a[6]^b[4]&a[4]^b[4]&a[5]^b[4]&a[7]^b[5]&a[3]^b[5]&a[4]^b[5]&a[6]^b[5]&a[7]^b[6]&a[2]^b[6]&a[3]^b[6]&a[5]^b[6]&a[6]^b[7]&a[1]^b[7]&a[2]^b[7]&a[4]^b[7]&a[5];
47 
assign z[4] = b[0]&a[4]^b[1]&a[3]^b[1]&a[7]^b[2]&a[2]^b[2]&a[6]^b[2]&a[7]^b[3]&a[1]^b[3]&a[5]^b[3]&a[6]^b[3]&a[7]^b[4]&a[0]^b[4]&a[4]^b[4]&a[5]^b[4]&a[6]^b[5]&a[3]^b[5]&a[4]^b[5]&a[5]^b[6]&a[2]^b[6]&a[3]^b[6]&a[4]^b[7]&a[1]^b[7]&a[2]^b[7]&a[3]^b[7]&a[7];
48 
assign z[5] = b[0]&a[5]^b[1]&a[4]^b[2]&a[3]^b[2]&a[7]^b[3]&a[2]^b[3]&a[6]^b[3]&a[7]^b[4]&a[1]^b[4]&a[5]^b[4]&a[6]^b[4]&a[7]^b[5]&a[0]^b[5]&a[4]^b[5]&a[5]^b[5]&a[6]^b[6]&a[3]^b[6]&a[4]^b[6]&a[5]^b[7]&a[2]^b[7]&a[3]^b[7]&a[4];
49 
assign z[6] = b[0]&a[6]^b[1]&a[5]^b[2]&a[4]^b[3]&a[3]^b[3]&a[7]^b[4]&a[2]^b[4]&a[6]^b[4]&a[7]^b[5]&a[1]^b[5]&a[5]^b[5]&a[6]^b[5]&a[7]^b[6]&a[0]^b[6]&a[4]^b[6]&a[5]^b[6]&a[6]^b[7]&a[3]^b[7]&a[4]^b[7]&a[5];
50 
assign z[7] = b[0]&a[7]^b[1]&a[6]^b[2]&a[5]^b[3]&a[4]^b[4]&a[3]^b[4]&a[7]^b[5]&a[2]^b[5]&a[6]^b[5]&a[7]^b[6]&a[1]^b[6]&a[5]^b[6]&a[6]^b[6]&a[7]^b[7]&a[0]^b[7]&a[4]^b[7]&a[5]^b[7]&a[6];
51 
endmodule
52 
 
53 
/******************************************************************/
54 
 
55 
module inv_gf256(x, y);
56 
input [7:0] x;
57 
output [7:0] y;
58 
reg [7:0] y;
59 
 
60 
always@(x)
61 
 
62 
case(x)
63 
0: y<= 0;
64 
1:      y<=     1;
65 
2:      y<=     142;
66 
4:      y<=     71;
67 
8:      y<=     173;
68 
16:     y<=     216;
69 
32:     y<=     108;
70 
64:     y<=     54;
71 
128:    y<=     27;
72 
29:     y<=     131;
73 
58:     y<=     207;
74 
116:    y<=     233;
75 
232:    y<=     250;
76 
205:    y<=     125;
77 
135:    y<=     176;
78 
19:     y<=     88;
79 
38:     y<=     44;
80 
76:     y<=     22;
81 
152:    y<=     11;
82 
45:     y<=     139;
83 
90:     y<=     203;
84 
180:    y<=     235;
85 
117:    y<=     251;
86 
234:    y<=     243;
87 
201:    y<=     247;
88 
143:    y<=     245;
89 
3:      y<=     244;
90 
6:      y<=     122;
91 
12:     y<=     61;
92 
24:     y<=     144;
93 
48:     y<=     72;
94 
96:     y<=     36;
95 
192:    y<=     18;
96 
157:    y<=     9;
97 
39:     y<=     138;
98 
78:     y<=     69;
99 
156:    y<=     172;
100 
37:     y<=     86;
101 
74:     y<=     43;
102 
148:    y<=     155;
103 
53:     y<=     195;
104 
106:    y<=     239;
105 
212:    y<=     249;
106 
181:    y<=     242;
107 
119:    y<=     121;
108 
238:    y<=     178;
109 
193:    y<=     89;
110 
159:    y<=     162;
111 
35:     y<=     81;
112 
70:     y<=     166;
113 
140:    y<=     83;
114 
5:      y<=     167;
115 
10:     y<=     221;
116 
20:     y<=     224;
117 
40:     y<=     112;
118 
80:     y<=     56;
119 
160:    y<=     28;
120 
93:     y<=     14;
121 
186:    y<=     7;
122 
105:    y<=     141;
123 
210:    y<=     200;
124 
185:    y<=     100;
125 
111:    y<=     50;
126 
222:    y<=     25;
127 
161:    y<=     130;
128 
95:     y<=     65;
129 
190:    y<=     174;
130 
97:     y<=     87;
131 
194:    y<=     165;
132 
153:    y<=     220;
133 
47:     y<=     110;
134 
94:     y<=     55;
135 
188:    y<=     149;
136 
101:    y<=     196;
137 
202:    y<=     98;
138 
137:    y<=     49;
139 
15:     y<=     150;
140 
30:     y<=     75;
141 
60:     y<=     171;
142 
120:    y<=     219;
143 
240:    y<=     227;
144 
253:    y<=     255;
145 
231:    y<=     241;
146 
211:    y<=     246;
147 
187:    y<=     123;
148 
107:    y<=     179;
149 
214:    y<=     215;
150 
177:    y<=     229;
151 
127:    y<=     252;
152 
254:    y<=     126;
153 
225:    y<=     63;
154 
223:    y<=     145;
155 
163:    y<=     198;
156 
91:     y<=     99;
157 
182:    y<=     191;
158 
113:    y<=     209;
159 
226:    y<=     230;
160 
217:    y<=     115;
161 
175:    y<=     183;
162 
67:     y<=     213;
163 
134:    y<=     228;
164 
17:     y<=     114;
165 
34:     y<=     57;
166 
68:     y<=     146;
167 
136:    y<=     73;
168 
13:     y<=     170;
169 
26:     y<=     85;
170 
52:     y<=     164;
171 
104:    y<=     82;
172 
208:    y<=     41;
173 
189:    y<=     154;
174 
103:    y<=     77;
175 
206:    y<=     168;
176 
129:    y<=     84;
177 
31:     y<=     42;
178 
62:     y<=     21;
179 
124:    y<=     132;
180 
248:    y<=     66;
181 
237:    y<=     33;
182 
199:    y<=     158;
183 
147:    y<=     79;
184 
59:     y<=     169;
185 
118:    y<=     218;
186 
236:    y<=     109;
187 
197:    y<=     184;
188 
151:    y<=     92;
189 
51:     y<=     46;
190 
102:    y<=     23;
191 
204:    y<=     133;
192 
133:    y<=     204;
193 
23:     y<=     102;
194 
46:     y<=     51;
195 
92:     y<=     151;
196 
184:    y<=     197;
197 
109:    y<=     236;
198 
218:    y<=     118;
199 
169:    y<=     59;
200 
79:     y<=     147;
201 
158:    y<=     199;
202 
33:     y<=     237;
203 
66:     y<=     248;
204 
132:    y<=     124;
205 
21:     y<=     62;
206 
42:     y<=     31;
207 
84:     y<=     129;
208 
168:    y<=     206;
209 
77:     y<=     103;
210 
154:    y<=     189;
211 
41:     y<=     208;
212 
82:     y<=     104;
213 
164:    y<=     52;
214 
85:     y<=     26;
215 
170:    y<=     13;
216 
73:     y<=     136;
217 
146:    y<=     68;
218 
57:     y<=     34;
219 
114:    y<=     17;
220 
228:    y<=     134;
221 
213:    y<=     67;
222 
183:    y<=     175;
223 
115:    y<=     217;
224 
230:    y<=     226;
225 
209:    y<=     113;
226 
191:    y<=     182;
227 
99:     y<=     91;
228 
198:    y<=     163;
229 
145:    y<=     223;
230 
63:     y<=     225;
231 
126:    y<=     254;
232 
252:    y<=     127;
233 
229:    y<=     177;
234 
215:    y<=     214;
235 
179:    y<=     107;
236 
123:    y<=     187;
237 
246:    y<=     211;
238 
241:    y<=     231;
239 
255:    y<=     253;
240 
227:    y<=     240;
241 
219:    y<=     120;
242 
171:    y<=     60;
243 
75:     y<=     30;
244 
150:    y<=     15;
245 
49:     y<=     137;
246 
98:     y<=     202;
247 
196:    y<=     101;
248 
149:    y<=     188;
249 
55:     y<=     94;
250 
110:    y<=     47;
251 
220:    y<=     153;
252 
165:    y<=     194;
253 
87:     y<=     97;
254 
174:    y<=     190;
255 
65:     y<=     95;
256 
130:    y<=     161;
257 
25:     y<=     222;
258 
50:     y<=     111;
259 
100:    y<=     185;
260 
200:    y<=     210;
261 
141:    y<=     105;
262 
7:      y<=     186;
263 
14:     y<=     93;
264 
28:     y<=     160;
265 
56:     y<=     80;
266 
112:    y<=     40;
267 
224:    y<=     20;
268 
221:    y<=     10;
269 
167:    y<=     5;
270 
83:     y<=     140;
271 
166:    y<=     70;
272 
81:     y<=     35;
273 
162:    y<=     159;
274 
89:     y<=     193;
275 
178:    y<=     238;
276 
121:    y<=     119;
277 
242:    y<=     181;
278 
249:    y<=     212;
279 
239:    y<=     106;
280 
195:    y<=     53;
281 
155:    y<=     148;
282 
43:     y<=     74;
283 
86:     y<=     37;
284 
172:    y<=     156;
285 
69:     y<=     78;
286 
138:    y<=     39;
287 
9:      y<=     157;
288 
18:     y<=     192;
289 
36:     y<=     96;
290 
72:     y<=     48;
291 
144:    y<=     24;
292 
61:     y<=     12;
293 
122:    y<=     6;
294 
244:    y<=     3;
295 
245:    y<=     143;
296 
247:    y<=     201;
297 
243:    y<=     234;
298 
251:    y<=     117;
299 
235:    y<=     180;
300 
203:    y<=     90;
301 
139:    y<=     45;
302 
11:     y<=     152;
303 
22:     y<=     76;
304 
44:     y<=     38;
305 
88:     y<=     19;
306 
176:    y<=     135;
307 
125:    y<=     205;
308 
250:    y<=     232;
309 
233:    y<=     116;
310 
207:    y<=     58;
311 
131:    y<=     29;
312 
27:     y<=     128;
313 
54:     y<=     64;
314 
108:    y<=     32;
315 
216:    y<=     16;
316 
173:    y<=     8;
317 
71:     y<=     4;
318 
142:    y<=     2;
319 
endcase
320 
 
321 
endmodule
322 
/******************************************************************/
323 
module RS_5_3_GF256(
324 
CLK,
325 
RESET,
326 
DATA_VALID_IN,
327 
DATA_IN,
328 
E_D,
329 
DATA_VALID_OUT,
330 
DATA_OUT);
331 
 
332 
input
333 
CLK,
334 
RESET,
335 
DATA_VALID_IN,
336 
E_D;
337 
 
338 
input [7:0] DATA_IN;
339 
output DATA_VALID_OUT;
340 
output [7:0] DATA_OUT;
341 
reg DATA_VALID_OUT;
342 
reg [7:0] DATA_OUT;
343 
reg [3:0] cntr1_;
344 
reg [2:0] cntr2_;
345 
reg cntr2_en;
346 
reg [7:0] SYND1_;
347 
reg [7:0] SYND2_;
348 
reg [7:0] VAL;
349 
reg [2:0] LOC2_;
350 
 
351 
wire [7:0] MULT2_;
352 
wire [7:0] ADD3_;
353 
wire    [2:0] LOC;
354 
 
355 
reg [7:0] FIFO0_;
356 
reg [7:0] FIFO1_;
357 
reg [7:0] FIFO2_;
358 
reg [7:0] FIFO3_;
359 
reg [7:0] FIFO4_;
360 
 
361 
assign ADD3_ = (E_D) ? (SYND1_ ^ MULT2_) : MULT2_;
362 
 
363 
MULT_BY_ALPHA51 m0_(.b(SYND2_), .z(MULT2_));
364 
SYN2ERR s_( .SYND1_(SYND1_), .SYND2_(SYND2_), .LOC(LOC) );
365 
 
366 
///////////////////////////////////////////////////////////////////////
367 
 
368 
always@(posedge CLK)
369 
 
370 
if (cntr2_en)
371 
begin
372 
        VAL<=SYND1_;
373 
        LOC2_<=LOC;
374 
end
375 
 
376 
 
377 
 
378 
 
379 
 
380 
///////////////////////////////////////////////////////////////////////
381 
 
382 
always@(posedge CLK or negedge RESET)
383 
 
384 
if (!RESET)
385 
 
386 
cntr1_<=0;
387 
 
388 
else
389 
case(cntr1_)
390 
 
391 
0: if (!DATA_VALID_IN)
392 
        if (E_D)
393 
                cntr1_<=1;
394 
        else
395 
                cntr1_<=5;
396 
1: if (!DATA_VALID_IN) cntr1_<=2;
397 
2: if (!DATA_VALID_IN) cntr1_<=3;
398 
3: cntr1_<=4;
399 
4: cntr1_<=0;
400 
5: if (!DATA_VALID_IN) cntr1_<=6;
401 
6: if (!DATA_VALID_IN) cntr1_<=7;
402 
7: if (!DATA_VALID_IN) cntr1_<=8;
403 
8: cntr1_<=0;
404 
endcase
405 
 
406 
 
407 
//////////////////////////////////////////////////////////////////////
408 
 
409 
always@(posedge CLK or negedge RESET)
410 
if (!RESET)
411 
 
412 
cntr2_<=0;
413 
 
414 
else if (cntr2_==0)
415 
begin
416 
        if (cntr2_en)
417 
                cntr2_<=cntr2_+1;
418 
end
419 
else if (cntr2_==4)
420 
        cntr2_<=0;
421 
else
422 
        cntr2_<=cntr2_+1;
423 
 
424 
 
425 
 
426 
 
427 
//////////////////////////////////////////////////////////////////////
428 
 
429 
always@(posedge CLK or negedge RESET)
430 
 
431 
if (!RESET)
432 
 
433 
        DATA_VALID_OUT<=1;
434 
 
435 
else if ((cntr1_==0)&&(E_D))
436 
 
437 
        DATA_VALID_OUT<=DATA_VALID_IN;
438 
 
439 
else if ( (cntr1_==1) || (cntr1_==2) )
440 
 
441 
        DATA_VALID_OUT<=DATA_VALID_IN;
442 
 
443 
else if ((cntr1_==3) || (cntr1_==4))
444 
 
445 
        DATA_VALID_OUT<=0;
446 
 
447 
else if ((cntr2_en) || (cntr2_!=0))
448 
 
449 
        DATA_VALID_OUT<=0;
450 
else
451 
        DATA_VALID_OUT<=1;
452 
 
453 
 
454 
//////////////////////////////////////////////////////////////////////
455 
 
456 
 
457 
always@(posedge CLK or negedge RESET)
458 
 
459 
if (!RESET)
460 
 
461 
        DATA_OUT<=0;
462 
 
463 
else if ((cntr1_==0)&&(E_D))
464 
 
465 
        DATA_OUT<=DATA_IN;
466 
 
467 
else if ( (cntr1_==1) || (cntr1_==2) )
468 
 
469 
        DATA_OUT<=DATA_IN;
470 
 
471 
else if ((cntr1_==3) || (cntr1_==4))
472 
 
473 
        DATA_OUT<=ADD3_;
474 
 
475 
else if (cntr2_en)
476 
begin
477 
        if(LOC==0)
478 
                DATA_OUT<=FIFO4_ ^ SYND1_;
479 
        else
480 
                DATA_OUT<=FIFO4_;
481 
 
482 
end
483 
else if (cntr2_==LOC2_)
484 
 
485 
        DATA_OUT<=FIFO4_ ^ VAL;
486 
 
487 
else
488 
 
489 
        DATA_OUT<=FIFO4_;
490 
 
491 
//////////////////////////////////////////////////////////////////////
492 
 
493 
 
494 
always@(posedge CLK or negedge RESET)
495 
 
496 
if (!RESET)
497 
begin
498 
 
499 
        FIFO0_<=0;
500 
        FIFO1_<=0;
501 
        FIFO2_<=0;
502 
        FIFO3_<=0;
503 
        FIFO4_<=0;
504 
 
505 
end
506 
else if (((!DATA_VALID_OUT) && (!E_D)) || (cntr1_>=5) || (cntr1_<=8) || (cntr2_en) || (cntr2_!=0) )
507 
begin
508 
        FIFO4_<=FIFO3_;
509 
        FIFO3_<=FIFO2_;
510 
        FIFO2_<=FIFO1_;
511 
        FIFO1_<=FIFO0_;
512 
        FIFO0_<=DATA_IN;
513 
end
514 
 
515 
//////////////////////////////////////////////////////////////////////
516 
 
517 
always@(posedge CLK or negedge RESET)
518 
 
519 
if (!RESET)
520 
begin
521 
 
522 
        SYND1_<=0;
523 
        SYND2_<=0;
524 
 
525 
end
526 
 
527 
else if ( !DATA_VALID_IN )
528 
begin
529 
        if (cntr1_==0)
530 
        begin
531 
                SYND1_<=DATA_IN;
532 
                SYND2_<=DATA_IN;
533 
        end
534 
        else
535 
        begin
536 
                SYND1_<=SYND1_^ DATA_IN;
537 
                SYND2_<=ADD3_^ DATA_IN;
538 
        end
539 
end
540 
else if ( (cntr1_==3) || (cntr1_==4) )
541 
 
542 
        begin
543 
                SYND1_<=SYND1_^ ADD3_;
544 
                SYND2_<=0;
545 
        end
546 
 
547 
 
548 
//////////////////////////////////////////////////////////////////////
549 
 
550 
always@(posedge CLK or negedge RESET)
551 
 
552 
if (!RESET)
553 
 
554 
        cntr2_en<=0;
555 
 
556 
else if (cntr1_==8)
557 
 
558 
        cntr2_en<=1;
559 
 
560 
else
561 
 
562 
        cntr2_en<=0;
563 
 
564 
 
565 
 
566 
endmodule
567 
 
568 
 
569 
/******************************************************************/
570 
/*
571 
This stimulus file
572 
- Creates 256^3 message symbols,
573 
- Encodes these message symbols into codewords
574 
- Then decodes them
575 
- And compares the decoded message to the original message.
576 
- I there is a mismatch then the ERR output of the stimulus file is SET for 1 clock cycle.
577 
*/
578 
 
579 
 
580 
 
581 
 
582 
module stimulus(
583 
CLK,
584 
RESET,
585 
DATA_VALID_IN,
586 
DATA_IN,
587 
E_D,
588 
ERR,
589 
DATA_VALID_OUT,
590 
DATA_OUT);
591 
 
592 
 
593 
 
594 
input DATA_VALID_OUT;
595 
input [7:0] DATA_OUT;
596 
output CLK, RESET, E_D, DATA_VALID_IN;
597 
output [7:0] DATA_IN;
598 
output ERR;
599 
 
600 
reg ERR;
601 
reg [7:0] c4, c3, c2, c1, c0;
602 
reg CLK, RESET, E_D, DATA_VALID_IN;
603 
reg [7:0] DATA_IN;
604 
 
605 
integer i, j, k;
606 
 
607 
RS_5_3_GF256    u0_(
608 
.CLK(CLK),
609 
.RESET(RESET),
610 
.DATA_VALID_IN(DATA_VALID_IN),
611 
.DATA_IN(DATA_IN),
612 
.E_D(E_D),
613 
.DATA_OUT(DATA_OUT),
614 
.DATA_VALID_OUT(DATA_VALID_OUT));
615 
 
616 
 
617 
/////////////////////////       CLK SIGNAL      ///////////////////////
618 
 
619 
initial CLK <= 0;
620 
always
621 
begin
622 
        #50
623 
        CLK <= !CLK;
624 
end
625 
 
626 
 
627 
/////////////////////////       RESET SIGNAL    ///////////////////////
628 
 
629 
initial
630 
begin
631 
        RESET <= 0;
632 
        #500
633 
        RESET <= 1;
634 
end
635 
 
636 
 
637 
/////////////////////////       DATA_VALID_IN & DATA_IN & E_D   ///////////////////////
638 
 
639 
initial
640 
begin
641 
DATA_VALID_IN<=1;
642 
E_D<=1;
643 
DATA_IN<=0;
644 
ERR<=0;
645 
#1000
646 
 
647 
for (i = 80; i < 256; i = i+1)
648 
        for (j = 0; j < 256; j = j+1)
649 
                for (k = 0; k < 256; k = k+1)
650 
                begin
651 
                        #100
652 
                        #100
653 
                        #100
654 
                        #100
655 
                        #100
656 
                        #100
657 
                        #100
658 
                        #100
659 
                        #100
660 
                        DATA_VALID_IN<=0;
661 
                        E_D<=1;
662 
                        DATA_IN<=i;
663 
                        #100
664 
                        DATA_IN<=j;
665 
                        #100
666 
                        DATA_IN<=k;
667 
                        #100
668 
                        DATA_IN<=0;
669 
                        DATA_VALID_IN<=1;
670 
                        #100
671 
                        #100
672 
                        #100
673 
                        #100
674 
                        #100
675 
                        #100
676 
                        #100
677 
                        #100
678 
                        #100
679 
                        #100
680 
                        DATA_VALID_IN<=0;
681 
                        E_D<=0;
682 
                        DATA_IN<=c4;
683 
                        #100
684 
                        DATA_IN<=c3;
685 
                        #100
686 
                        DATA_IN<=c2;
687 
                        #100
688 
                        DATA_IN<=c1;
689 
                        #100
690 
                        DATA_IN<=c0;
691 
                        #100
692 
                        DATA_VALID_IN<=1;
693 
 
694 
                        #150
695 
                        if (DATA_OUT!=i)        begin ERR<=1; end
696 
                        #100
697 
                        if (DATA_OUT!=j)        begin ERR<=1; end
698 
                        #100
699 
                        if (DATA_OUT!=k)        begin ERR<=1; end
700 
                        #50
701 
                        ERR<=0;
702 
 
703 
                end
704 
end
705 
 
706 
 
707 
 
708 
 
709 
 
710 
 
711 
 
712 
always@(posedge CLK or negedge RESET)
713 
 
714 
if (!RESET)
715 
begin
716 
c0<=0;
717 
c1<=0;
718 
c2<=0;
719 
c3<=0;
720 
c4<=0;
721 
end
722 
else if (!DATA_VALID_OUT)
723 
begin
724 
c0<=DATA_OUT;
725 
c1<=c0;
726 
c2<=c1;
727 
c3<=c2;
728 
c4<=c3;
729 
end
730 
 
731 
 
732 
 
733 
 
734 
/////////////////////
735 
 
736 
 
737 
 
738 
///////////////////////////////////////////////////////////////// DEC 2
739 
 
740 
 
741 
 
742 
 
743 
 
744 
 
745 
 
746 
always
747 
begin
748 
        #1000000000
749 
        $finish;
750 
end
751 
endmodule
752 
 
753 
 
754 
 
755 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.