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1 2 soneryesil 
module MULT_BY_ALPHA51(b, z);
2 
input [7:0] b;
3 
output [7:0] z;
4 
assign z[0] = b[5]^b[7];
5 
assign z[1] = b[0]^b[6];
6 
assign z[2] = b[1]^b[5];
7 
assign z[3] = b[0]^b[2]^b[5]^b[6]^b[7];
8 
assign z[4] = b[1]^b[3]^b[5]^b[6]^b[7]^b[7];
9 
assign z[5] = b[2]^b[4]^b[6]^b[7];
10 
assign z[6] = b[3]^b[5]^b[7];
11 
assign z[7] = b[4]^b[6];
12 
endmodule
13 
 
14 
module SYN2ERR(SYND1_, SYND2_, LOC);
15 
 
16 
 
17 
input [7:0] SYND1_, SYND2_;
18 
output [2:0] LOC;
19 
 
20 
 
21 
 
22 
 
23 
wire [7:0] SYND2_inv;
24 
wire [7:0] mult_out;
25 
 
26 
inv_gf256       inv_(.x(SYND2_), .y(SYND2_inv));
27 
gf256mult       mult_(.a(SYND1_), .b(SYND2_inv), .z(mult_out));
28 
 
29 
assign LOC[2] = ~(mult_out[1] | mult_out[2] );
30 
assign LOC[1] = mult_out[4];
31 
assign LOC[0] = mult_out[2];
32 
 
33 
 
34 
endmodule
35 
 
36 
/******************************************************************/
37 
 
38 
module gf256mult(a, b, z);
39 
input [7:0] a;
40 
input [7:0] b;
41 
output [7:0] z;
42 
assign z[0] = b[0]&a[0]^b[1]&a[7]^b[2]&a[6]^b[3]&a[5]^b[4]&a[4]^b[5]&a[3]^b[5]&a[7]^b[6]&a[2]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[5]^b[7]&a[6]^b[7]&a[7];
43 
assign z[1] = b[0]&a[1]^b[1]&a[0]^b[2]&a[7]^b[3]&a[6]^b[4]&a[5]^b[5]&a[4]^b[6]&a[3]^b[6]&a[7]^b[7]&a[2]^b[7]&a[6]^b[7]&a[7];
44 
assign z[2] = b[0]&a[2]^b[1]&a[1]^b[1]&a[7]^b[2]&a[0]^b[2]&a[6]^b[3]&a[5]^b[3]&a[7]^b[4]&a[4]^b[4]&a[6]^b[5]&a[3]^b[5]&a[5]^b[5]&a[7]^b[6]&a[2]^b[6]&a[4]^b[6]&a[6]^b[6]&a[7]^b[7]&a[1]^b[7]&a[3]^b[7]&a[5]^b[7]&a[6];
45 
assign z[3] = b[0]&a[3]^b[1]&a[2]^b[1]&a[7]^b[2]&a[1]^b[2]&a[6]^b[2]&a[7]^b[3]&a[0]^b[3]&a[5]^b[3]&a[6]^b[4]&a[4]^b[4]&a[5]^b[4]&a[7]^b[5]&a[3]^b[5]&a[4]^b[5]&a[6]^b[5]&a[7]^b[6]&a[2]^b[6]&a[3]^b[6]&a[5]^b[6]&a[6]^b[7]&a[1]^b[7]&a[2]^b[7]&a[4]^b[7]&a[5];
46 
assign z[4] = b[0]&a[4]^b[1]&a[3]^b[1]&a[7]^b[2]&a[2]^b[2]&a[6]^b[2]&a[7]^b[3]&a[1]^b[3]&a[5]^b[3]&a[6]^b[3]&a[7]^b[4]&a[0]^b[4]&a[4]^b[4]&a[5]^b[4]&a[6]^b[5]&a[3]^b[5]&a[4]^b[5]&a[5]^b[6]&a[2]^b[6]&a[3]^b[6]&a[4]^b[7]&a[1]^b[7]&a[2]^b[7]&a[3]^b[7]&a[7];
47 
assign z[5] = b[0]&a[5]^b[1]&a[4]^b[2]&a[3]^b[2]&a[7]^b[3]&a[2]^b[3]&a[6]^b[3]&a[7]^b[4]&a[1]^b[4]&a[5]^b[4]&a[6]^b[4]&a[7]^b[5]&a[0]^b[5]&a[4]^b[5]&a[5]^b[5]&a[6]^b[6]&a[3]^b[6]&a[4]^b[6]&a[5]^b[7]&a[2]^b[7]&a[3]^b[7]&a[4];
48 
assign z[6] = b[0]&a[6]^b[1]&a[5]^b[2]&a[4]^b[3]&a[3]^b[3]&a[7]^b[4]&a[2]^b[4]&a[6]^b[4]&a[7]^b[5]&a[1]^b[5]&a[5]^b[5]&a[6]^b[5]&a[7]^b[6]&a[0]^b[6]&a[4]^b[6]&a[5]^b[6]&a[6]^b[7]&a[3]^b[7]&a[4]^b[7]&a[5];
49 
assign z[7] = b[0]&a[7]^b[1]&a[6]^b[2]&a[5]^b[3]&a[4]^b[4]&a[3]^b[4]&a[7]^b[5]&a[2]^b[5]&a[6]^b[5]&a[7]^b[6]&a[1]^b[6]&a[5]^b[6]&a[6]^b[6]&a[7]^b[7]&a[0]^b[7]&a[4]^b[7]&a[5]^b[7]&a[6];
50 
endmodule
51 
 
52 
/******************************************************************/
53 
 
54 
module inv_gf256(x, y);
55 
input [7:0] x;
56 
output [7:0] y;
57 
reg [7:0] y;
58 
 
59 
always@(x)
60 
 
61 
case(x)
62 
0: y<= 0;
63 
1:      y<=     1;
64 
2:      y<=     142;
65 
4:      y<=     71;
66 
8:      y<=     173;
67 
16:     y<=     216;
68 
32:     y<=     108;
69 
64:     y<=     54;
70 
128:    y<=     27;
71 
29:     y<=     131;
72 
58:     y<=     207;
73 
116:    y<=     233;
74 
232:    y<=     250;
75 
205:    y<=     125;
76 
135:    y<=     176;
77 
19:     y<=     88;
78 
38:     y<=     44;
79 
76:     y<=     22;
80 
152:    y<=     11;
81 
45:     y<=     139;
82 
90:     y<=     203;
83 
180:    y<=     235;
84 
117:    y<=     251;
85 
234:    y<=     243;
86 
201:    y<=     247;
87 
143:    y<=     245;
88 
3:      y<=     244;
89 
6:      y<=     122;
90 
12:     y<=     61;
91 
24:     y<=     144;
92 
48:     y<=     72;
93 
96:     y<=     36;
94 
192:    y<=     18;
95 
157:    y<=     9;
96 
39:     y<=     138;
97 
78:     y<=     69;
98 
156:    y<=     172;
99 
37:     y<=     86;
100 
74:     y<=     43;
101 
148:    y<=     155;
102 
53:     y<=     195;
103 
106:    y<=     239;
104 
212:    y<=     249;
105 
181:    y<=     242;
106 
119:    y<=     121;
107 
238:    y<=     178;
108 
193:    y<=     89;
109 
159:    y<=     162;
110 
35:     y<=     81;
111 
70:     y<=     166;
112 
140:    y<=     83;
113 
5:      y<=     167;
114 
10:     y<=     221;
115 
20:     y<=     224;
116 
40:     y<=     112;
117 
80:     y<=     56;
118 
160:    y<=     28;
119 
93:     y<=     14;
120 
186:    y<=     7;
121 
105:    y<=     141;
122 
210:    y<=     200;
123 
185:    y<=     100;
124 
111:    y<=     50;
125 
222:    y<=     25;
126 
161:    y<=     130;
127 
95:     y<=     65;
128 
190:    y<=     174;
129 
97:     y<=     87;
130 
194:    y<=     165;
131 
153:    y<=     220;
132 
47:     y<=     110;
133 
94:     y<=     55;
134 
188:    y<=     149;
135 
101:    y<=     196;
136 
202:    y<=     98;
137 
137:    y<=     49;
138 
15:     y<=     150;
139 
30:     y<=     75;
140 
60:     y<=     171;
141 
120:    y<=     219;
142 
240:    y<=     227;
143 
253:    y<=     255;
144 
231:    y<=     241;
145 
211:    y<=     246;
146 
187:    y<=     123;
147 
107:    y<=     179;
148 
214:    y<=     215;
149 
177:    y<=     229;
150 
127:    y<=     252;
151 
254:    y<=     126;
152 
225:    y<=     63;
153 
223:    y<=     145;
154 
163:    y<=     198;
155 
91:     y<=     99;
156 
182:    y<=     191;
157 
113:    y<=     209;
158 
226:    y<=     230;
159 
217:    y<=     115;
160 
175:    y<=     183;
161 
67:     y<=     213;
162 
134:    y<=     228;
163 
17:     y<=     114;
164 
34:     y<=     57;
165 
68:     y<=     146;
166 
136:    y<=     73;
167 
13:     y<=     170;
168 
26:     y<=     85;
169 
52:     y<=     164;
170 
104:    y<=     82;
171 
208:    y<=     41;
172 
189:    y<=     154;
173 
103:    y<=     77;
174 
206:    y<=     168;
175 
129:    y<=     84;
176 
31:     y<=     42;
177 
62:     y<=     21;
178 
124:    y<=     132;
179 
248:    y<=     66;
180 
237:    y<=     33;
181 
199:    y<=     158;
182 
147:    y<=     79;
183 
59:     y<=     169;
184 
118:    y<=     218;
185 
236:    y<=     109;
186 
197:    y<=     184;
187 
151:    y<=     92;
188 
51:     y<=     46;
189 
102:    y<=     23;
190 
204:    y<=     133;
191 
133:    y<=     204;
192 
23:     y<=     102;
193 
46:     y<=     51;
194 
92:     y<=     151;
195 
184:    y<=     197;
196 
109:    y<=     236;
197 
218:    y<=     118;
198 
169:    y<=     59;
199 
79:     y<=     147;
200 
158:    y<=     199;
201 
33:     y<=     237;
202 
66:     y<=     248;
203 
132:    y<=     124;
204 
21:     y<=     62;
205 
42:     y<=     31;
206 
84:     y<=     129;
207 
168:    y<=     206;
208 
77:     y<=     103;
209 
154:    y<=     189;
210 
41:     y<=     208;
211 
82:     y<=     104;
212 
164:    y<=     52;
213 
85:     y<=     26;
214 
170:    y<=     13;
215 
73:     y<=     136;
216 
146:    y<=     68;
217 
57:     y<=     34;
218 
114:    y<=     17;
219 
228:    y<=     134;
220 
213:    y<=     67;
221 
183:    y<=     175;
222 
115:    y<=     217;
223 
230:    y<=     226;
224 
209:    y<=     113;
225 
191:    y<=     182;
226 
99:     y<=     91;
227 
198:    y<=     163;
228 
145:    y<=     223;
229 
63:     y<=     225;
230 
126:    y<=     254;
231 
252:    y<=     127;
232 
229:    y<=     177;
233 
215:    y<=     214;
234 
179:    y<=     107;
235 
123:    y<=     187;
236 
246:    y<=     211;
237 
241:    y<=     231;
238 
255:    y<=     253;
239 
227:    y<=     240;
240 
219:    y<=     120;
241 
171:    y<=     60;
242 
75:     y<=     30;
243 
150:    y<=     15;
244 
49:     y<=     137;
245 
98:     y<=     202;
246 
196:    y<=     101;
247 
149:    y<=     188;
248 
55:     y<=     94;
249 
110:    y<=     47;
250 
220:    y<=     153;
251 
165:    y<=     194;
252 
87:     y<=     97;
253 
174:    y<=     190;
254 
65:     y<=     95;
255 
130:    y<=     161;
256 
25:     y<=     222;
257 
50:     y<=     111;
258 
100:    y<=     185;
259 
200:    y<=     210;
260 
141:    y<=     105;
261 
7:      y<=     186;
262 
14:     y<=     93;
263 
28:     y<=     160;
264 
56:     y<=     80;
265 
112:    y<=     40;
266 
224:    y<=     20;
267 
221:    y<=     10;
268 
167:    y<=     5;
269 
83:     y<=     140;
270 
166:    y<=     70;
271 
81:     y<=     35;
272 
162:    y<=     159;
273 
89:     y<=     193;
274 
178:    y<=     238;
275 
121:    y<=     119;
276 
242:    y<=     181;
277 
249:    y<=     212;
278 
239:    y<=     106;
279 
195:    y<=     53;
280 
155:    y<=     148;
281 
43:     y<=     74;
282 
86:     y<=     37;
283 
172:    y<=     156;
284 
69:     y<=     78;
285 
138:    y<=     39;
286 
9:      y<=     157;
287 
18:     y<=     192;
288 
36:     y<=     96;
289 
72:     y<=     48;
290 
144:    y<=     24;
291 
61:     y<=     12;
292 
122:    y<=     6;
293 
244:    y<=     3;
294 
245:    y<=     143;
295 
247:    y<=     201;
296 
243:    y<=     234;
297 
251:    y<=     117;
298 
235:    y<=     180;
299 
203:    y<=     90;
300 
139:    y<=     45;
301 
11:     y<=     152;
302 
22:     y<=     76;
303 
44:     y<=     38;
304 
88:     y<=     19;
305 
176:    y<=     135;
306 
125:    y<=     205;
307 
250:    y<=     232;
308 
233:    y<=     116;
309 
207:    y<=     58;
310 
131:    y<=     29;
311 
27:     y<=     128;
312 
54:     y<=     64;
313 
108:    y<=     32;
314 
216:    y<=     16;
315 
173:    y<=     8;
316 
71:     y<=     4;
317 
142:    y<=     2;
318 
endcase
319 
 
320 
endmodule
321 
/******************************************************************/
322 
module RS_5_3_GF256(
323 
CLK,
324 
RESET,
325 
DATA_VALID_IN,
326 
DATA_IN,
327 
E_D,
328 
DATA_VALID_OUT,
329 
DATA_OUT);
330 
 
331 
input
332 
CLK,
333 
RESET,
334 
DATA_VALID_IN,
335 
E_D;
336 
 
337 
input [7:0] DATA_IN;
338 
output DATA_VALID_OUT;
339 
output [7:0] DATA_OUT;
340 
reg DATA_VALID_OUT;
341 
reg [7:0] DATA_OUT;
342 
reg [3:0] cntr1_;
343 
reg [2:0] cntr2_;
344 
reg cntr2_en;
345 
reg [7:0] SYND1_;
346 
reg [7:0] SYND2_;
347 
reg [7:0] VAL;
348 
reg [2:0] LOC2_;
349 
 
350 
wire [7:0] MULT2_;
351 
wire [7:0] ADD3_;
352 
wire    [2:0] LOC;
353 
 
354 
reg [7:0] FIFO0_;
355 
reg [7:0] FIFO1_;
356 
reg [7:0] FIFO2_;
357 
reg [7:0] FIFO3_;
358 
reg [7:0] FIFO4_;
359 
 
360 
assign ADD3_ = (E_D) ? (SYND1_ ^ MULT2_) : MULT2_;
361 
 
362 
MULT_BY_ALPHA51 m0_(.b(SYND2_), .z(MULT2_));
363 
SYN2ERR s_( .SYND1_(SYND1_), .SYND2_(SYND2_), .LOC(LOC) );
364 
 
365 
///////////////////////////////////////////////////////////////////////
366 
 
367 
always@(posedge CLK)
368 
 
369 
if (cntr2_en)
370 
begin
371 
        VAL<=SYND1_;
372 
        LOC2_<=LOC;
373 
end
374 
 
375 
 
376 
 
377 
 
378 
 
379 
///////////////////////////////////////////////////////////////////////
380 
 
381 
always@(posedge CLK or negedge RESET)
382 
 
383 
if (!RESET)
384 
 
385 
cntr1_<=0;
386 
 
387 
else
388 
case(cntr1_)
389 
 
390 
0: if (!DATA_VALID_IN)
391 
        if (E_D)
392 
                cntr1_<=1;
393 
        else
394 
                cntr1_<=5;
395 
1: if (!DATA_VALID_IN) cntr1_<=2;
396 
2: if (!DATA_VALID_IN) cntr1_<=3;
397 
3: cntr1_<=4;
398 
4: cntr1_<=0;
399 
5: if (!DATA_VALID_IN) cntr1_<=6;
400 
6: if (!DATA_VALID_IN) cntr1_<=7;
401 
7: if (!DATA_VALID_IN) cntr1_<=8;
402 
8: cntr1_<=0;
403 
endcase
404 
 
405 
 
406 
//////////////////////////////////////////////////////////////////////
407 
 
408 
always@(posedge CLK or negedge RESET)
409 
if (!RESET)
410 
 
411 
cntr2_<=0;
412 
 
413 
else if (cntr2_==0)
414 
begin
415 
        if (cntr2_en)
416 
                cntr2_<=cntr2_+1;
417 
end
418 
else if (cntr2_==4)
419 
        cntr2_<=0;
420 
else
421 
        cntr2_<=cntr2_+1;
422 
 
423 
 
424 
 
425 
 
426 
//////////////////////////////////////////////////////////////////////
427 
 
428 
always@(posedge CLK or negedge RESET)
429 
 
430 
if (!RESET)
431 
 
432 
        DATA_VALID_OUT<=1;
433 
 
434 
else if ((cntr1_==0)&&(E_D))
435 
 
436 
        DATA_VALID_OUT<=DATA_VALID_IN;
437 
 
438 
else if ( (cntr1_==1) || (cntr1_==2) )
439 
 
440 
        DATA_VALID_OUT<=DATA_VALID_IN;
441 
 
442 
else if ((cntr1_==3) || (cntr1_==4))
443 
 
444 
        DATA_VALID_OUT<=0;
445 
 
446 
else if ((cntr2_en) || (cntr2_!=0))
447 
 
448 
        DATA_VALID_OUT<=0;
449 
else
450 
        DATA_VALID_OUT<=1;
451 
 
452 
 
453 
//////////////////////////////////////////////////////////////////////
454 
 
455 
 
456 
always@(posedge CLK or negedge RESET)
457 
 
458 
if (!RESET)
459 
 
460 
        DATA_OUT<=0;
461 
 
462 
else if ((cntr1_==0)&&(E_D))
463 
 
464 
        DATA_OUT<=DATA_IN;
465 
 
466 
else if ( (cntr1_==1) || (cntr1_==2) )
467 
 
468 
        DATA_OUT<=DATA_IN;
469 
 
470 
else if ((cntr1_==3) || (cntr1_==4))
471 
 
472 
        DATA_OUT<=ADD3_;
473 
 
474 
else if (cntr2_en)
475 
begin
476 
        if(LOC==0)
477 
                DATA_OUT<=FIFO4_ ^ SYND1_;
478 
        else
479 
                DATA_OUT<=FIFO4_;
480 
 
481 
end
482 
else if (cntr2_==LOC2_)
483 
 
484 
        DATA_OUT<=FIFO4_ ^ VAL;
485 
 
486 
else
487 
 
488 
        DATA_OUT<=FIFO4_;
489 
 
490 
//////////////////////////////////////////////////////////////////////
491 
 
492 
 
493 
always@(posedge CLK or negedge RESET)
494 
 
495 
if (!RESET)
496 
begin
497 
 
498 
        FIFO0_<=0;
499 
        FIFO1_<=0;
500 
        FIFO2_<=0;
501 
        FIFO3_<=0;
502 
        FIFO4_<=0;
503 
 
504 
end
505 
else if (((!DATA_VALID_OUT) && (!E_D)) || (cntr1_>=5) || (cntr1_<=8) || (cntr2_en) || (cntr2_!=0) )
506 
begin
507 
        FIFO4_<=FIFO3_;
508 
        FIFO3_<=FIFO2_;
509 
        FIFO2_<=FIFO1_;
510 
        FIFO1_<=FIFO0_;
511 
        FIFO0_<=DATA_IN;
512 
end
513 
 
514 
//////////////////////////////////////////////////////////////////////
515 
 
516 
always@(posedge CLK or negedge RESET)
517 
 
518 
if (!RESET)
519 
begin
520 
 
521 
        SYND1_<=0;
522 
        SYND2_<=0;
523 
 
524 
end
525 
 
526 
else if ( !DATA_VALID_IN )
527 
begin
528 
        if (cntr1_==0)
529 
        begin
530 
                SYND1_<=DATA_IN;
531 
                SYND2_<=DATA_IN;
532 
        end
533 
        else
534 
        begin
535 
                SYND1_<=SYND1_^ DATA_IN;
536 
                SYND2_<=ADD3_^ DATA_IN;
537 
        end
538 
end
539 
else if ( (cntr1_==3) || (cntr1_==4) )
540 
 
541 
        begin
542 
                SYND1_<=SYND1_^ ADD3_;
543 
                SYND2_<=0;
544 
        end
545 
 
546 
 
547 
//////////////////////////////////////////////////////////////////////
548 
 
549 
always@(posedge CLK or negedge RESET)
550 
 
551 
if (!RESET)
552 
 
553 
        cntr2_en<=0;
554 
 
555 
else if (cntr1_==8)
556 
 
557 
        cntr2_en<=1;
558 
 
559 
else
560 
 
561 
        cntr2_en<=0;
562 
 
563 
 
564 
 
565 
endmodule
566 
 
567 
 
568 
/******************************************************************/
569 
/*
570 
This stimulus file
571 
- Creates 256^3 message symbols,
572 
- Encodes these message symbols into codewords
573 
- Then decodes them
574 
- And compares the decoded message to the original message.
575 
- I there is a mismatch then the ERR output of the stimulus file is SET for 1 clock cycle.
576 
*/
577 
 
578 
 
579 
 
580 
 
581 
module stimulus(
582 
CLK,
583 
RESET,
584 
DATA_VALID_IN,
585 
DATA_IN,
586 
E_D,
587 
ERR,
588 
DATA_VALID_OUT,
589 
DATA_OUT);
590 
 
591 
 
592 
 
593 
input DATA_VALID_OUT;
594 
input [7:0] DATA_OUT;
595 
output CLK, RESET, E_D, DATA_VALID_IN;
596 
output [7:0] DATA_IN;
597 
output ERR;
598 
 
599 
reg ERR;
600 
reg [7:0] c4, c3, c2, c1, c0;
601 
reg CLK, RESET, E_D, DATA_VALID_IN;
602 
reg [7:0] DATA_IN;
603 
 
604 
integer i, j, k;
605 
 
606 
RS_5_3_GF256    u0_(
607 
.CLK(CLK),
608 
.RESET(RESET),
609 
.DATA_VALID_IN(DATA_VALID_IN),
610 
.DATA_IN(DATA_IN),
611 
.E_D(E_D),
612 
.DATA_OUT(DATA_OUT),
613 
.DATA_VALID_OUT(DATA_VALID_OUT));
614 
 
615 
 
616 
/////////////////////////       CLK SIGNAL      ///////////////////////
617 
 
618 
initial CLK <= 0;
619 
always
620 
begin
621 
        #50
622 
        CLK <= !CLK;
623 
end
624 
 
625 
 
626 
/////////////////////////       RESET SIGNAL    ///////////////////////
627 
 
628 
initial
629 
begin
630 
        RESET <= 0;
631 
        #500
632 
        RESET <= 1;
633 
end
634 
 
635 
 
636 
/////////////////////////       DATA_VALID_IN & DATA_IN & E_D   ///////////////////////
637 
 
638 
initial
639 
begin
640 
DATA_VALID_IN<=1;
641 
E_D<=1;
642 
DATA_IN<=0;
643 
ERR<=0;
644 
#1000
645 
 
646 
for (i = 80; i < 256; i = i+1)
647 
        for (j = 0; j < 256; j = j+1)
648 
                for (k = 0; k < 256; k = k+1)
649 
                begin
650 
                        #100
651 
                        #100
652 
                        #100
653 
                        #100
654 
                        #100
655 
                        #100
656 
                        #100
657 
                        #100
658 
                        #100
659 
                        DATA_VALID_IN<=0;
660 
                        E_D<=1;
661 
                        DATA_IN<=i;
662 
                        #100
663 
                        DATA_IN<=j;
664 
                        #100
665 
                        DATA_IN<=k;
666 
                        #100
667 
                        DATA_IN<=0;
668 
                        DATA_VALID_IN<=1;
669 
                        #100
670 
                        #100
671 
                        #100
672 
                        #100
673 
                        #100
674 
                        #100
675 
                        #100
676 
                        #100
677 
                        #100
678 
                        #100
679 
                        DATA_VALID_IN<=0;
680 
                        E_D<=0;
681 
                        DATA_IN<=c4;
682 
                        #100
683 
                        DATA_IN<=c3;
684 
                        #100
685 
                        DATA_IN<=c2;
686 
                        #100
687 
                        DATA_IN<=c1;
688 
                        #100
689 
                        DATA_IN<=c0;
690 
                        #100
691 
                        DATA_VALID_IN<=1;
692 
 
693 
                        #150
694 
                        if (DATA_OUT!=i)        begin ERR<=1; end
695 
                        #100
696 
                        if (DATA_OUT!=j)        begin ERR<=1; end
697 
                        #100
698 
                        if (DATA_OUT!=k)        begin ERR<=1; end
699 
                        #50
700 
                        ERR<=0;
701 
 
702 
                end
703 
end
704 
 
705 
 
706 
 
707 
 
708 
 
709 
 
710 
 
711 
always@(posedge CLK or negedge RESET)
712 
 
713 
if (!RESET)
714 
begin
715 
c0<=0;
716 
c1<=0;
717 
c2<=0;
718 
c3<=0;
719 
c4<=0;
720 
end
721 
else if (!DATA_VALID_OUT)
722 
begin
723 
c0<=DATA_OUT;
724 
c1<=c0;
725 
c2<=c1;
726 
c3<=c2;
727 
c4<=c3;
728 
end
729 
 
730 
 
731 
 
732 
 
733 
/////////////////////
734 
 
735 
 
736 
 
737 
///////////////////////////////////////////////////////////////// DEC 2
738 
 
739 
 
740 
 
741 
 
742 
 
743 
 
744 
 
745 
always
746 
begin
747 
        #1000000000
748 
        $finish;
749 
end
750 
endmodule
751 
 
752 
 
753 
 
754 
 

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