1 |
2 |
unicore |
---------------------------------------------------------------------
|
2 |
|
|
---- ----
|
3 |
|
|
---- Reed Solomon decoder/encoder IP core ----
|
4 |
|
|
---- ----
|
5 |
|
|
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
|
6 |
|
|
---- Company: Unicore Systems http://unicore.co.ua ----
|
7 |
|
|
---- ----
|
8 |
|
|
---- Downloaded from: http://www.opencores.org ----
|
9 |
|
|
---- ----
|
10 |
|
|
---------------------------------------------------------------------
|
11 |
|
|
---- ----
|
12 |
|
|
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
|
13 |
|
|
---- www.unicore.co.ua ----
|
14 |
|
|
---- o.uzenkov@unicore.co.ua ----
|
15 |
|
|
---- ----
|
16 |
|
|
---- This source file may be used and distributed without ----
|
17 |
|
|
---- restriction provided that this copyright statement is not ----
|
18 |
|
|
---- removed from the file and that any derivative work contains ----
|
19 |
|
|
---- the original copyright notice and the associated disclaimer.----
|
20 |
|
|
---- ----
|
21 |
|
|
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
|
22 |
|
|
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
|
23 |
|
|
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
|
24 |
|
|
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
|
25 |
|
|
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
|
26 |
|
|
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
|
27 |
|
|
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
28 |
|
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
|
29 |
|
|
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
|
30 |
|
|
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
|
31 |
|
|
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
|
32 |
|
|
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
|
33 |
|
|
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
34 |
|
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
|
35 |
|
|
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
|
36 |
|
|
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
|
37 |
|
|
---- ----
|
38 |
|
|
---------------------------------------------------------------------
|
39 |
|
|
|
40 |
|
|
--{{ Section below this comment is automatically maintained
|
41 |
|
|
-- and may be overwritten
|
42 |
|
|
--{entity {RS_BER_MESS} architecture {RS_BER_MESS}}
|
43 |
|
|
|
44 |
|
|
library IEEE;
|
45 |
|
|
use IEEE.STD_LOGIC_1164.all;
|
46 |
|
|
use ieee.std_logic_arith.all;
|
47 |
|
|
use ieee.std_logic_unsigned.all;
|
48 |
|
|
use type1.all;
|
49 |
|
|
|
50 |
|
|
entity RS_BER_MESS is
|
51 |
|
|
--generic( G_range: integer := 4;
|
52 |
|
|
-- A_range: integer := 9);
|
53 |
|
|
port(
|
54 |
|
|
CLK : in STD_LOGIC;
|
55 |
|
|
RST : in STD_LOGIC;
|
56 |
|
|
STR : in STD_LOGIC;
|
57 |
|
|
D_IN : in STD_LOGIC_VECTOR(7 downto 0);
|
58 |
|
|
S_OK : out STD_LOGIC;
|
59 |
|
|
SNB : out STD_LOGIC;
|
60 |
|
|
D_OUT : out kgx8;
|
61 |
|
|
D_OUT1 : out tregA
|
62 |
|
|
);
|
63 |
|
|
end RS_BER_MESS;
|
64 |
|
|
|
65 |
|
|
|
66 |
|
|
architecture RS_BER_MESS of RS_BER_MESS is
|
67 |
|
|
|
68 |
|
|
component VEC_MUL is
|
69 |
|
|
port(
|
70 |
|
|
CLK : in STD_LOGIC;
|
71 |
|
|
RST : in STD_LOGIC;
|
72 |
|
|
m_d : in STD_LOGIC;
|
73 |
|
|
A,B : in kgx8;
|
74 |
|
|
C : out kgx8
|
75 |
|
|
);
|
76 |
|
|
end component;
|
77 |
|
|
|
78 |
|
|
type trom2 is array(0 to 255) of integer; --(2**i v G8 )
|
79 |
|
|
constant tb2si : trom2 :=(
|
80 |
|
|
1, 2, 4, 8, 16, 32, 64, 128,29, 58, 116,232,205,135,19, 38,
|
81 |
|
|
76, 152,45, 90, 180,117,234,201,143,3, 6, 12, 24, 48, 96, 192,
|
82 |
|
|
157,39, 78, 156,37, 74, 148,53, 106,212,181,119,238,193,159,35,
|
83 |
|
|
70, 140,5, 10, 20, 40, 80, 160,93, 186,105,210,185,111,222,161,
|
84 |
|
|
95, 190,97, 194,153,47, 94, 188,101,202,137,15, 30, 60, 120,240,
|
85 |
|
|
253,231,211,187,107,214,177,127,254,225,223,163,91, 182,113,226,
|
86 |
|
|
217,175,67, 134,17, 34, 68, 136,13, 26, 52, 104,208,189,103,206,
|
87 |
|
|
129,31, 62, 124,248,237,199,147,59, 118,236,197,151,51, 102,204,
|
88 |
|
|
133,23, 46, 92, 184,109,218,169,79, 158,33, 66, 132,21, 42, 84,
|
89 |
|
|
168,77, 154,41, 82, 164,85, 170,73, 146,57, 114,228,213,183,115,
|
90 |
|
|
230,209,191,99, 198,145,63, 126,252,229,215,179,123,246,241,255,
|
91 |
|
|
227,219,171,75, 150,49, 98, 196,149,55, 110,220,165,87, 174,65,
|
92 |
|
|
130,25, 50, 100,200,141,7, 14, 28, 56, 112,224,221,167,83, 166,
|
93 |
|
|
81, 162,89, 178,121,242,249,239,195,155,43, 86, 172,69, 138,9,
|
94 |
|
|
18, 36, 72, 144,61, 122,244,245,247,243,251,235,203,139,11, 22,
|
95 |
|
|
44, 88, 176,125,250,233,207,131,27, 54, 108,216,173,71, 142,1
|
96 |
|
|
);
|
97 |
|
|
|
98 |
|
|
constant rmx2 : trom2 :=
|
99 |
|
|
(
|
100 |
|
|
1, 4, 16, 64, 29, 116,205,19 ,76, 45, 180,234,143,6, 24, 96,
|
101 |
|
|
157,78, 37, 148,106,181,238,159,70, 5, 20, 80, 93, 105,185,222,
|
102 |
|
|
95, 97, 153,94, 101,137,30, 120,253,211,107,177,254,223,91, 113,
|
103 |
|
|
217,67, 17, 68, 13, 52, 208,103,129,62, 248,199,59, 236,151,102,
|
104 |
|
|
133,46, 184,218,79, 33, 132,42, 168,154,82, 85, 73, 57, 228,183,
|
105 |
|
|
230,191,198,63, 252,215,123,241,227,171,150,98, 149,110,165,174,
|
106 |
|
|
130,50, 200,7, 28, 112,221,83, 81, 89, 121,249,195,43, 172,138,
|
107 |
|
|
18, 72, 61, 244,247,251,203,11, 44, 176,250,207,27, 108,173,142,
|
108 |
|
|
2, 8, 32, 128,58, 232,135,38, 152,90, 117,201,3, 12, 48, 192,
|
109 |
|
|
39, 156,74, 53, 212,119,193,35, 140,10, 40, 160,186,210,111,161,
|
110 |
|
|
190,194,47, 188,202,15, 60, 240,231,187,214,127,225,163,182,226,
|
111 |
|
|
175,134,34, 136,26, 104,189,206,31, 124,237,147,118,197,51, 204,
|
112 |
|
|
23, 92, 109,169,158,66, 21, 84, 77, 41, 164,170,146,114,213,115,
|
113 |
|
|
209,99, 145,126,229,179,246,255,219,75, 49, 196,55, 220,87, 65,
|
114 |
|
|
25, 100,141,14, 56, 224,167,166,162,178,242,239,155,86, 69, 9,
|
115 |
|
|
36, 144,122,245,243,235,139,22, 88, 125,233,131,54, 216,71, 1
|
116 |
|
|
);
|
117 |
|
|
|
118 |
|
|
|
119 |
|
|
|
120 |
|
|
type treg1 is array(G_range-1 downto 0) of std_logic_vector(7 downto 0);
|
121 |
|
|
signal reg,reg1,reg2,reg3,reg4: kgx8;
|
122 |
|
|
signal rg0,rg1,rg2: kgx8;
|
123 |
|
|
signal s1,s2,s3,md,run,r1,s10 : std_logic;
|
124 |
|
|
signal cnt,cnt1,cnt2,cnt3 : std_logic_vector (7 downto 0) := (others => '0');
|
125 |
|
|
signal del,Q,L,M,subb : std_logic_vector (7 downto 0) := (others => '0');
|
126 |
|
|
|
127 |
|
|
|
128 |
|
|
signal cnt4,sm,cnt5,cnt4i,cnt6 : std_logic_vector (7 downto 0) := (others => '0');
|
129 |
|
|
signal reg6i,reg6,reg5,reg7,reg8: kgx8;
|
130 |
|
|
signal rn0,rn1,rn2,md1,rn00,rn01 : std_logic;
|
131 |
|
|
-- type tregA is array(A_range - 1 downto 0) of std_logic_vector(7 downto 0);
|
132 |
|
|
signal rgA1,rgA2,rgA3,rgAo : tregA;
|
133 |
|
|
signal er0,er1 : std_logic_vector (7 downto 0):= (others => '0');
|
134 |
|
|
signal er10,er11 : std_logic_vector (7 downto 0):= (others => '0');
|
135 |
|
|
signal ercnt : std_logic_vector (7 downto 0):= (others => '0');
|
136 |
|
|
signal r11 : std_logic;
|
137 |
|
|
|
138 |
|
|
|
139 |
|
|
|
140 |
|
|
begin
|
141 |
|
|
process(clk,rst)
|
142 |
|
|
begin
|
143 |
|
|
if rst = '1' then
|
144 |
|
|
s1 <= '0';
|
145 |
|
|
s2 <= '0';
|
146 |
|
|
cnt <= x"00";
|
147 |
|
|
reg <= (others => (others => '0'));
|
148 |
|
|
elsif clk = '1' and clk'event then
|
149 |
|
|
if str = '1' then s1 <= '1';
|
150 |
|
|
elsif (cnt = G_range -1 and s1 = '1') then s1 <= '0';
|
151 |
|
|
end if;
|
152 |
|
|
if str = '1' then cnt <= (others => '0');
|
153 |
|
|
elsif (cnt /= G_range -1 and s1 = '1') then cnt <= cnt + 1;
|
154 |
|
|
end if;
|
155 |
|
|
if s1 = '1' then
|
156 |
|
|
reg (conv_integer(cnt)) <= d_in;
|
157 |
|
|
end if;
|
158 |
|
|
s2 <= s1;
|
159 |
|
|
s3 <= not s1 and s2;
|
160 |
|
|
end if;
|
161 |
|
|
end process;
|
162 |
|
|
|
163 |
|
|
process(clk,rst)
|
164 |
|
|
begin
|
165 |
|
|
if rst = '1' then
|
166 |
|
|
reg1 <= (others => (others => '0'));
|
167 |
|
|
reg2 <= (others => (others => '0'));
|
168 |
|
|
reg3 <= (others => (others => '0'));
|
169 |
|
|
elsif clk = '1' and clk'event then
|
170 |
|
|
-- S
|
171 |
|
|
if s3 = '1' then reg1 <= reg; --reg1(0) <= reg(3);reg1(1) <= reg(2);reg1(2) <= reg(1);reg1(3) <= reg(0);
|
172 |
|
|
end if;
|
173 |
|
|
-- L*
|
174 |
|
|
if cnt3 = x"06" and del /= x"00" then
|
175 |
|
|
for i in 0 to G_range-1 loop reg4(i) <= reg2(i) xor rg0(i); end loop;
|
176 |
|
|
end if;
|
177 |
|
|
-- L
|
178 |
|
|
if s3 = '1' then
|
179 |
|
|
reg2(0) <= x"01";
|
180 |
|
|
for i in 1 to G_range-1 loop reg2(i) <= x"00"; end loop;
|
181 |
|
|
elsif run = '1' and cnt3 = x"08" and del /= x"00" then
|
182 |
|
|
for i in 0 to G_range-1 loop reg2(i) <= reg4(i); end loop;
|
183 |
|
|
end if;
|
184 |
|
|
-- B
|
185 |
|
|
if s3 = '1' then
|
186 |
|
|
reg3(0) <= x"00";reg3(1) <= x"01";
|
187 |
|
|
for i in 2 to G_range-1 loop reg3(i) <= x"00"; end loop;
|
188 |
|
|
elsif cnt3 = x"08" then
|
189 |
|
|
if del /= x"00" and subb(7) = '1' then
|
190 |
|
|
reg3(0) <= x"00";
|
191 |
|
|
for i in 1 to G_range-1 loop reg3(i) <= rg0(i-1); end loop;
|
192 |
|
|
else
|
193 |
|
|
reg3(0) <= x"00";
|
194 |
|
|
for i in 1 to G_range-1 loop reg3(i) <= reg3(i-1); end loop;
|
195 |
|
|
end if;
|
196 |
|
|
end if;
|
197 |
|
|
end if;
|
198 |
|
|
end process;
|
199 |
|
|
process(clk,rst)
|
200 |
|
|
begin
|
201 |
|
|
if rst = '1' then
|
202 |
|
|
cnt3 <= x"00";
|
203 |
|
|
elsif clk = '1' and clk'event then
|
204 |
|
|
if s3 = '1' or cnt3 = x"09" then cnt3 <= x"00";
|
205 |
|
|
else cnt3 <= cnt3 + 1;
|
206 |
|
|
end if;
|
207 |
|
|
if run = '1' then
|
208 |
|
|
if cnt3 = x"01" then rg1 <= reg2;
|
209 |
|
|
|
210 |
|
|
case Q is
|
211 |
|
|
when x"00" => rg2(0) <= reg1(0);rg2(1) <= x"00"; rg2(2) <= x"00"; rg2(3) <= x"00";
|
212 |
|
|
when x"01" => rg2(0) <= reg1(1);rg2(1) <= reg1(0); rg2(2) <= x"00"; rg2(3) <= x"00";
|
213 |
|
|
when x"02" => rg2(0) <= reg1(2);rg2(1) <= reg1(1); rg2(2) <= reg1(0);rg2(3) <= x"00";
|
214 |
|
|
when others => rg2(0) <= reg1(3);rg2(1) <= reg1(2); rg2(2) <= reg1(1);rg2(3) <= reg1(0);
|
215 |
|
|
end case;
|
216 |
|
|
md <= '0';
|
217 |
|
|
elsif cnt3 = x"04" then rg1 <= (others => del); rg2 <= reg3; md <= '0';
|
218 |
|
|
elsif cnt3 = x"05" then rg1 <= (others => del); rg2 <= reg2; md <= '1';
|
219 |
|
|
end if;
|
220 |
|
|
else
|
221 |
|
|
md <= '0';
|
222 |
|
|
if cnt4 = x"01" then
|
223 |
|
|
rg2(0) <= reg5(0); rg2(1) <= reg5(0); rg2(2) <= reg5(1); rg2(3) <= x"00";
|
224 |
|
|
rg1(0) <= reg1(0); rg1(1) <= reg1(1); rg1(2) <= reg1(0); rg1(3) <= x"00";
|
225 |
|
|
elsif cnt4 = x"02" then
|
226 |
|
|
rg2(0) <= reg5(2); rg2(1) <= reg5(1); rg2(2) <= reg5(0); rg2(3) <= x"00";
|
227 |
|
|
rg1(0) <= reg1(0); rg1(1) <= reg1(1); rg1(2) <= reg1(2); rg1(3) <= x"00";
|
228 |
|
|
elsif cnt4 = x"03" then
|
229 |
|
|
rg2(0) <= reg5(2); rg2(1) <= reg5(1); rg2(2) <= reg5(0); rg2(3) <= x"00";
|
230 |
|
|
rg1(0) <= reg1(1); rg1(1) <= reg1(2); rg1(2) <= reg1(3); rg1(3) <= x"00";
|
231 |
|
|
end if;
|
232 |
|
|
end if;
|
233 |
|
|
if cnt3 = x"03" then
|
234 |
|
|
-- del <= rg0(0) xor rg0(1) xor rg0(2) xor rg0(3);
|
235 |
|
|
case L is
|
236 |
|
|
when x"00" => del <= rg0(0);
|
237 |
|
|
when x"01" => del <= rg0(0) xor rg0(1);
|
238 |
|
|
when x"02" => del <= rg0(0) xor rg0(1) xor rg0(2);
|
239 |
|
|
when others => del <= rg0(0) xor rg0(1) xor rg0(2) xor rg0(3);
|
240 |
|
|
end case;
|
241 |
|
|
|
242 |
|
|
end if;
|
243 |
|
|
end if;
|
244 |
|
|
end process;
|
245 |
|
|
|
246 |
|
|
|
247 |
|
|
MULL: VEC_MUL
|
248 |
|
|
port map(
|
249 |
|
|
CLK => clk,
|
250 |
|
|
RST => rst,
|
251 |
|
|
m_d => md,
|
252 |
|
|
A => rg2, B => rg1,
|
253 |
|
|
C => rg0
|
254 |
|
|
);
|
255 |
|
|
process(clk,rst)
|
256 |
|
|
begin
|
257 |
|
|
if rst = '1' then
|
258 |
|
|
run <= '0'; r1 <= '0';
|
259 |
|
|
Q <= x"00";
|
260 |
|
|
M <= x"FF";
|
261 |
|
|
L <= x"00";
|
262 |
|
|
s_ok <= '0';
|
263 |
|
|
--snb <= '0';
|
264 |
|
|
d_out <= (others => (others => '0'));
|
265 |
|
|
elsif clk = '1' and clk'event then
|
266 |
|
|
if s3 = '1' then run <= '1';
|
267 |
|
|
elsif Q = x"04" then run <= '0';
|
268 |
|
|
end if;
|
269 |
|
|
if s3 = '1' then Q <= x"00";
|
270 |
|
|
elsif cnt3 = x"09" and run = '1' then Q <= Q + 1;
|
271 |
|
|
end if;
|
272 |
|
|
if s3 = '1' then M <= x"FF";
|
273 |
|
|
elsif (cnt3 = x"04" and subb(7) = '1' and del /= x"00") then M <= Q - L;
|
274 |
|
|
end if;
|
275 |
|
|
if s3 = '1' then L <= x"00";
|
276 |
|
|
elsif run = '1' and (cnt3 = x"04" and subb(7) = '1' and del /= x"00") then L <= Q - M;
|
277 |
|
|
end if;
|
278 |
|
|
if cnt3 = x"02" then subb <= L - Q + M; end if;
|
279 |
|
|
r1 <= run;
|
280 |
|
|
if r1 = '1' and run = '0' then d_out <= reg2; end if;
|
281 |
|
|
-- snb <= not run and r1;
|
282 |
|
|
if s3 = '1' then s_ok <= '0';
|
283 |
|
|
-- elsif r1 = '1' and run = '0' then s_ok <= s10;
|
284 |
|
|
elsif rn01 = '1' and rn00 = '0' and (ercnt = L) then s_ok <= s10;
|
285 |
|
|
end if;
|
286 |
|
|
end if;
|
287 |
|
|
end process;
|
288 |
|
|
s10 <= '1' when reg2(3) = x"00" and
|
289 |
|
|
((reg2(2) /= x"00" and L = x"02") or
|
290 |
|
|
(reg2(2) = x"00" and reg2(1) /= x"00" and L = x"01")) else '0';
|
291 |
|
|
|
292 |
|
|
--- àäðåñà è ïîëèíîì îøèáîê
|
293 |
|
|
process(clk,rst)
|
294 |
|
|
begin
|
295 |
|
|
if rst = '1' then
|
296 |
|
|
reg5 <= (others => (others => '0'));
|
297 |
|
|
reg6 <= (others => (others => '0'));
|
298 |
|
|
reg8 <= (others => (others => '0'));
|
299 |
|
|
cnt4 <= x"00";
|
300 |
|
|
cnt4i <= x"00";
|
301 |
|
|
rn0 <= '0';
|
302 |
|
|
rn00 <= '0';
|
303 |
|
|
md1 <= '0';
|
304 |
|
|
r11 <= '0';
|
305 |
|
|
elsif clk = '1' and clk'event then
|
306 |
|
|
|
307 |
|
|
--rn00 <= rn0;
|
308 |
|
|
rn00 <= r11;
|
309 |
|
|
if r1 = '1' and run = '0' then
|
310 |
|
|
reg5 <= reg2;
|
311 |
|
|
md1 <= '0';
|
312 |
|
|
elsif rn2 = '1' and cnt6 = x"01" then reg5 <= reg8;
|
313 |
|
|
elsif rn2 = '1' and cnt6 = x"05" then reg5(0) <= er10; reg5(1) <= er11; md1 <= '1';
|
314 |
|
|
end if;
|
315 |
|
|
r11 <= rn0;
|
316 |
|
|
if r1 = '1' and run = '0' then cnt4 <= x"00";
|
317 |
|
|
elsif cnt4 /= x"FF" then cnt4 <= cnt4 + 1;
|
318 |
|
|
end if;
|
319 |
|
|
if r1 = '1' and run = '0' then rn0 <= '1';
|
320 |
|
|
elsif cnt4 = x"FF" then rn0 <= '0'; --elsif cnt4i = x"FF" then rn0 <= '0';
|
321 |
|
|
end if;
|
322 |
|
|
if cnt4 = x"03" then
|
323 |
|
|
reg8(0) <= rg0(0);
|
324 |
|
|
reg8(1) <= rg0(1) xor rg0(2);
|
325 |
|
|
elsif cnt4 = x"04" then
|
326 |
|
|
reg8(2) <= rg0(0) xor rg0(1) xor rg0(2);
|
327 |
|
|
elsif cnt4 = x"05" then
|
328 |
|
|
reg8(3) <= rg0(2) xor rg0(1) xor rg0(0);
|
329 |
|
|
end if;
|
330 |
|
|
cnt4i <= cnt4;
|
331 |
|
|
if rn0 = '1' then
|
332 |
|
|
reg6(0) <= x"01";
|
333 |
|
|
reg6(1) <= conv_std_logic_vector (tb2si(conv_integer(cnt4)),8);
|
334 |
|
|
reg6(2) <= conv_std_logic_vector (rmx2(conv_integer(cnt4)),8);
|
335 |
|
|
reg6(3) <= x"00";
|
336 |
|
|
elsif rn2 = '1' and cnt6 = x"01" then
|
337 |
|
|
reg6(0) <= x"01";
|
338 |
|
|
reg6(1) <= rgA1(conv_integer(er0));
|
339 |
|
|
reg6(2) <= rgA2(conv_integer(er0));
|
340 |
|
|
reg6(3) <= rgA3(conv_integer(er0));
|
341 |
|
|
elsif rn2 = '1' and cnt6 = x"02" then
|
342 |
|
|
reg6(0) <= x"01";
|
343 |
|
|
reg6(1) <= rgA1(conv_integer(er1));
|
344 |
|
|
reg6(2) <= rgA2(conv_integer(er1));
|
345 |
|
|
reg6(3) <= rgA3(conv_integer(er1));
|
346 |
|
|
elsif rn2 = '1' and cnt6 = x"05" then
|
347 |
|
|
reg6(0) <= reg2(1); reg6(1) <= reg2(1);
|
348 |
|
|
end if;
|
349 |
|
|
|
350 |
|
|
end if;
|
351 |
|
|
end process;
|
352 |
|
|
|
353 |
|
|
MULL1: VEC_MUL
|
354 |
|
|
port map(
|
355 |
|
|
CLK => clk,
|
356 |
|
|
RST => rst,
|
357 |
|
|
m_d => md1,
|
358 |
|
|
A => reg5, B => reg6,
|
359 |
|
|
C => reg7
|
360 |
|
|
);
|
361 |
|
|
|
362 |
|
|
sm <= reg7(2) xor reg7(1) xor reg7(0);
|
363 |
|
|
process(clk,rst)
|
364 |
|
|
begin
|
365 |
|
|
if rst = '1' then
|
366 |
|
|
rgA3 <= (others => (others => '0'));
|
367 |
|
|
rgA2 <= (others => (others => '0'));
|
368 |
|
|
rgA1 <= (others => (others => '0'));
|
369 |
|
|
cnt5 <= x"FF";
|
370 |
|
|
er0 <= (others => '0');
|
371 |
|
|
er1 <= (others => '0');
|
372 |
|
|
ercnt <= (others => '0');
|
373 |
|
|
rn01 <= '0';
|
374 |
|
|
elsif clk = '1' and clk'event then
|
375 |
|
|
rn01 <= rn00;
|
376 |
|
|
cnt5 <= 255 - cnt4i;
|
377 |
|
|
reg6i <= reg6;
|
378 |
|
|
if cnt5 < A_range then
|
379 |
|
|
if sm = x"00" and rn00 = '1' then
|
380 |
|
|
rgA1(conv_integer(cnt5)) <= reg6i(1);
|
381 |
|
|
rgA2(conv_integer(cnt5)) <= reg6i(2);
|
382 |
|
|
rgA3(conv_integer(cnt5)) <= reg6i(3);
|
383 |
|
|
end if;
|
384 |
|
|
end if;
|
385 |
|
|
|
386 |
|
|
if r1 = '1' and run = '0' then ercnt <= (others => '0');
|
387 |
|
|
elsif sm = x"00" and rn00 = '1' and cnt5 < A_range then
|
388 |
|
|
ercnt <= ercnt + 1;
|
389 |
|
|
end if;
|
390 |
|
|
|
391 |
|
|
if cnt5 < A_range then
|
392 |
|
|
if sm = x"00" and rn00 = '1' then
|
393 |
|
|
if ercnt = x"00" then
|
394 |
|
|
er0 <= cnt5; er1 <= cnt5;
|
395 |
|
|
elsif ercnt = x"01" then
|
396 |
|
|
er0 <= cnt5;
|
397 |
|
|
end if;
|
398 |
|
|
end if;
|
399 |
|
|
end if;
|
400 |
|
|
end if;
|
401 |
|
|
end process;
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
----
|
405 |
|
|
process(clk,rst)
|
406 |
|
|
begin
|
407 |
|
|
if rst = '1' then
|
408 |
|
|
cnt6 <= x"00";
|
409 |
|
|
rn1 <= '0'; rn2 <= '0';
|
410 |
|
|
rgAo <= (others => (others => '0'));
|
411 |
|
|
snb <= '0';
|
412 |
|
|
rn2 <= '0';
|
413 |
|
|
elsif clk = '1' and clk'event then
|
414 |
|
|
rn1 <= rn0;
|
415 |
|
|
if rn1 = '1' and rn0 = '0' then cnt6 <= x"00";
|
416 |
|
|
elsif cnt6 /= x"10" then cnt6 <= cnt6 + 1;
|
417 |
|
|
end if;
|
418 |
|
|
if rn1 = '1' and rn0 = '0' then rn2 <= '1';
|
419 |
|
|
elsif cnt6 = x"10" then rn2 <= '0';
|
420 |
|
|
end if;
|
421 |
|
|
|
422 |
|
|
if cnt6 = x"09" then d_out1 <= rgAo; end if;
|
423 |
|
|
|
424 |
|
|
if cnt6 = x"0A" then snb <= rn2; else snb <= '0'; end if;
|
425 |
|
|
if cnt6 = x"03" then er10 <= sm; end if;
|
426 |
|
|
if cnt6 = x"04" then er11 <= sm; end if;
|
427 |
|
|
if str = '1' then rgAo <= (others => (others => '0'));
|
428 |
|
|
elsif cnt6 = x"07" then
|
429 |
|
|
rgAo(conv_integer(er0)) <= reg7(0);
|
430 |
|
|
rgAo(conv_integer(er1)) <= reg7(1);
|
431 |
|
|
end if;
|
432 |
|
|
end if;
|
433 |
|
|
end process;
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
|
437 |
|
|
end RS_BER_MESS;
|
438 |
|
|
|
439 |
|
|
|