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[/] [rs_dec_enc/] [trunk/] [rtl/] [RS_DEC_SINDDROM.vhd] - Blame information for rev 2

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1 2 unicore 
---------------------------------------------------------------------
2 
----                                                             ----
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----  Reed Solomon decoder/encoder IP core                       ----
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----                                                             ----
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----  Authors: Anatoliy Sergienko, Volodya Lepeha                ----
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----  Company: Unicore Systems http://unicore.co.ua              ----
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----                                                             ----
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----  Downloaded from: http://www.opencores.org                  ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD                 ----
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---- www.unicore.co.ua                                           ----
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---- o.uzenkov@unicore.co.ua                                     ----
15 
----                                                             ----
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---- This source file may be used and distributed without        ----
17 
---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
19 
---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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---- THIS SOFTWARE IS PROVIDED "AS IS"                           ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT              ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT         ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION)                 ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,              ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT              ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING                 ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,                 ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.          ----
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----                                                             ----
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---------------------------------------------------------------------
39 
 
40 
 
41 
library IEEE;
42 
use IEEE.STD_LOGIC_1164.all;
43 
use ieee.std_logic_arith.all;
44 
use ieee.std_logic_unsigned.all;
45 
use type1.all;
46 
 
47 
entity RS_DEC_SINDDROM is
48 
        --generic( G_range:  integer := 4;
49 
--      A_range:  integer := 9);
50 
         port(
51 
                 CLK : in STD_LOGIC;
52 
                 RST : in STD_LOGIC;
53 
                 STR : in STD_LOGIC;
54 
                 D_IN : in STD_LOGIC_VECTOR(7 downto 0);
55 
                 RD : in STD_LOGIC;
56 
                 D_OUT : out STD_LOGIC_VECTOR(7 downto 0);
57 
                 S_er : out STD_LOGIC;
58 
                 SNB : out STD_LOGIC;
59 
                 D_OUT1 : out tregA
60 
             );
61 
end RS_DEC_SINDDROM;
62 
 
63 
--}} End of automatically maintained section
64 
 
65 
architecture RS_DEC_SINDDROM of RS_DEC_SINDDROM is
66 
--
67 
--type trom2 is array(0 to 255) of integer;  --(2**i v G8 )
68 
type trom2 is array(0 to 1020) of integer;  --(2**i v G8 )
69 
constant tb2si : trom2 :=(
70 
1,  2,  4,  8,  16, 32, 64, 128,29, 58, 116,232,205,135,19, 38,
71 
76, 152,45, 90, 180,117,234,201,143,3,  6,  12, 24, 48, 96, 192,
72 
157,39, 78, 156,37, 74, 148,53, 106,212,181,119,238,193,159,35,
73 
70, 140,5,  10, 20, 40, 80, 160,93, 186,105,210,185,111,222,161,
74 
95, 190,97, 194,153,47, 94, 188,101,202,137,15, 30, 60, 120,240,
75 
253,231,211,187,107,214,177,127,254,225,223,163,91, 182,113,226,
76 
217,175,67, 134,17, 34, 68, 136,13, 26, 52, 104,208,189,103,206,
77 
129,31, 62, 124,248,237,199,147,59, 118,236,197,151,51, 102,204,
78 
133,23, 46, 92, 184,109,218,169,79, 158,33, 66, 132,21, 42, 84,
79 
168,77, 154,41, 82, 164,85, 170,73, 146,57, 114,228,213,183,115,
80 
230,209,191,99, 198,145,63, 126,252,229,215,179,123,246,241,255,
81 
227,219,171,75, 150,49, 98, 196,149,55, 110,220,165,87, 174,65,
82 
130,25, 50, 100,200,141,7,  14, 28, 56, 112,224,221,167,83, 166,
83 
81, 162,89, 178,121,242,249,239,195,155,43, 86, 172,69, 138,9,
84 
18, 36, 72, 144,61, 122,244,245,247,243,251,235,203,139,11, 22,
85 
44, 88, 176,125,250,233,207,131,27, 54, 108,216,173,71, 142,1,
86 
 
87 
    2,  4,  8,  16, 32, 64, 128,29, 58, 116,232,205,135,19, 38,
88 
76, 152,45, 90, 180,117,234,201,143,3,  6,  12, 24, 48, 96, 192,
89 
157,39, 78, 156,37, 74, 148,53, 106,212,181,119,238,193,159,35,
90 
70, 140,5,  10, 20, 40, 80, 160,93, 186,105,210,185,111,222,161,
91 
95, 190,97, 194,153,47, 94, 188,101,202,137,15, 30, 60, 120,240,
92 
253,231,211,187,107,214,177,127,254,225,223,163,91, 182,113,226,
93 
217,175,67, 134,17, 34, 68, 136,13, 26, 52, 104,208,189,103,206,
94 
129,31, 62, 124,248,237,199,147,59, 118,236,197,151,51, 102,204,
95 
133,23, 46, 92, 184,109,218,169,79, 158,33, 66, 132,21, 42, 84,
96 
168,77, 154,41, 82, 164,85, 170,73, 146,57, 114,228,213,183,115,
97 
230,209,191,99, 198,145,63, 126,252,229,215,179,123,246,241,255,
98 
227,219,171,75, 150,49, 98, 196,149,55, 110,220,165,87, 174,65,
99 
130,25, 50, 100,200,141,7,  14, 28, 56, 112,224,221,167,83, 166,
100 
81, 162,89, 178,121,242,249,239,195,155,43, 86, 172,69, 138,9,
101 
18, 36, 72, 144,61, 122,244,245,247,243,251,235,203,139,11, 22,
102 
44, 88, 176,125,250,233,207,131,27, 54, 108,216,173,71, 142,1,
103 
 
104 
    2,  4,  8,  16, 32, 64, 128,29, 58, 116,232,205,135,19, 38,
105 
76, 152,45, 90, 180,117,234,201,143,3,  6,  12, 24, 48, 96, 192,
106 
157,39, 78, 156,37, 74, 148,53, 106,212,181,119,238,193,159,35,
107 
70, 140,5,  10, 20, 40, 80, 160,93, 186,105,210,185,111,222,161,
108 
95, 190,97, 194,153,47, 94, 188,101,202,137,15, 30, 60, 120,240,
109 
253,231,211,187,107,214,177,127,254,225,223,163,91, 182,113,226,
110 
217,175,67, 134,17, 34, 68, 136,13, 26, 52, 104,208,189,103,206,
111 
129,31, 62, 124,248,237,199,147,59, 118,236,197,151,51, 102,204,
112 
133,23, 46, 92, 184,109,218,169,79, 158,33, 66, 132,21, 42, 84,
113 
168,77, 154,41, 82, 164,85, 170,73, 146,57, 114,228,213,183,115,
114 
230,209,191,99, 198,145,63, 126,252,229,215,179,123,246,241,255,
115 
227,219,171,75, 150,49, 98, 196,149,55, 110,220,165,87, 174,65,
116 
130,25, 50, 100,200,141,7,  14, 28, 56, 112,224,221,167,83, 166,
117 
81, 162,89, 178,121,242,249,239,195,155,43, 86, 172,69, 138,9,
118 
18, 36, 72, 144,61, 122,244,245,247,243,251,235,203,139,11, 22,
119 
44, 88, 176,125,250,233,207,131,27, 54, 108,216,173,71, 142,1,
120 
 
121 
    2,  4,  8,  16, 32, 64, 128,29, 58, 116,232,205,135,19, 38,
122 
76, 152,45, 90, 180,117,234,201,143,3,  6,  12, 24, 48, 96, 192,
123 
157,39, 78, 156,37, 74, 148,53, 106,212,181,119,238,193,159,35,
124 
70, 140,5,  10, 20, 40, 80, 160,93, 186,105,210,185,111,222,161,
125 
95, 190,97, 194,153,47, 94, 188,101,202,137,15, 30, 60, 120,240,
126 
253,231,211,187,107,214,177,127,254,225,223,163,91, 182,113,226,
127 
217,175,67, 134,17, 34, 68, 136,13, 26, 52, 104,208,189,103,206,
128 
129,31, 62, 124,248,237,199,147,59, 118,236,197,151,51, 102,204,
129 
133,23, 46, 92, 184,109,218,169,79, 158,33, 66, 132,21, 42, 84,
130 
168,77, 154,41, 82, 164,85, 170,73, 146,57, 114,228,213,183,115,
131 
230,209,191,99, 198,145,63, 126,252,229,215,179,123,246,241,255,
132 
227,219,171,75, 150,49, 98, 196,149,55, 110,220,165,87, 174,65,
133 
130,25, 50, 100,200,141,7,  14, 28, 56, 112,224,221,167,83, 166,
134 
81, 162,89, 178,121,242,249,239,195,155,43, 86, 172,69, 138,9,
135 
18, 36, 72, 144,61, 122,244,245,247,243,251,235,203,139,11, 22,
136 
44, 88, 176,125,250,233,207,131,27, 54, 108,216,173,71, 142,1
137 
 
138 
);
139 
 
140 
component mul_g8 is
141 
         port(
142 
                 clk : in STD_LOGIC;
143 
                 rst : in STD_LOGIC;
144 
                 m_d : in STD_LOGIC;
145 
                 a : in STD_LOGIC_VECTOR(7 downto 0);
146 
                 b : in STD_LOGIC_VECTOR(7 downto 0);
147 
                 res : out STD_LOGIC_VECTOR(7 downto 0)
148 
             );
149 
end component;
150 
 
151 
 
152 
type treg is array(A_range - 1 downto 0) of std_logic_vector(7 downto 0);
153 
type treg1 is array(G_range + 1  downto 0) of std_logic_vector(7 downto 0);
154 
signal reg2 : tregA;
155 
signal reg,reg1 : treg1;
156 
 
157 
signal cnt,cnt1,cnt2,rg0 : std_logic_vector (9 downto 0) := (others => '0');
158 
signal data,dm : std_logic_vector (7 downto 0);
159 
signal run, st1, run1,s0,s1,s2,r1 : std_logic;
160 
signal m2i : std_logic_vector (7 downto 0);
161 
signal ds : std_logic_vector (7 downto 0);
162 
signal  rgA :  tregA;
163 
signal dd :integer;
164 
begin
165 
process(clk,rst)
166 
begin
167 
        if rst = '1' then
168 
                cnt <=  (others => '0');
169 
                cnt1 <= (others => '0');
170 
                cnt2 <= (others => '0');
171 
                run <= '0';
172 
                st1 <= '0';
173 
                rg0 <= conv_std_logic_vector(A_range -1,10);
174 
        elsif clk = '1' and clk'event then
175 
        if str = '1' then st1 <= '1'; end if;
176 
        if str = '1' then cnt <= (others => '0');
177 
        elsif (cnt /= A_range -1 and st1 = '1') then cnt <= cnt + 1;
178 
        end if;
179 
        if (str = '1' or (cnt1 = 0 and cnt2 = G_range)or cnt2 = G_range + 1) then run <= '0';
180 
        elsif cnt = A_range -1 then run <= '1';
181 
        end if;
182 
 
183 
        if str = '1' then rg0 <= conv_std_logic_vector(A_range -1,10);
184 
        elsif cnt1 = 0 then rg0 <= rg0 + conv_std_logic_vector(A_range -1,10);
185 
        end if;
186 
        if str = '1' then  cnt1 <=  conv_std_logic_vector(A_range -1,10);
187 
        elsif cnt1 = 0 then cnt1 <= rg0 + conv_std_logic_vector(A_range -1,10);
188 
        elsif run = '1' then cnt1 <= cnt1 - cnt2;
189 
        end if;
190 
        if str = '1' then cnt2 <= ext("01",10);
191 
        elsif cnt1 = 0 then cnt2 <= cnt2 + 1; end if;
192 
                r1 <= run;
193 
                if r1 = '0' and run = '1' then d_out1 <= reg2; end if;
194 
        end if;
195 
end process;
196 
 
197 
data <= d_in when run = '0' else reg2(A_range -1);
198 
process(clk)
199 
begin
200 
        if clk = '1' and clk'event then
201 
                reg2(A_range - 1 downto 1) <= reg2(A_range - 2 downto 0);
202 
                reg2(0) <= data;
203 
        end if;
204 
end process;
205 
m2i <= conv_std_logic_vector(tb2si(conv_integer(cnt1)),8);
206 
dd <= conv_integer(cnt1);
207 
 
208 
mul : mul_g8
209 
         port map(
210 
                 clk => clk, rst => rst,
211 
                 m_d => '0',
212 
                 a => m2i,       b => data,
213 
                 res => dm
214 
             );
215 
process(clk,rst)
216 
begin
217 
        if rst = '1' then
218 
                ds <=  (others => '0');
219 
                run1 <= '0';
220 
                s0 <= '0';
221 
                s1 <= '0';
222 
        elsif clk = '1' and clk'event then
223 
        if run = '1' and cnt1 = 0 then s0 <= '1'; else s0 <= '0'; end if;
224 
                s1 <= s0;
225 
                run1 <= run;
226 
                if run1 = '0' then ds <= x"00";
227 
                elsif s1 = '1' then ds <= dm;
228 
                else ds <= ds xor dm;
229 
                end if;
230 
                if s1 = '1' then
231 
                        reg(g_range downto 1) <= reg(g_range -1 downto 0);
232 
                        reg(0) <= ds;
233 
                end if;
234 
                if str = '1' then s_er <= '0';
235 
                elsif s1 = '1' and ds /= x"00" then s_er <= '1';
236 
                end if;
237 
 
238 
 
239 
        end if;
240 
end process;
241 
process(clk,rst)
242 
begin
243 
        if rst = '1' then
244 
                snb <= '0';
245 
        elsif clk = '1' and clk'event then
246 
                s2 <= s1 and not run;
247 
                if s2 = '1' then
248 
                        reg1 <= reg;
249 
                else
250 
                        reg1(g_range downto 1) <= reg1(g_range -1 downto 0);reg1(0) <= x"00";
251 
                end if;
252 
                snb <= s2;
253 
                d_out <= reg1(g_range -1);
254 
        end if;
255 
end process;
256 
 
257 
 
258 
         -- enter your statements here --
259 
 
260 
end RS_DEC_SINDDROM;

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