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unicore |
---------------------------------------------------------------------
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---- ----
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---- Reed Solomon decoder/encoder IP core ----
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---- ----
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---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
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---- Company: Unicore Systems http://unicore.co.ua ----
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---- ----
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---- Downloaded from: http://www.opencores.org ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006-2010 Unicore Systems LTD ----
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---- www.unicore.co.ua ----
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---- o.uzenkov@unicore.co.ua ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED "AS IS" ----
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---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
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---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
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---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
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---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
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---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
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---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
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---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
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---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
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---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
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---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
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---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
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---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
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---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_unsigned .all;
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use IEEE.STD_LOGIC_arith .all;
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use type1.all;
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entity VEC_MUL is
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port(
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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m_d : in STD_LOGIC;
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A,B : in kgx8;
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C : out kgx8
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);
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end VEC_MUL;
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--}} End of automatically maintained section
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architecture VEC_MUL of VEC_MUL is
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component mul_g8 is
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port(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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m_d : in STD_LOGIC;
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a : in STD_LOGIC_VECTOR(7 downto 0);
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b : in STD_LOGIC_VECTOR(7 downto 0);
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res : out STD_LOGIC_VECTOR(7 downto 0)
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);
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end component;
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begin
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U_md: for i in 0 to G_range - 1 generate
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mul : mul_g8
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port map(
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clk => clk, rst => rst,
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m_d => m_d,
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a => a(i), b => b(i),
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res => c(i)
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);
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end generate;
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-- enter your statements here --
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end VEC_MUL;
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