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[/] [rs_decoder_31_19_6/] [trunk/] [controller.v] - Blame information for rev 4

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//****************************************************//
// This controller provides timing synchronization    //
// among all four modules (SC, KES, CSEE and FIFO     //
// Registers). It consists of 2 FSMs that operate on  //
// different clock phases.                            //
// With these FSMs, it is possible for SC block to    //
// get new received word data, while CSEE is still    //
// correcting old data. It is no need to wait the     //
// CSEE block to correct old data completely.         //
// So, it can minimize throughput bottleneck          //
// to only in KES block.                              //
//****************************************************//
 
module MainControl(start, reset, clock1, clock2, finish_kes,
                  errdetect, rootcntr, lambda_degree, active_sc,
                  active_kes, active_csee, evalsynd, holdsynd,
                  errfound, decode_fail, ready, dataoutstart,
                  dataoutend, shift_fifo, hold_fifo, en_infifo,
                  en_outfifo, lastdataout, evalerror);
 
input start, reset;
input clock1, clock2;
input errdetect, finish_kes;
input [2:0] rootcntr, lambda_degree;
output active_sc, active_kes, active_csee, ready;
output evalsynd, holdsynd, errfound, decode_fail;
output dataoutstart, dataoutend;
output shift_fifo, hold_fifo, en_infifo, en_outfifo;
output lastdataout, evalerror;
 
reg active_sc, active_kes, active_csee;
reg ready, decode_fail, evalsynd, holdsynd, errfound;
reg shift_fifo, hold_fifo, en_infifo, en_outfifo;
reg encntdataout, encntdatain;
reg [4:0] cntdatain, cntdataout;
reg dataoutstart, dataoutend;
reg datainfinish;
wire lastdataout;
 
parameter [3:0] st1_0=0, st1_1=1, st1_2=2, st1_3=3, st1_4=4, st1_5=5,
                st1_6=6, st1_7=7, st1_8=8, st1_9=9, st1_10=10,
                st1_11=11, st1_12=12, st1_13=13, st1_14=14;
reg [3:0] state1, nxt_state1;
 
parameter [3:0] st2_0=0, st2_1=1, st2_2=2, st2_3=3, st2_4=4, st2_5=5,
                st2_6=6, st2_7=7, st2_8=8, st2_9=9, st2_10=10,
                st2_11=11;
reg [3:0] state2, nxt_state2;
 
//***************************************************//
//                    FSM 1                          //
//***************************************************//
always@(posedge clock1 or negedge reset)
begin
    if(~reset)
      state1 = st1_0;
    else
      state1 = nxt_state1;
end
 
always@(state1 or start or rootcntr or lambda_degree or errdetect
         or datainfinish or finish_kes or dataoutend)
begin
   case(state1)
        st1_0 : begin
                if(start)
                  nxt_state1 = st1_1;
                else
                  nxt_state1 = st1_0;
                end
        st1_1 : nxt_state1 = st1_2;
        st1_2 : begin
                if(datainfinish)
                   nxt_state1 = st1_3;
                else
                   nxt_state1 = st1_2;
                end
        st1_3 : begin
                if(errdetect)
                   nxt_state1 = st1_4;
                else
                   nxt_state1 = st1_12;
                end
        st1_4 : nxt_state1 = st1_5;
        st1_5 : begin
                if(finish_kes)
                  nxt_state1 = st1_6;
                else
                   nxt_state1 = st1_5;
                end
        st1_6 : nxt_state1 = st1_7;
        st1_7 : begin
                if((~start)&&(~dataoutend))
                   nxt_state1 = st1_7;
                else if(dataoutend)
                   begin
                       if(lambda_degree == rootcntr)
                          nxt_state1 = st1_0;
                       else
                          nxt_state1 = st1_10;
                   end
                else
                   nxt_state1 = st1_8;
                end
        st1_8 : begin
                if(dataoutend)
                   begin
                      if(lambda_degree == rootcntr)
                         nxt_state1 = st1_2;
                      else
                         nxt_state1 = st1_11;
                   end
                else
                   nxt_state1 = st1_9;
                end
        st1_9 : begin
                if(dataoutend)
                   begin
                      if(lambda_degree == rootcntr)
                         nxt_state1 = st1_2;
                      else
                         nxt_state1 = st1_11;
                   end
                else
                   nxt_state1 = st1_9;
                end
        st1_10: begin
                if(start)
                   nxt_state1 = st1_1;
                else
                   nxt_state1 = st1_0;
                end
        st1_11: begin
                if(datainfinish)
                   nxt_state1 = st1_3;
                else
                   nxt_state1 = st1_2;
                end
        st1_12: begin
                if((~start)&&(~dataoutend))
                   nxt_state1 = st1_12;
                else if(dataoutend)
                   nxt_state1 = st1_0;
                else
                   nxt_state1 = st1_13;
                end
        st1_13: begin
                if(dataoutend)
                   nxt_state1 = st1_2;
                else
                   nxt_state1 = st1_14;
                end
        st1_14: begin
                if(dataoutend)
                   nxt_state1 = st1_2;
                else
                   nxt_state1 = st1_14;
                end
       default: nxt_state1 = st1_0;
   endcase
end
 
// Output logic of FSM1 //
always@(state1)
begin
    case(state1)
        st1_0 :begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_1 :begin
               ready = 1;
               active_sc = 1;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_2 :begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_3 :begin
               ready = 0;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 1;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_4 :begin
               ready = 0;
               active_sc = 0;
               active_kes = 1;
               active_csee = 0;
               evalsynd = 0;
               errfound = 1;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_5 :begin
               ready = 0;
               active_sc = 0;
               active_kes = 1;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_6 :begin
               ready = 0;
               active_sc = 0;
               active_kes = 1;
               active_csee = 1;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
        st1_7 :begin
               ready = 1;
               active_sc = 0;
               active_kes = 1;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 1;
               end
        st1_8 :begin
               ready = 1;
               active_sc = 1;
               active_kes = 1;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 1;
               end
        st1_9 :begin
               ready = 1;
               active_sc = 0;
               active_kes = 1;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 1;
               end
        st1_10:begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 1;
               en_outfifo = 0;
               end
        st1_11:begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 1;
               en_outfifo = 0;
               end
        st1_12:begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 1;
               end
        st1_13:begin
               ready = 1;
               active_sc = 1;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 1;
               end
        st1_14:begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 1;
               end
       default:begin
               ready = 1;
               active_sc = 0;
               active_kes = 0;
               active_csee = 0;
               evalsynd = 0;
               errfound = 0;
               decode_fail = 0;
               en_outfifo = 0;
               end
    endcase
end
 
//****************************************// 
//                 FSM 2                  //
//****************************************//
always@(posedge clock2 or negedge reset)
begin
   if(~reset)
      state2 = st2_0;
   else
      state2 = nxt_state2;
end
 
always@(state2 or active_sc or cntdatain or lastdataout or en_outfifo)
begin
   case(state2)
      st2_0 : begin
              if(active_sc)
                 nxt_state2 = st2_1;
              else
                 nxt_state2 = st2_0;
              end
      st2_1 : begin
              if(cntdatain == 5'b11110)
                 nxt_state2 = st2_2;
              else
                 nxt_state2 = st2_1;
              end
      st2_2 : nxt_state2 = st2_3;
      st2_3 : begin
              if(en_outfifo)
                 nxt_state2 = st2_4;
              else
                 nxt_state2 = st2_3;
              end
      st2_4 : begin
              if(active_sc)
                 nxt_state2 = st2_8;
              else
                 nxt_state2 = st2_5;
              end
      st2_5 : begin
              if(active_sc)
                 nxt_state2 = st2_9;
              else
                 nxt_state2 = st2_6;
              end
      st2_6 : begin
              if(active_sc)
                 nxt_state2 = st2_9;
              else if((lastdataout) && (~active_sc))
                 nxt_state2 = st2_7;
              else
                 nxt_state2 = st2_6;
              end
      st2_7 : begin
              if(active_sc)
                 nxt_state2 = st2_1;
              else
                 nxt_state2 = st2_0;
              end
      st2_8 : nxt_state2 = st2_9;
      st2_9 : begin
              if((lastdataout) && (cntdatain==5'b11110))
                 nxt_state2 = st2_10;
              else if(lastdataout)
                 nxt_state2 = st2_11;
              else
                 nxt_state2 = st2_9;
              end
      st2_10: nxt_state2 = st2_3;
      st2_11: begin
              if(cntdatain==5'b11110)
                 nxt_state2 = st2_2;
              else
                 nxt_state2 = st2_1;
              end
      default: nxt_state2 = st2_0;
   endcase
end
 
// Output logic of FSM 2 //
always@(state2)
begin
    case(state2)
        st2_0 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 0;
                hold_fifo = 0;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_1 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 1;
                encntdatain = 1;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_2 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 1;
                encntdatain = 0;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 1;
                end
        st2_3 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 0;
                hold_fifo = 1;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 0;
                holdsynd = 1;
                datainfinish = 0;
                end
        st2_4 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 0;
                hold_fifo = 1;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 1;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_5 : begin
                dataoutstart = 1;
                dataoutend = 0;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 1;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_6 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 1;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_7 : begin
                dataoutstart = 0;
                dataoutend = 1;
                shift_fifo = 0;
                hold_fifo = 0;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_8 : begin
                dataoutstart = 1;
                dataoutend = 0;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 1;
                encntdatain = 1;
                encntdataout = 1;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_9 : begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 1;
                encntdatain = 1;
                encntdataout = 1;
                holdsynd = 0;
                datainfinish = 0;
                end
        st2_10: begin
                dataoutstart = 0;
                dataoutend = 1;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 1;
                encntdatain = 0;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 1;
                end
        st2_11: begin
                dataoutstart = 0;
                dataoutend = 1;
                shift_fifo = 1;
                hold_fifo = 0;
                en_infifo = 1;
                encntdatain = 1;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 0;
                end
       default: begin
                dataoutstart = 0;
                dataoutend = 0;
                shift_fifo = 0;
                hold_fifo = 0;
                en_infifo = 0;
                encntdatain = 0;
                encntdataout = 0;
                holdsynd = 0;
                datainfinish = 0;
                end
   endcase
  end
 
 
//*********************//
// Counter for dataout //               
always@(posedge clock1)
begin
   if(encntdataout)
      cntdataout =  cntdataout + 1;
   else
      cntdataout = 5'b0;
end
 
// Counter for datain //               
always@(posedge clock1)
begin
   if(encntdatain)
      cntdatain =  cntdatain + 1;
   else
      cntdatain = 5'b0;
end
 
// lastdataout is 1 if cntdataout = 5'b11111 //
assign lastdataout = cntdataout[4] & (cntdataout[3]&cntdataout[2]) &
                     (cntdataout[1]&cntdataout[0]);
 
assign evalerror = encntdataout;
 
endmodule

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Subversion Repositories rs_decoder_31_19_6

[/] [rs_decoder_31_19_6/] [trunk/] [controller.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	rud_dp	`//****************************************************//`
2			`// This controller provides timing synchronization //`
3			`// among all four modules (SC, KES, CSEE and FIFO //`
4			`// Registers). It consists of 2 FSMs that operate on //`
5			`// different clock phases. //`
6			`// With these FSMs, it is possible for SC block to //`
7			`// get new received word data, while CSEE is still //`
8			`// correcting old data. It is no need to wait the //`
9			`// CSEE block to correct old data completely. //`
10			`// So, it can minimize throughput bottleneck //`
11			`// to only in KES block. //`
12			`//****************************************************//`
13
14			`module MainControl(start, reset, clock1, clock2, finish_kes,`
15			`errdetect, rootcntr, lambda_degree, active_sc,`
16			`active_kes, active_csee, evalsynd, holdsynd,`
17			`errfound, decode_fail, ready, dataoutstart,`
18			`dataoutend, shift_fifo, hold_fifo, en_infifo,`
19			`en_outfifo, lastdataout, evalerror);`
20
21			`input start, reset;`
22			`input clock1, clock2;`
23			`input errdetect, finish_kes;`
24			`input [2:0] rootcntr, lambda_degree;`
25			`output active_sc, active_kes, active_csee, ready;`
26			`output evalsynd, holdsynd, errfound, decode_fail;`
27			`output dataoutstart, dataoutend;`
28			`output shift_fifo, hold_fifo, en_infifo, en_outfifo;`
29			`output lastdataout, evalerror;`
30
31			`reg active_sc, active_kes, active_csee;`
32			`reg ready, decode_fail, evalsynd, holdsynd, errfound;`
33			`reg shift_fifo, hold_fifo, en_infifo, en_outfifo;`
34			`reg encntdataout, encntdatain;`
35			`reg [4:0] cntdatain, cntdataout;`
36			`reg dataoutstart, dataoutend;`
37			`reg datainfinish;`
38			`wire lastdataout;`
39
40			`parameter [3:0] st1_0=0, st1_1=1, st1_2=2, st1_3=3, st1_4=4, st1_5=5,`
41			`st1_6=6, st1_7=7, st1_8=8, st1_9=9, st1_10=10,`
42			`st1_11=11, st1_12=12, st1_13=13, st1_14=14;`
43			`reg [3:0] state1, nxt_state1;`
44
45			`parameter [3:0] st2_0=0, st2_1=1, st2_2=2, st2_3=3, st2_4=4, st2_5=5,`
46			`st2_6=6, st2_7=7, st2_8=8, st2_9=9, st2_10=10,`
47			`st2_11=11;`
48			`reg [3:0] state2, nxt_state2;`
49
50			`//***************************************************//`
51			`// FSM 1 //`
52			`//***************************************************//`
53			`always@(posedge clock1 or negedge reset)`
54			`begin`
55			`if(~reset)`
56			`state1 = st1_0;`
57			`else`
58			`state1 = nxt_state1;`
59			`end`
60
61			`always@(state1 or start or rootcntr or lambda_degree or errdetect`
62			`or datainfinish or finish_kes or dataoutend)`
63			`begin`
64			`case(state1)`
65			`st1_0 : begin`
66			`if(start)`
67			`nxt_state1 = st1_1;`
68			`else`
69			`nxt_state1 = st1_0;`
70			`end`
71			`st1_1 : nxt_state1 = st1_2;`
72			`st1_2 : begin`
73			`if(datainfinish)`
74			`nxt_state1 = st1_3;`
75			`else`
76			`nxt_state1 = st1_2;`
77			`end`
78			`st1_3 : begin`
79			`if(errdetect)`
80			`nxt_state1 = st1_4;`
81			`else`
82			`nxt_state1 = st1_12;`
83			`end`
84			`st1_4 : nxt_state1 = st1_5;`
85			`st1_5 : begin`
86			`if(finish_kes)`
87			`nxt_state1 = st1_6;`
88			`else`
89			`nxt_state1 = st1_5;`
90			`end`
91			`st1_6 : nxt_state1 = st1_7;`
92			`st1_7 : begin`
93			`if((~start)&&(~dataoutend))`
94			`nxt_state1 = st1_7;`
95			`else if(dataoutend)`
96			`begin`
97			`if(lambda_degree == rootcntr)`
98			`nxt_state1 = st1_0;`
99			`else`
100			`nxt_state1 = st1_10;`
101			`end`
102			`else`
103			`nxt_state1 = st1_8;`
104			`end`
105			`st1_8 : begin`
106			`if(dataoutend)`
107			`begin`
108			`if(lambda_degree == rootcntr)`
109			`nxt_state1 = st1_2;`
110			`else`
111			`nxt_state1 = st1_11;`
112			`end`
113			`else`
114			`nxt_state1 = st1_9;`
115			`end`
116			`st1_9 : begin`
117			`if(dataoutend)`
118			`begin`
119			`if(lambda_degree == rootcntr)`
120			`nxt_state1 = st1_2;`
121			`else`
122			`nxt_state1 = st1_11;`
123			`end`
124			`else`
125			`nxt_state1 = st1_9;`
126			`end`
127			`st1_10: begin`
128			`if(start)`
129			`nxt_state1 = st1_1;`
130			`else`
131			`nxt_state1 = st1_0;`
132			`end`
133			`st1_11: begin`
134			`if(datainfinish)`
135			`nxt_state1 = st1_3;`
136			`else`
137			`nxt_state1 = st1_2;`
138			`end`
139			`st1_12: begin`
140			`if((~start)&&(~dataoutend))`
141			`nxt_state1 = st1_12;`
142			`else if(dataoutend)`
143			`nxt_state1 = st1_0;`
144			`else`
145			`nxt_state1 = st1_13;`
146			`end`
147			`st1_13: begin`
148			`if(dataoutend)`
149			`nxt_state1 = st1_2;`
150			`else`
151			`nxt_state1 = st1_14;`
152			`end`
153			`st1_14: begin`
154			`if(dataoutend)`
155			`nxt_state1 = st1_2;`
156			`else`
157			`nxt_state1 = st1_14;`
158			`end`
159			`default: nxt_state1 = st1_0;`
160			`endcase`
161			`end`
162
163			`// Output logic of FSM1 //`
164			`always@(state1)`
165			`begin`
166			`case(state1)`
167			`st1_0 :begin`
168			`ready = 1;`
169			`active_sc = 0;`
170			`active_kes = 0;`
171			`active_csee = 0;`
172			`evalsynd = 0;`
173			`errfound = 0;`
174			`decode_fail = 0;`
175			`en_outfifo = 0;`
176			`end`
177			`st1_1 :begin`
178			`ready = 1;`
179			`active_sc = 1;`
180			`active_kes = 0;`
181			`active_csee = 0;`
182			`evalsynd = 0;`
183			`errfound = 0;`
184			`decode_fail = 0;`
185			`en_outfifo = 0;`
186			`end`
187			`st1_2 :begin`
188			`ready = 1;`
189			`active_sc = 0;`
190			`active_kes = 0;`
191			`active_csee = 0;`
192			`evalsynd = 0;`
193			`errfound = 0;`
194			`decode_fail = 0;`
195			`en_outfifo = 0;`
196			`end`
197			`st1_3 :begin`
198			`ready = 0;`
199			`active_sc = 0;`
200			`active_kes = 0;`
201			`active_csee = 0;`
202			`evalsynd = 1;`
203			`errfound = 0;`
204			`decode_fail = 0;`
205			`en_outfifo = 0;`
206			`end`
207			`st1_4 :begin`
208			`ready = 0;`
209			`active_sc = 0;`
210			`active_kes = 1;`
211			`active_csee = 0;`
212			`evalsynd = 0;`
213			`errfound = 1;`
214			`decode_fail = 0;`
215			`en_outfifo = 0;`
216			`end`
217			`st1_5 :begin`
218			`ready = 0;`
219			`active_sc = 0;`
220			`active_kes = 1;`
221			`active_csee = 0;`
222			`evalsynd = 0;`
223			`errfound = 0;`
224			`decode_fail = 0;`
225			`en_outfifo = 0;`
226			`end`
227			`st1_6 :begin`
228			`ready = 0;`
229			`active_sc = 0;`
230			`active_kes = 1;`
231			`active_csee = 1;`
232			`evalsynd = 0;`
233			`errfound = 0;`
234			`decode_fail = 0;`
235			`en_outfifo = 0;`
236			`end`
237			`st1_7 :begin`
238			`ready = 1;`
239			`active_sc = 0;`
240			`active_kes = 1;`
241			`active_csee = 0;`
242			`evalsynd = 0;`
243			`errfound = 0;`
244			`decode_fail = 0;`
245			`en_outfifo = 1;`
246			`end`
247			`st1_8 :begin`
248			`ready = 1;`
249			`active_sc = 1;`
250			`active_kes = 1;`
251			`active_csee = 0;`
252			`evalsynd = 0;`
253			`errfound = 0;`
254			`decode_fail = 0;`
255			`en_outfifo = 1;`
256			`end`
257			`st1_9 :begin`
258			`ready = 1;`
259			`active_sc = 0;`
260			`active_kes = 1;`
261			`active_csee = 0;`
262			`evalsynd = 0;`
263			`errfound = 0;`
264			`decode_fail = 0;`
265			`en_outfifo = 1;`
266			`end`
267			`st1_10:begin`
268			`ready = 1;`
269			`active_sc = 0;`
270			`active_kes = 0;`
271			`active_csee = 0;`
272			`evalsynd = 0;`
273			`errfound = 0;`
274			`decode_fail = 1;`
275			`en_outfifo = 0;`
276			`end`
277			`st1_11:begin`
278			`ready = 1;`
279			`active_sc = 0;`
280			`active_kes = 0;`
281			`active_csee = 0;`
282			`evalsynd = 0;`
283			`errfound = 0;`
284			`decode_fail = 1;`
285			`en_outfifo = 0;`
286			`end`
287			`st1_12:begin`
288			`ready = 1;`
289			`active_sc = 0;`
290			`active_kes = 0;`
291			`active_csee = 0;`
292			`evalsynd = 0;`
293			`errfound = 0;`
294			`decode_fail = 0;`
295			`en_outfifo = 1;`
296			`end`
297			`st1_13:begin`
298			`ready = 1;`
299			`active_sc = 1;`
300			`active_kes = 0;`
301			`active_csee = 0;`
302			`evalsynd = 0;`
303			`errfound = 0;`
304			`decode_fail = 0;`
305			`en_outfifo = 1;`
306			`end`
307			`st1_14:begin`
308			`ready = 1;`
309			`active_sc = 0;`
310			`active_kes = 0;`
311			`active_csee = 0;`
312			`evalsynd = 0;`
313			`errfound = 0;`
314			`decode_fail = 0;`
315			`en_outfifo = 1;`
316			`end`
317			`default:begin`
318			`ready = 1;`
319			`active_sc = 0;`
320			`active_kes = 0;`
321			`active_csee = 0;`
322			`evalsynd = 0;`
323			`errfound = 0;`
324			`decode_fail = 0;`
325			`en_outfifo = 0;`
326			`end`
327			`endcase`
328			`end`
329
330			`//****************************************//`
331			`// FSM 2 //`
332			`//****************************************//`
333			`always@(posedge clock2 or negedge reset)`
334			`begin`
335			`if(~reset)`
336			`state2 = st2_0;`
337			`else`
338			`state2 = nxt_state2;`
339			`end`
340
341			`always@(state2 or active_sc or cntdatain or lastdataout or en_outfifo)`
342			`begin`
343			`case(state2)`
344			`st2_0 : begin`
345			`if(active_sc)`
346			`nxt_state2 = st2_1;`
347			`else`
348			`nxt_state2 = st2_0;`
349			`end`
350			`st2_1 : begin`
351			`if(cntdatain == 5'b11110)`
352			`nxt_state2 = st2_2;`
353			`else`
354			`nxt_state2 = st2_1;`
355			`end`
356			`st2_2 : nxt_state2 = st2_3;`
357			`st2_3 : begin`
358			`if(en_outfifo)`
359			`nxt_state2 = st2_4;`
360			`else`
361			`nxt_state2 = st2_3;`
362			`end`
363			`st2_4 : begin`
364			`if(active_sc)`
365			`nxt_state2 = st2_8;`
366			`else`
367			`nxt_state2 = st2_5;`
368			`end`
369			`st2_5 : begin`
370			`if(active_sc)`
371			`nxt_state2 = st2_9;`
372			`else`
373			`nxt_state2 = st2_6;`
374			`end`
375			`st2_6 : begin`
376			`if(active_sc)`
377			`nxt_state2 = st2_9;`
378			`else if((lastdataout) && (~active_sc))`
379			`nxt_state2 = st2_7;`
380			`else`
381			`nxt_state2 = st2_6;`
382			`end`
383			`st2_7 : begin`
384			`if(active_sc)`
385			`nxt_state2 = st2_1;`
386			`else`
387			`nxt_state2 = st2_0;`
388			`end`
389			`st2_8 : nxt_state2 = st2_9;`
390			`st2_9 : begin`
391			`if((lastdataout) && (cntdatain==5'b11110))`
392			`nxt_state2 = st2_10;`
393			`else if(lastdataout)`
394			`nxt_state2 = st2_11;`
395			`else`
396			`nxt_state2 = st2_9;`
397			`end`
398			`st2_10: nxt_state2 = st2_3;`
399			`st2_11: begin`
400			`if(cntdatain==5'b11110)`
401			`nxt_state2 = st2_2;`
402			`else`
403			`nxt_state2 = st2_1;`
404			`end`
405			`default: nxt_state2 = st2_0;`
406			`endcase`
407			`end`
408
409			`// Output logic of FSM 2 //`
410			`always@(state2)`
411			`begin`
412			`case(state2)`
413			`st2_0 : begin`
414			`dataoutstart = 0;`
415			`dataoutend = 0;`
416			`shift_fifo = 0;`
417			`hold_fifo = 0;`
418			`en_infifo = 0;`
419			`encntdatain = 0;`
420			`encntdataout = 0;`
421			`holdsynd = 0;`
422			`datainfinish = 0;`
423			`end`
424			`st2_1 : begin`
425			`dataoutstart = 0;`
426			`dataoutend = 0;`
427			`shift_fifo = 1;`
428			`hold_fifo = 0;`
429			`en_infifo = 1;`
430			`encntdatain = 1;`
431			`encntdataout = 0;`
432			`holdsynd = 0;`
433			`datainfinish = 0;`
434			`end`
435			`st2_2 : begin`
436			`dataoutstart = 0;`
437			`dataoutend = 0;`
438			`shift_fifo = 1;`
439			`hold_fifo = 0;`
440			`en_infifo = 1;`
441			`encntdatain = 0;`
442			`encntdataout = 0;`
443			`holdsynd = 0;`
444			`datainfinish = 1;`
445			`end`
446			`st2_3 : begin`
447			`dataoutstart = 0;`
448			`dataoutend = 0;`
449			`shift_fifo = 0;`
450			`hold_fifo = 1;`
451			`en_infifo = 0;`
452			`encntdatain = 0;`
453			`encntdataout = 0;`
454			`holdsynd = 1;`
455			`datainfinish = 0;`
456			`end`
457			`st2_4 : begin`
458			`dataoutstart = 0;`
459			`dataoutend = 0;`
460			`shift_fifo = 0;`
461			`hold_fifo = 1;`
462			`en_infifo = 0;`
463			`encntdatain = 0;`
464			`encntdataout = 1;`
465			`holdsynd = 0;`
466			`datainfinish = 0;`
467			`end`
468			`st2_5 : begin`
469			`dataoutstart = 1;`
470			`dataoutend = 0;`
471			`shift_fifo = 1;`
472			`hold_fifo = 0;`
473			`en_infifo = 0;`
474			`encntdatain = 0;`
475			`encntdataout = 1;`
476			`holdsynd = 0;`
477			`datainfinish = 0;`
478			`end`
479			`st2_6 : begin`
480			`dataoutstart = 0;`
481			`dataoutend = 0;`
482			`shift_fifo = 1;`
483			`hold_fifo = 0;`
484			`en_infifo = 0;`
485			`encntdatain = 0;`
486			`encntdataout = 1;`
487			`holdsynd = 0;`
488			`datainfinish = 0;`
489			`end`
490			`st2_7 : begin`
491			`dataoutstart = 0;`
492			`dataoutend = 1;`
493			`shift_fifo = 0;`
494			`hold_fifo = 0;`
495			`en_infifo = 0;`
496			`encntdatain = 0;`
497			`encntdataout = 0;`
498			`holdsynd = 0;`
499			`datainfinish = 0;`
500			`end`
501			`st2_8 : begin`
502			`dataoutstart = 1;`
503			`dataoutend = 0;`
504			`shift_fifo = 1;`
505			`hold_fifo = 0;`
506			`en_infifo = 1;`
507			`encntdatain = 1;`
508			`encntdataout = 1;`
509			`holdsynd = 0;`
510			`datainfinish = 0;`
511			`end`
512			`st2_9 : begin`
513			`dataoutstart = 0;`
514			`dataoutend = 0;`
515			`shift_fifo = 1;`
516			`hold_fifo = 0;`
517			`en_infifo = 1;`
518			`encntdatain = 1;`
519			`encntdataout = 1;`
520			`holdsynd = 0;`
521			`datainfinish = 0;`
522			`end`
523			`st2_10: begin`
524			`dataoutstart = 0;`
525			`dataoutend = 1;`
526			`shift_fifo = 1;`
527			`hold_fifo = 0;`
528			`en_infifo = 1;`
529			`encntdatain = 0;`
530			`encntdataout = 0;`
531			`holdsynd = 0;`
532			`datainfinish = 1;`
533			`end`
534			`st2_11: begin`
535			`dataoutstart = 0;`
536			`dataoutend = 1;`
537			`shift_fifo = 1;`
538			`hold_fifo = 0;`
539			`en_infifo = 1;`
540			`encntdatain = 1;`
541			`encntdataout = 0;`
542			`holdsynd = 0;`
543			`datainfinish = 0;`
544			`end`
545			`default: begin`
546			`dataoutstart = 0;`
547			`dataoutend = 0;`
548			`shift_fifo = 0;`
549			`hold_fifo = 0;`
550			`en_infifo = 0;`
551			`encntdatain = 0;`
552			`encntdataout = 0;`
553			`holdsynd = 0;`
554			`datainfinish = 0;`
555			`end`
556			`endcase`
557			`end`
558
559
560			`//*********************//`
561			`// Counter for dataout //`
562			`always@(posedge clock1)`
563			`begin`
564			`if(encntdataout)`
565			`cntdataout = cntdataout + 1;`
566			`else`
567			`cntdataout = 5'b0;`
568			`end`
569
570			`// Counter for datain //`
571			`always@(posedge clock1)`
572			`begin`
573			`if(encntdatain)`
574			`cntdatain = cntdatain + 1;`
575			`else`
576			`cntdatain = 5'b0;`
577			`end`
578
579			`// lastdataout is 1 if cntdataout = 5'b11111 //`
580			`assign lastdataout = cntdataout[4] & (cntdataout[3]&cntdataout[2]) &`
581			`(cntdataout[1]&cntdataout[0]);`
582
583			`assign evalerror = encntdataout;`
584
585			`endmodule`