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[/] [rs_decoder_31_19_6/] [trunk/] [testbench.v] - Blame information for rev 6

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///*************************************************************///
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///                                                             ///
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///          Reed-Solomon Decoder (31,19,6)                     ///
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///                                                             ///
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///                                                             ///
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///          Author : Rudy Dwi Putra                            ///
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///                   rudy.dp@gmail.com                         ///
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///                                                             ///
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///*************************************************************///
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///                                                             ///
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/// Copyright (C) 2006  Rudy Dwi Putra                          ///
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///                     rudy.dp@gmail.com                       ///
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///                                                             ///
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/// This source file may be used and distributed without        ///
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/// restriction provided that this copyright statement is not   ///
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/// removed from the file and that any derivative work contains ///
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/// the original copyright notice and the associated disclaimer.///
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///                                                             ///
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///     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ///
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/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ///
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/// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ///
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/// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ///
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/// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ///
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/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ///
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/// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ///
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/// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ///
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/// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ///
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/// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ///
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/// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ///
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/// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ///
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/// POSSIBILITY OF SUCH DAMAGE.                                 ///
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///                                                             ///
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///*************************************************************///
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//***************************************//
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// Testbench for RS Decoder (31, 19, 6)  //
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//***************************************//
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module testbench_rsdecoder;
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reg [4:0] recword;
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reg clock1, clock2;
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reg start, reset;
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//******************************************************//
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// ready = if set to 1, decoder is ready to input or it //
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// is inputting new data                                                                                                                                //
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// dataoutstart = flag the first symbol of outputted            //
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// received word.                                                                                                                                                               //
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// dataoutend = flag the last symbol of outputted                               //
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// received word.                                                                                                                                                               //
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// errfound = set to 1, if one of syndrome values                       //
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// is not zero.                                                                                                                                                                 //
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// decode_fail = set to 1, if decoder fails to correct  //
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// the received word.                                                                                                                                           //
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//******************************************************//
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wire ready, decode_fail, errfound, dataoutstart, dataoutend;
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wire [4:0] corr_recword;
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parameter [5:0] clk_period = 50;
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initial
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begin
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   recword = 5'b0;
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   start = 0;
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   reset = 0;
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end
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//**********//
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//  clock1  //
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//**********//
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initial
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begin
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    clock1 = 0;
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    forever #(clk_period/2) clock1 = ~clock1;
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end
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//**********//
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//  clock2  //
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//**********//
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initial
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begin
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    clock2 = 1;
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    forever #(clk_period/2) clock2 = ~clock2;
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end
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//***********************************************//
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// This section defines feeding of received word //
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// and start signal. Start signal is active 1    //
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// clock cycle before first symbol of received   //
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// word. All input and output synchronize with   //
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// clock2. First received word contains no error //
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// symbol. Thus, all syndrome values will be zero//
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// and decoder will pass the received word.      //
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// Second received word contains 6 error symbol. //
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// Decoder will determine its error locator      //
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// and error evaluator polynomial in KES block.  //
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// Then, it calculates error values in CSEE      //
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// block. Third received word contains 8 error   //
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// symbol. Decoder can't correct the error and   //
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// at the end of outputted received word, it will//
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// set decode_fail to 1.                         //
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//***********************************************//  
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initial
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begin
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    #(clk_period) reset = 1;
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    //start has to be active 1 clock cycle before first recword, 
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    //otherwise decoder will output wrong recword.
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    #(clk_period) start = 1;
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    #(clk_period) start = 0;
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    //First received word contains no error symbol.
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    //The decoder should give errfound = 0 at the end
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    //of syndrome calculation stage.
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    recword = 5'b10100;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b00101;
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    #(clk_period) recword = 5'b10001;
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    #(clk_period) recword = 5'b10110;
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    #(clk_period) recword = 5'b00001;
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    #(clk_period) recword = 5'b00010;
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    #(clk_period) recword = 5'b11100;
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    #(clk_period) recword = 5'b00011;
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    #(clk_period) recword = 5'b10001;
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    #(clk_period) recword = 5'b00110;
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    #(clk_period) recword = 5'b00111;
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    #(clk_period) recword = 5'b01010;
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    #(clk_period) recword = 5'b11111;
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    #(clk_period) recword = 5'b01011;
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b00101;
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    #(clk_period) recword = 5'b00001;
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    #(clk_period) recword = 5'b10111;
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b00010;
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    #(clk_period) recword = 5'b10110;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b01011;
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    #(clk_period) recword = 5'b00110;
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    #(clk_period) recword = 5'b11110;
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b11111;
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    #(clk_period) recword = 5'b01010;
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    #(clk_period) recword = 5'b11110;
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    #(clk_period) recword = 5'b0;
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    #(18*clk_period) start = 1;
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    #(clk_period) start = 0;
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    //Second received word contains 6 error symbols.
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    //The decoder sets errfound = 1, and activates
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    //KES block and then CSEE block. Because the
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    //number of errors is equal to correction capability
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    //of the decoder, decoder can correct the received
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    //word.
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    recword = 5'b01100; //it should be 5'b10100
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b00101;
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    #(clk_period) recword = 5'b10001;
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    #(clk_period) recword = 5'b10110;
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    #(clk_period) recword = 5'b00001;
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    #(clk_period) recword = 5'b00110; //it should be 5'b00010
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    #(clk_period) recword = 5'b11100;
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    #(clk_period) recword = 5'b00011;
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    #(clk_period) recword = 5'b10001;
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    #(clk_period) recword = 5'b00110;
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    #(clk_period) recword = 5'b00101; //it should be 5'b00111
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    #(clk_period) recword = 5'b01010;
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    #(clk_period) recword = 5'b11111;
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    #(clk_period) recword = 5'b11111; //it should be 5'b01011
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b00101;
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    #(clk_period) recword = 5'b00001;
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    #(clk_period) recword = 5'b10111;
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    #(clk_period) recword = 5'b01101; //it should be 5'b10100
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    #(clk_period) recword = 5'b00010;
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    #(clk_period) recword = 5'b10110;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b01011;
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    #(clk_period) recword = 5'b00110;
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    #(clk_period) recword = 5'b11110;
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b10101; //it should be 5'b11111
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    #(clk_period) recword = 5'b01010;
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    #(clk_period) recword = 5'b11110;
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    #(clk_period) recword = 5'b0;
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    #(20*clk_period) start = 1;
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    #(clk_period) start = 0;
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    //Third received word contains 8 error symbols.
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    //Because the number of errors is greater than correction
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    //capability, decoder will resume decoding failure at the end of
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    //outputted received word.
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    recword = 5'b10100;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b00101;
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    #(clk_period) recword = 5'b10001;
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    #(clk_period) recword = 5'b10110;
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    #(clk_period) recword = 5'b00100; //it should be 5'b00001
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    #(clk_period) recword = 5'b00010;
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    #(clk_period) recword = 5'b11100;
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    #(clk_period) recword = 5'b10010; //it should be 5'b00011
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    #(clk_period) recword = 5'b10101; //it should be 5'b10001
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    #(clk_period) recword = 5'b00110;
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    #(clk_period) recword = 5'b10011; //it should be 5'b00111
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    #(clk_period) recword = 5'b01010;
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    #(clk_period) recword = 5'b11111;
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    #(clk_period) recword = 5'b01011;
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b00110; //it should be 5'b00100
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    #(clk_period) recword = 5'b00101;
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    #(clk_period) recword = 5'b00100; //it should be 5'b00001
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    #(clk_period) recword = 5'b10110; //it should be 5'b10111
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    #(clk_period) recword = 5'b10100;
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    #(clk_period) recword = 5'b00010;
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    #(clk_period) recword = 5'b10110;
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    #(clk_period) recword = 5'b00100;
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    #(clk_period) recword = 5'b01011;
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    #(clk_period) recword = 5'b00110;
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    #(clk_period) recword = 5'b11110;
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    #(clk_period) recword = 5'b10010; //it should be 5'b10100
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    #(clk_period) recword = 5'b11111;
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    #(clk_period) recword = 5'b01010;
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    #(clk_period) recword = 5'b11110;
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    #(clk_period) recword = 5'b0;
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end
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RSDecoder rsdecoder(recword, start, clock1, clock2, reset, ready,
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                  errfound, decode_fail, dataoutstart, dataoutend,
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                  corr_recword);
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endmodule

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