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[/] [rs_encoder_decoder/] [rtl/] [RS8Controller.v] - Blame information for rev 2

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// This is a verilog File Generated
// By The C++ program That Generates
// Reed Solomon Controller  
// Barlekamp Messay Controller 
 
module RS8Controller(clk_i, rst_i,
  valid_i,                   // Controller input valid
  calc_S_0_o,                // Control Signal to Calculate S_0
  dft_sel_o,                 // select FFT or IFFT
  dft_calc_o,                // calculate fourier transform
  mem_in_o,                  // memory control signal to input what in the memory
  en_fir_o,                  // calculate new delta
  fir_sel_o,                 // calculate new delta
  calc_bm_step_o,            // Calculate BM Step
  step_o,                    // current_step
  done_bm_step_i,            // update from BM circuit
  elp_busy_i,                // Controller input busy signal from error loc poly
  r_calc_o,                  // To enable R0 to calculate
  r_calc_sel_o,              // To enable R0 to select memmory address
  r_calc_done_i,             // When R0 has completed the operation
  push_o,                    // push data in syndrom
  mem_addr_o,                // Memmory Address
  load_last_o,               // This is the first DFT calculation control signal 
  wren_o,                    // Write Data IN memmory
  done_dec_o,                // done BM decoding 
  last_in_sel_o,             // ouput data 0
  valid_o_o,                 // Asserted when data is being outputed from the RS decoder
  busy_o                     // States the Status of the RS decoder
  );
 
  // Declaration of the inputs
  input clk_i, rst_i;
  input valid_i;
  output reg dft_calc_o;
  output reg [1:0] dft_sel_o;
  output reg busy_o;
  output reg en_fir_o;
  output reg fir_sel_o;
  output reg valid_o_o;
 
  // Control Signals associated 
  output reg calc_S_0_o;
 
  // with Error Loc Poly calculator
  output reg calc_bm_step_o;
  output wire [7:0] step_o;
  input done_bm_step_i;
  input elp_busy_i;
 
  // R 0 calculator control signals
  input r_calc_done_i;   // When R0 has completed the operation
  output reg r_calc_sel_o;     // R0 memory address select
  output reg r_calc_o;       // to enable R0 to calculate
 
  output reg push_o;
  output reg done_dec_o;
 
  // MEMORY ADDRESS AND MEMORY CONTROL SIGNALS
  output wire [7:0] mem_addr_o;
  output reg mem_in_o;
  output reg wren_o;
 
 
  output reg load_last_o;
  output reg last_in_sel_o;
 
  // Declaration of Wires And Register are here 
  // Control Registers
  // INPUT COUNTER HANDLER
  reg [8:0] input_cntr;
  reg clr_input_cntr;
  always @ (posedge clk_i) begin
    if ((rst_i)||(clr_input_cntr)) begin
      input_cntr  = 0;
    end
    else if ((valid_i)&& (~(busy_o))) begin
      input_cntr = input_cntr + 1;
    end
  end
 
  // ErrorPolyCalcStep
  reg [7:0] step;
  always @ (posedge clk_i) begin
    if ((rst_i)||(done_dec_o)) begin
      step  = 0;
    end
    else if (done_bm_step_i) begin
      step = step + 1;
    end
  end
 
  reg clr_mem_addr;
  reg inc_mem_addr;
  reg [7:0] mem_addr;
  always @(posedge clk_i) begin
    if((rst_i)||(clr_mem_addr)) begin
      mem_addr = 0;
    end
    else if(inc_mem_addr) begin
      mem_addr = mem_addr +1;
    end
  end
 
  reg inc_idft_cntr;
  reg clr_idft_cntr;
  reg [7:0] idft_cntr;
  always @(posedge clk_i) begin
    if((rst_i)||(clr_idft_cntr)) begin
      idft_cntr = 0;
    end
    else if(inc_idft_cntr) begin
      idft_cntr = idft_cntr +1;
    end
  end
 
  assign step_o = step;
  assign mem_addr_o = mem_addr;
 
  // Controller State Machine  
  parameter INIT        = 5'b00000;
  parameter INPUT       = 5'b00001;
  parameter CALCSYND    = 5'b00010;
  parameter CALCDELTA1  = 5'b00011;
  parameter CALCDELTA2  = 5'b00100;
  parameter CALCBMSTEP1 = 5'b00101;
  parameter CALCBMSTEP2 = 5'b00110;
  parameter DONEBM      = 5'b00111;
  parameter CALCR0      = 5'b01000;
  parameter PUTZEROIDFT = 5'b01001;
  parameter MEMORY      = 5'b01010;
  parameter CALCRE      = 5'b01011;
  parameter LOADIDFT    = 5'b01100;
  parameter DATA0OUT    = 5'b01101;
  parameter CALCIDFT    = 5'b01110;
  parameter DONE        = 5'b01111;
 
  reg [4:0] cs,ns;
 
  // STATE TRANSITION BODY
  always @ (posedge clk_i) begin
    if (rst_i) begin
      cs <= INIT;
    end
    else begin
      cs <= ns;
    end
  end
 
  // Combination Body
  always @(*) begin
  case (cs)
    INIT: begin
      ns = INPUT;
 
      // output
      calc_S_0_o         = 0;
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      inc_mem_addr       = 0;
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      clr_input_cntr     = 1;
      clr_mem_addr       = 0;
      push_o             = 0;
      wren_o             = 0;
      mem_in_o           = 0;
      r_calc_sel_o       = 0;
      r_calc_o           = 0;
      busy_o             = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
    end
    INPUT: begin
      // At this state All the data is inputed
      if(input_cntr < 255) begin
        ns = INPUT;
      end
      else begin
        ns = CALCDELTA1;
      end
 
      // output
      if (valid_i) begin
        dft_calc_o       = 1;
        calc_S_0_o       = 1;
        dft_sel_o        = 2'b01;
      end
      else begin
        dft_calc_o       = 0;
        calc_S_0_o       = 0;
        dft_sel_o        = 2'b00;
      end
      inc_mem_addr       = 0;
 
      //used Not used 
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      done_dec_o         = 0;
      clr_input_cntr     = 0;
      clr_mem_addr       = 1;
      push_o             = 0;
      wren_o             = 0;
      mem_in_o           = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      busy_o             = 0;
      load_last_o        = 0;
 
 
      //un used
      valid_o_o          = 0;
      last_in_sel_o      = 0;
 
    end
    CALCSYND: begin
      ns = CALCDELTA1;
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 1;
      inc_mem_addr       = 1;
      wren_o             = 0;
      mem_in_o           = 1;
 
      // need to be trimmed 
      push_o             = 0;
 
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      done_dec_o         = 0;
      calc_S_0_o         = 0;
      valid_o_o          = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      clr_mem_addr       = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 1;
      // important signal 
      busy_o             = 1;
 
    end
    CALCDELTA1: begin
      ns = CALCDELTA2;
           // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      inc_mem_addr       = 0;
      en_fir_o           = 1;
 
      // The memory is written with first 16 syndroms
      wren_o             = 1;
      mem_in_o           = 1;
      push_o             = 0;
 
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      calc_S_0_o         = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      clr_mem_addr       = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 0;
      busy_o             = 1;
    end
    CALCDELTA2: begin
      ns = CALCBMSTEP1;
 
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      inc_mem_addr       = 0;
      en_fir_o           = 0;
 
      // why memmory is being written here
      wren_o             = 0;
      mem_in_o           = 0;
      push_o             = 0;
 
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      calc_S_0_o         = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      clr_mem_addr       = 0;
      load_last_o        = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 0;
      busy_o             = 1;
    end
 
    CALCBMSTEP1: begin
      ns = CALCBMSTEP2;
      // output
      calc_bm_step_o     = 1;
 
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      en_fir_o           = 0;
      inc_mem_addr       = 0;
      fir_sel_o          = 0;
      calc_S_0_o         = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      clr_mem_addr       = 0;
      push_o             = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      mem_in_o           = 0;
      wren_o             = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 0;
      busy_o             = 1;
 
    end
    CALCBMSTEP2: begin
      if (done_bm_step_i) begin
        if(step_o < 15) // 2*t-1
          ns = CALCSYND;
        else
          ns = DONEBM;
      end
      else begin
        ns = CALCBMSTEP2;
      end
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      inc_mem_addr       = 0;
      calc_S_0_o         = 0;
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      clr_mem_addr       = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      push_o             = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      mem_in_o           = 0;
      wren_o             = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 1;
      busy_o             = 1;
    end
    DONEBM: begin
      // important wait for the elp to complete inversion aswell
      if(elp_busy_i) begin
        ns = DONEBM;
        r_calc_o = 0;
        r_calc_sel_o= 0;
      end
      else begin
        ns = CALCR0;
        r_calc_o = 1;
        r_calc_sel_o= 1;
      end
 
      // output
      clr_mem_addr       = 0;
 
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      en_fir_o           = 0;
      calc_S_0_o         = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
 
      done_dec_o         = 0;
      valid_o_o          = 0;
      push_o             = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      inc_mem_addr       = 0;
      mem_in_o           = 0;
      wren_o             = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 1;
      busy_o             = 1;
    end
    CALCR0: begin
      if(r_calc_done_i) begin
        ns = MEMORY;
      end
      else begin
        ns = CALCR0;
      end
      // output
      r_calc_sel_o       = 1;
      r_calc_o           = 0;
 
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      en_fir_o           = 0;
      calc_S_0_o         = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
 
      done_dec_o         = 0;
      valid_o_o          = 0;
      push_o             = 0;
      inc_idft_cntr      = 0;
      clr_mem_addr       = 0;
      clr_idft_cntr      = 0;
      inc_mem_addr       = 0;
      mem_in_o           = 0;
      wren_o             = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
 
      clr_input_cntr     = 1;
      busy_o             = 1;
    end
    MEMORY: begin
      ns = CALCRE;
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 1; // calc_first DFT0
      fir_sel_o          = 1; // calc_first RE
      en_fir_o           = 1; // dont calc first RE
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      calc_bm_step_o     = 0;
 
      // Put data in Memmory
      clr_mem_addr       = 0;
      inc_mem_addr       = 0;
      wren_o             = 0;
      mem_in_o           = 0;
 
      done_dec_o         = 0;
 
      valid_o_o          = 0;
      push_o             = 0;
      load_last_o        = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      calc_S_0_o         = 0;
      last_in_sel_o      = 0;
 
      busy_o             = 1;
      clr_input_cntr     = 1;
 
    end
    CALCRE: begin
      if(mem_addr<255) begin
        ns = CALCRE;
        clr_mem_addr = 0;
      end
      else begin
        ns = PUTZEROIDFT;
        clr_mem_addr = 1;
      end
      // output
      // calculate remaining syndrome
      dft_sel_o          = 2'b00;
      dft_calc_o         = 1;
      // calculate r0 
      en_fir_o           = 1;
      fir_sel_o          = 1;
      inc_mem_addr       = 1;
      calc_S_0_o         = 0;
      load_last_o        = 1;
      wren_o             = 1;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      mem_in_o           = 0;
 
      // add syndrome and ro and put it in memmory
      //////////////////////
      inc_idft_cntr      = 0;
      push_o             = 0;
      clr_idft_cntr      = 0;
      calc_bm_step_o     = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      clr_input_cntr     = 0;
      last_in_sel_o      = 0;
      busy_o             = 1;
    end
 
    PUTZEROIDFT:begin
      if(mem_addr<15) begin
        ns = PUTZEROIDFT;
      end
      else begin
        ns = LOADIDFT;
      end
      // output
      dft_sel_o          = 2'b11;
      dft_calc_o         = 1;
      inc_mem_addr       = 1;
      // This signal is used to push zero in IDFT
      push_o             = 1;
 
      en_fir_o           = 0;
      inc_idft_cntr      = 0;
      clr_idft_cntr      = 0;
      calc_bm_step_o     = 0;
 
      wren_o             = 0;
      mem_in_o           = 0;
      clr_mem_addr       = 0;
      fir_sel_o          = 0;
 
      done_dec_o         = 0;
 
      valid_o_o          = 0;
      load_last_o        = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      calc_S_0_o         = 0;
      last_in_sel_o      = 0;
 
      busy_o             = 1;
      clr_input_cntr     = 1;
 
    end
    LOADIDFT: begin
      if(mem_addr<254) begin
        ns = LOADIDFT;
      end
      else begin
        ns = DATA0OUT;
      end
      // output
      dft_sel_o          = 2'b11;
      dft_calc_o         = 1;
      inc_mem_addr       = 1;
      clr_mem_addr       = 0;
      load_last_o        = 0;
      clr_idft_cntr      = 1;
 
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      inc_idft_cntr      = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      clr_input_cntr     = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      push_o             = 0;
      wren_o             = 0;
      mem_in_o           = 0;
      calc_S_0_o         = 0;
      last_in_sel_o      = 0;
 
      busy_o             = 1;
    end
    DATA0OUT: begin
      ns = CALCIDFT;
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      inc_mem_addr       = 0;
      clr_mem_addr       = 0;
      load_last_o        = 0;
      clr_idft_cntr      = 1;
 
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      inc_idft_cntr      = 0;
      done_dec_o         = 0;
      valid_o_o          = 1;
      clr_input_cntr     = 0;
      push_o             = 0;
      wren_o             = 0;
      mem_in_o           = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      calc_S_0_o         = 0;
      last_in_sel_o      = 1;
 
      busy_o             = 1;
    end
    CALCIDFT: begin
      if(idft_cntr<253) begin
        ns = CALCIDFT;
      end
      else begin
        ns = DONE;
      end
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 1;
      inc_mem_addr       = 0;
      clr_mem_addr       = 1;
      inc_idft_cntr      = 1;
      clr_idft_cntr      = 0;
      valid_o_o          = 1;
 
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      done_dec_o         = 0;
      clr_input_cntr     = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      push_o             = 0;
      wren_o             = 0;
      mem_in_o           = 0;
      load_last_o        = 0;
      calc_S_0_o         = 0;
      last_in_sel_o      = 0;
 
      busy_o             = 1;
    end
    DONE: begin
      ns = INIT;
      // output
      done_dec_o         = 1;
      clr_input_cntr     = 1;
      clr_mem_addr       = 1;
      clr_idft_cntr      = 1;
      busy_o             = 1;
 
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      inc_idft_cntr      = 0;
      valid_o_o          = 0;
      mem_in_o           = 0;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      push_o             = 0;
      wren_o             = 0;
      inc_mem_addr       = 0;
      load_last_o        = 0;
      calc_S_0_o         = 0;
      last_in_sel_o      = 0;
    end
    default: begin
      ns = INIT;
      // output
      dft_sel_o          = 2'b00;
      dft_calc_o         = 0;
      en_fir_o           = 0;
      fir_sel_o          = 0;
      calc_bm_step_o     = 0;
      inc_idft_cntr      = 0;
      done_dec_o         = 0;
      valid_o_o          = 0;
      clr_input_cntr     = 1;
      clr_mem_addr       = 1;
      clr_idft_cntr      = 1;
      r_calc_o           = 0;
      r_calc_sel_o       = 0;
      mem_in_o           = 0;
      push_o             = 0;
      wren_o             = 0;
      inc_mem_addr       = 0;
      load_last_o        = 0;
      last_in_sel_o      = 0;
      calc_S_0_o         = 0;
      busy_o             = 1;
 
    end
  endcase
  end
endmodule

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[/] [rs_encoder_decoder/] [rtl/] [RS8Controller.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	farooq21	`// This is a verilog File Generated`
2			`// By The C++ program That Generates`
3			`// Reed Solomon Controller`
4			`// Barlekamp Messay Controller`
5
6			`module RS8Controller(clk_i, rst_i,`
7			`valid_i, // Controller input valid`
8			`calc_S_0_o, // Control Signal to Calculate S_0`
9			`dft_sel_o, // select FFT or IFFT`
10			`dft_calc_o, // calculate fourier transform`
11			`mem_in_o, // memory control signal to input what in the memory`
12			`en_fir_o, // calculate new delta`
13			`fir_sel_o, // calculate new delta`
14			`calc_bm_step_o, // Calculate BM Step`
15			`step_o, // current_step`
16			`done_bm_step_i, // update from BM circuit`
17			`elp_busy_i, // Controller input busy signal from error loc poly`
18			`r_calc_o, // To enable R0 to calculate`
19			`r_calc_sel_o, // To enable R0 to select memmory address`
20			`r_calc_done_i, // When R0 has completed the operation`
21			`push_o, // push data in syndrom`
22			`mem_addr_o, // Memmory Address`
23			`load_last_o, // This is the first DFT calculation control signal`
24			`wren_o, // Write Data IN memmory`
25			`done_dec_o, // done BM decoding`
26			`last_in_sel_o, // ouput data 0`
27			`valid_o_o, // Asserted when data is being outputed from the RS decoder`
28			`busy_o // States the Status of the RS decoder`
29			`);`
30
31			`// Declaration of the inputs`
32			`input clk_i, rst_i;`
33			`input valid_i;`
34			`output reg dft_calc_o;`
35			`output reg [1:0] dft_sel_o;`
36			`output reg busy_o;`
37			`output reg en_fir_o;`
38			`output reg fir_sel_o;`
39			`output reg valid_o_o;`
40
41			`// Control Signals associated`
42			`output reg calc_S_0_o;`
43
44			`// with Error Loc Poly calculator`
45			`output reg calc_bm_step_o;`
46			`output wire [7:0] step_o;`
47			`input done_bm_step_i;`
48			`input elp_busy_i;`
49
50			`// R 0 calculator control signals`
51			`input r_calc_done_i; // When R0 has completed the operation`
52			`output reg r_calc_sel_o; // R0 memory address select`
53			`output reg r_calc_o; // to enable R0 to calculate`
54
55			`output reg push_o;`
56			`output reg done_dec_o;`
57
58			`// MEMORY ADDRESS AND MEMORY CONTROL SIGNALS`
59			`output wire [7:0] mem_addr_o;`
60			`output reg mem_in_o;`
61			`output reg wren_o;`
62
63
64			`output reg load_last_o;`
65			`output reg last_in_sel_o;`
66
67			`// Declaration of Wires And Register are here`
68			`// Control Registers`
69			`// INPUT COUNTER HANDLER`
70			`reg [8:0] input_cntr;`
71			`reg clr_input_cntr;`
72			`always @ (posedge clk_i) begin`
73			`if ((rst_i)\|\|(clr_input_cntr)) begin`
74			`input_cntr = 0;`
75			`end`
76			`else if ((valid_i)&& (~(busy_o))) begin`
77			`input_cntr = input_cntr + 1;`
78			`end`
79			`end`
80
81			`// ErrorPolyCalcStep`
82			`reg [7:0] step;`
83			`always @ (posedge clk_i) begin`
84			`if ((rst_i)\|\|(done_dec_o)) begin`
85			`step = 0;`
86			`end`
87			`else if (done_bm_step_i) begin`
88			`step = step + 1;`
89			`end`
90			`end`
91
92			`reg clr_mem_addr;`
93			`reg inc_mem_addr;`
94			`reg [7:0] mem_addr;`
95			`always @(posedge clk_i) begin`
96			`if((rst_i)\|\|(clr_mem_addr)) begin`
97			`mem_addr = 0;`
98			`end`
99			`else if(inc_mem_addr) begin`
100			`mem_addr = mem_addr +1;`
101			`end`
102			`end`
103
104			`reg inc_idft_cntr;`
105			`reg clr_idft_cntr;`
106			`reg [7:0] idft_cntr;`
107			`always @(posedge clk_i) begin`
108			`if((rst_i)\|\|(clr_idft_cntr)) begin`
109			`idft_cntr = 0;`
110			`end`
111			`else if(inc_idft_cntr) begin`
112			`idft_cntr = idft_cntr +1;`
113			`end`
114			`end`
115
116			`assign step_o = step;`
117			`assign mem_addr_o = mem_addr;`
118
119			`// Controller State Machine`
120			`parameter INIT = 5'b00000;`
121			`parameter INPUT = 5'b00001;`
122			`parameter CALCSYND = 5'b00010;`
123			`parameter CALCDELTA1 = 5'b00011;`
124			`parameter CALCDELTA2 = 5'b00100;`
125			`parameter CALCBMSTEP1 = 5'b00101;`
126			`parameter CALCBMSTEP2 = 5'b00110;`
127			`parameter DONEBM = 5'b00111;`
128			`parameter CALCR0 = 5'b01000;`
129			`parameter PUTZEROIDFT = 5'b01001;`
130			`parameter MEMORY = 5'b01010;`
131			`parameter CALCRE = 5'b01011;`
132			`parameter LOADIDFT = 5'b01100;`
133			`parameter DATA0OUT = 5'b01101;`
134			`parameter CALCIDFT = 5'b01110;`
135			`parameter DONE = 5'b01111;`
136
137			`reg [4:0] cs,ns;`
138
139			`// STATE TRANSITION BODY`
140			`always @ (posedge clk_i) begin`
141			`if (rst_i) begin`
142			`cs <= INIT;`
143			`end`
144			`else begin`
145			`cs <= ns;`
146			`end`
147			`end`
148
149			`// Combination Body`
150			`always @(*) begin`
151			`case (cs)`
152			`INIT: begin`
153			`ns = INPUT;`
154
155			`// output`
156			`calc_S_0_o = 0;`
157			`dft_sel_o = 2'b00;`
158			`dft_calc_o = 0;`
159			`inc_mem_addr = 0;`
160			`en_fir_o = 0;`
161			`fir_sel_o = 0;`
162			`calc_bm_step_o = 0;`
163			`done_dec_o = 0;`
164			`valid_o_o = 0;`
165			`inc_idft_cntr = 0;`
166			`clr_idft_cntr = 0;`
167			`clr_input_cntr = 1;`
168			`clr_mem_addr = 0;`
169			`push_o = 0;`
170			`wren_o = 0;`
171			`mem_in_o = 0;`
172			`r_calc_sel_o = 0;`
173			`r_calc_o = 0;`
174			`busy_o = 0;`
175			`load_last_o = 0;`
176			`last_in_sel_o = 0;`
177
178			`end`
179			`INPUT: begin`
180			`// At this state All the data is inputed`
181			`if(input_cntr < 255) begin`
182			`ns = INPUT;`
183			`end`
184			`else begin`
185			`ns = CALCDELTA1;`
186			`end`
187
188			`// output`
189			`if (valid_i) begin`
190			`dft_calc_o = 1;`
191			`calc_S_0_o = 1;`
192			`dft_sel_o = 2'b01;`
193			`end`
194			`else begin`
195			`dft_calc_o = 0;`
196			`calc_S_0_o = 0;`
197			`dft_sel_o = 2'b00;`
198			`end`
199			`inc_mem_addr = 0;`
200
201			`//used Not used`
202			`en_fir_o = 0;`
203			`fir_sel_o = 0;`
204			`calc_bm_step_o = 0;`
205			`inc_idft_cntr = 0;`
206			`clr_idft_cntr = 0;`
207			`done_dec_o = 0;`
208			`clr_input_cntr = 0;`
209			`clr_mem_addr = 1;`
210			`push_o = 0;`
211			`wren_o = 0;`
212			`mem_in_o = 0;`
213			`r_calc_o = 0;`
214			`r_calc_sel_o = 0;`
215			`busy_o = 0;`
216			`load_last_o = 0;`
217
218
219			`//un used`
220			`valid_o_o = 0;`
221			`last_in_sel_o = 0;`
222
223			`end`
224			`CALCSYND: begin`
225			`ns = CALCDELTA1;`
226			`// output`
227			`dft_sel_o = 2'b00;`
228			`dft_calc_o = 1;`
229			`inc_mem_addr = 1;`
230			`wren_o = 0;`
231			`mem_in_o = 1;`
232
233			`// need to be trimmed`
234			`push_o = 0;`
235
236			`inc_idft_cntr = 0;`
237			`clr_idft_cntr = 0;`
238			`en_fir_o = 0;`
239			`fir_sel_o = 0;`
240			`calc_bm_step_o = 0;`
241			`done_dec_o = 0;`
242			`calc_S_0_o = 0;`
243			`valid_o_o = 0;`
244			`r_calc_o = 0;`
245			`r_calc_sel_o = 0;`
246			`clr_mem_addr = 0;`
247			`load_last_o = 0;`
248			`last_in_sel_o = 0;`
249
250			`clr_input_cntr = 1;`
251			`// important signal`
252			`busy_o = 1;`
253
254			`end`
255			`CALCDELTA1: begin`
256			`ns = CALCDELTA2;`
257			`// output`
258			`dft_sel_o = 2'b00;`
259			`dft_calc_o = 0;`
260			`inc_mem_addr = 0;`
261			`en_fir_o = 1;`
262
263			`// The memory is written with first 16 syndroms`
264			`wren_o = 1;`
265			`mem_in_o = 1;`
266			`push_o = 0;`
267
268			`fir_sel_o = 0;`
269			`calc_bm_step_o = 0;`
270			`calc_S_0_o = 0;`
271			`inc_idft_cntr = 0;`
272			`clr_idft_cntr = 0;`
273			`done_dec_o = 0;`
274			`valid_o_o = 0;`
275			`r_calc_o = 0;`
276			`r_calc_sel_o = 0;`
277			`clr_mem_addr = 0;`
278			`load_last_o = 0;`
279			`last_in_sel_o = 0;`
280
281			`clr_input_cntr = 0;`
282			`busy_o = 1;`
283			`end`
284			`CALCDELTA2: begin`
285			`ns = CALCBMSTEP1;`
286
287			`// output`
288			`dft_sel_o = 2'b00;`
289			`dft_calc_o = 0;`
290			`inc_mem_addr = 0;`
291			`en_fir_o = 0;`
292
293			`// why memmory is being written here`
294			`wren_o = 0;`
295			`mem_in_o = 0;`
296			`push_o = 0;`
297
298			`fir_sel_o = 0;`
299			`calc_bm_step_o = 0;`
300			`calc_S_0_o = 0;`
301			`inc_idft_cntr = 0;`
302			`clr_idft_cntr = 0;`
303			`done_dec_o = 0;`
304			`valid_o_o = 0;`
305			`clr_mem_addr = 0;`
306			`load_last_o = 0;`
307			`r_calc_o = 0;`
308			`r_calc_sel_o = 0;`
309			`last_in_sel_o = 0;`
310
311			`clr_input_cntr = 0;`
312			`busy_o = 1;`
313			`end`
314
315			`CALCBMSTEP1: begin`
316			`ns = CALCBMSTEP2;`
317			`// output`
318			`calc_bm_step_o = 1;`
319
320			`dft_sel_o = 2'b00;`
321			`dft_calc_o = 0;`
322			`inc_idft_cntr = 0;`
323			`clr_idft_cntr = 0;`
324			`en_fir_o = 0;`
325			`inc_mem_addr = 0;`
326			`fir_sel_o = 0;`
327			`calc_S_0_o = 0;`
328			`done_dec_o = 0;`
329			`valid_o_o = 0;`
330			`clr_mem_addr = 0;`
331			`push_o = 0;`
332			`r_calc_o = 0;`
333			`r_calc_sel_o = 0;`
334			`mem_in_o = 0;`
335			`wren_o = 0;`
336			`load_last_o = 0;`
337			`last_in_sel_o = 0;`
338
339			`clr_input_cntr = 0;`
340			`busy_o = 1;`
341
342			`end`
343			`CALCBMSTEP2: begin`
344			`if (done_bm_step_i) begin`
345			`if(step_o < 15) // 2*t-1`
346			`ns = CALCSYND;`
347			`else`
348			`ns = DONEBM;`
349			`end`
350			`else begin`
351			`ns = CALCBMSTEP2;`
352			`end`
353			`// output`
354			`dft_sel_o = 2'b00;`
355			`dft_calc_o = 0;`
356			`inc_mem_addr = 0;`
357			`calc_S_0_o = 0;`
358			`en_fir_o = 0;`
359			`fir_sel_o = 0;`
360			`calc_bm_step_o = 0;`
361			`done_dec_o = 0;`
362			`valid_o_o = 0;`
363			`clr_mem_addr = 0;`
364			`inc_idft_cntr = 0;`
365			`clr_idft_cntr = 0;`
366			`push_o = 0;`
367			`r_calc_o = 0;`
368			`r_calc_sel_o = 0;`
369			`mem_in_o = 0;`
370			`wren_o = 0;`
371			`load_last_o = 0;`
372			`last_in_sel_o = 0;`
373
374			`clr_input_cntr = 1;`
375			`busy_o = 1;`
376			`end`
377			`DONEBM: begin`
378			`// important wait for the elp to complete inversion aswell`
379			`if(elp_busy_i) begin`
380			`ns = DONEBM;`
381			`r_calc_o = 0;`
382			`r_calc_sel_o= 0;`
383			`end`
384			`else begin`
385			`ns = CALCR0;`
386			`r_calc_o = 1;`
387			`r_calc_sel_o= 1;`
388			`end`
389
390			`// output`
391			`clr_mem_addr = 0;`
392
393			`dft_sel_o = 2'b00;`
394			`dft_calc_o = 0;`
395			`en_fir_o = 0;`
396			`calc_S_0_o = 0;`
397			`fir_sel_o = 0;`
398			`calc_bm_step_o = 0;`
399
400			`done_dec_o = 0;`
401			`valid_o_o = 0;`
402			`push_o = 0;`
403			`inc_idft_cntr = 0;`
404			`clr_idft_cntr = 0;`
405			`inc_mem_addr = 0;`
406			`mem_in_o = 0;`
407			`wren_o = 0;`
408			`load_last_o = 0;`
409			`last_in_sel_o = 0;`
410
411			`clr_input_cntr = 1;`
412			`busy_o = 1;`
413			`end`
414			`CALCR0: begin`
415			`if(r_calc_done_i) begin`
416			`ns = MEMORY;`
417			`end`
418			`else begin`
419			`ns = CALCR0;`
420			`end`
421			`// output`
422			`r_calc_sel_o = 1;`
423			`r_calc_o = 0;`
424
425			`dft_sel_o = 2'b00;`
426			`dft_calc_o = 0;`
427			`en_fir_o = 0;`
428			`calc_S_0_o = 0;`
429			`fir_sel_o = 0;`
430			`calc_bm_step_o = 0;`
431
432			`done_dec_o = 0;`
433			`valid_o_o = 0;`
434			`push_o = 0;`
435			`inc_idft_cntr = 0;`
436			`clr_mem_addr = 0;`
437			`clr_idft_cntr = 0;`
438			`inc_mem_addr = 0;`
439			`mem_in_o = 0;`
440			`wren_o = 0;`
441			`load_last_o = 0;`
442			`last_in_sel_o = 0;`
443
444			`clr_input_cntr = 1;`
445			`busy_o = 1;`
446			`end`
447			`MEMORY: begin`
448			`ns = CALCRE;`
449			`// output`
450			`dft_sel_o = 2'b00;`
451			`dft_calc_o = 1; // calc_first DFT0`
452			`fir_sel_o = 1; // calc_first RE`
453			`en_fir_o = 1; // dont calc first RE`
454			`inc_idft_cntr = 0;`
455			`clr_idft_cntr = 0;`
456			`calc_bm_step_o = 0;`
457
458			`// Put data in Memmory`
459			`clr_mem_addr = 0;`
460			`inc_mem_addr = 0;`
461			`wren_o = 0;`
462			`mem_in_o = 0;`
463
464			`done_dec_o = 0;`
465
466			`valid_o_o = 0;`
467			`push_o = 0;`
468			`load_last_o = 0;`
469			`r_calc_o = 0;`
470			`r_calc_sel_o = 0;`
471			`calc_S_0_o = 0;`
472			`last_in_sel_o = 0;`
473
474			`busy_o = 1;`
475			`clr_input_cntr = 1;`
476
477			`end`
478			`CALCRE: begin`
479			`if(mem_addr<255) begin`
480			`ns = CALCRE;`
481			`clr_mem_addr = 0;`
482			`end`
483			`else begin`
484			`ns = PUTZEROIDFT;`
485			`clr_mem_addr = 1;`
486			`end`
487			`// output`
488			`// calculate remaining syndrome`
489			`dft_sel_o = 2'b00;`
490			`dft_calc_o = 1;`
491			`// calculate r0`
492			`en_fir_o = 1;`
493			`fir_sel_o = 1;`
494			`inc_mem_addr = 1;`
495			`calc_S_0_o = 0;`
496			`load_last_o = 1;`
497			`wren_o = 1;`
498			`r_calc_o = 0;`
499			`r_calc_sel_o = 0;`
500			`mem_in_o = 0;`
501
502			`// add syndrome and ro and put it in memmory`
503			`//////////////////////`
504			`inc_idft_cntr = 0;`
505			`push_o = 0;`
506			`clr_idft_cntr = 0;`
507			`calc_bm_step_o = 0;`
508			`done_dec_o = 0;`
509			`valid_o_o = 0;`
510			`clr_input_cntr = 0;`
511			`last_in_sel_o = 0;`
512			`busy_o = 1;`
513			`end`
514
515			`PUTZEROIDFT:begin`
516			`if(mem_addr<15) begin`
517			`ns = PUTZEROIDFT;`
518			`end`
519			`else begin`
520			`ns = LOADIDFT;`
521			`end`
522			`// output`
523			`dft_sel_o = 2'b11;`
524			`dft_calc_o = 1;`
525			`inc_mem_addr = 1;`
526			`// This signal is used to push zero in IDFT`
527			`push_o = 1;`
528
529			`en_fir_o = 0;`
530			`inc_idft_cntr = 0;`
531			`clr_idft_cntr = 0;`
532			`calc_bm_step_o = 0;`
533
534			`wren_o = 0;`
535			`mem_in_o = 0;`
536			`clr_mem_addr = 0;`
537			`fir_sel_o = 0;`
538
539			`done_dec_o = 0;`
540
541			`valid_o_o = 0;`
542			`load_last_o = 0;`
543			`r_calc_o = 0;`
544			`r_calc_sel_o = 0;`
545			`calc_S_0_o = 0;`
546			`last_in_sel_o = 0;`
547
548			`busy_o = 1;`
549			`clr_input_cntr = 1;`
550
551			`end`
552			`LOADIDFT: begin`
553			`if(mem_addr<254) begin`
554			`ns = LOADIDFT;`
555			`end`
556			`else begin`
557			`ns = DATA0OUT;`
558			`end`
559			`// output`
560			`dft_sel_o = 2'b11;`
561			`dft_calc_o = 1;`
562			`inc_mem_addr = 1;`
563			`clr_mem_addr = 0;`
564			`load_last_o = 0;`
565			`clr_idft_cntr = 1;`
566
567			`en_fir_o = 0;`
568			`fir_sel_o = 0;`
569			`calc_bm_step_o = 0;`
570			`inc_idft_cntr = 0;`
571			`done_dec_o = 0;`
572			`valid_o_o = 0;`
573			`clr_input_cntr = 0;`
574			`r_calc_o = 0;`
575			`r_calc_sel_o = 0;`
576			`push_o = 0;`
577			`wren_o = 0;`
578			`mem_in_o = 0;`
579			`calc_S_0_o = 0;`
580			`last_in_sel_o = 0;`
581
582			`busy_o = 1;`
583			`end`
584			`DATA0OUT: begin`
585			`ns = CALCIDFT;`
586			`// output`
587			`dft_sel_o = 2'b00;`
588			`dft_calc_o = 0;`
589			`inc_mem_addr = 0;`
590			`clr_mem_addr = 0;`
591			`load_last_o = 0;`
592			`clr_idft_cntr = 1;`
593
594			`en_fir_o = 0;`
595			`fir_sel_o = 0;`
596			`calc_bm_step_o = 0;`
597			`inc_idft_cntr = 0;`
598			`done_dec_o = 0;`
599			`valid_o_o = 1;`
600			`clr_input_cntr = 0;`
601			`push_o = 0;`
602			`wren_o = 0;`
603			`mem_in_o = 0;`
604			`r_calc_o = 0;`
605			`r_calc_sel_o = 0;`
606			`calc_S_0_o = 0;`
607			`last_in_sel_o = 1;`
608
609			`busy_o = 1;`
610			`end`
611			`CALCIDFT: begin`
612			`if(idft_cntr<253) begin`
613			`ns = CALCIDFT;`
614			`end`
615			`else begin`
616			`ns = DONE;`
617			`end`
618			`// output`
619			`dft_sel_o = 2'b00;`
620			`dft_calc_o = 1;`
621			`inc_mem_addr = 0;`
622			`clr_mem_addr = 1;`
623			`inc_idft_cntr = 1;`
624			`clr_idft_cntr = 0;`
625			`valid_o_o = 1;`
626
627			`en_fir_o = 0;`
628			`fir_sel_o = 0;`
629			`calc_bm_step_o = 0;`
630			`done_dec_o = 0;`
631			`clr_input_cntr = 0;`
632			`r_calc_o = 0;`
633			`r_calc_sel_o = 0;`
634			`push_o = 0;`
635			`wren_o = 0;`
636			`mem_in_o = 0;`
637			`load_last_o = 0;`
638			`calc_S_0_o = 0;`
639			`last_in_sel_o = 0;`
640
641			`busy_o = 1;`
642			`end`
643			`DONE: begin`
644			`ns = INIT;`
645			`// output`
646			`done_dec_o = 1;`
647			`clr_input_cntr = 1;`
648			`clr_mem_addr = 1;`
649			`clr_idft_cntr = 1;`
650			`busy_o = 1;`
651
652			`dft_sel_o = 2'b00;`
653			`dft_calc_o = 0;`
654			`en_fir_o = 0;`
655			`fir_sel_o = 0;`
656			`calc_bm_step_o = 0;`
657			`inc_idft_cntr = 0;`
658			`valid_o_o = 0;`
659			`mem_in_o = 0;`
660			`r_calc_o = 0;`
661			`r_calc_sel_o = 0;`
662			`push_o = 0;`
663			`wren_o = 0;`
664			`inc_mem_addr = 0;`
665			`load_last_o = 0;`
666			`calc_S_0_o = 0;`
667			`last_in_sel_o = 0;`
668			`end`
669			`default: begin`
670			`ns = INIT;`
671			`// output`
672			`dft_sel_o = 2'b00;`
673			`dft_calc_o = 0;`
674			`en_fir_o = 0;`
675			`fir_sel_o = 0;`
676			`calc_bm_step_o = 0;`
677			`inc_idft_cntr = 0;`
678			`done_dec_o = 0;`
679			`valid_o_o = 0;`
680			`clr_input_cntr = 1;`
681			`clr_mem_addr = 1;`
682			`clr_idft_cntr = 1;`
683			`r_calc_o = 0;`
684			`r_calc_sel_o = 0;`
685			`mem_in_o = 0;`
686			`push_o = 0;`
687			`wren_o = 0;`
688			`inc_mem_addr = 0;`
689			`load_last_o = 0;`
690			`last_in_sel_o = 0;`
691			`calc_S_0_o = 0;`
692			`busy_o = 1;`
693
694			`end`
695			`endcase`
696			`end`
697			`endmodule`