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farooq21 |
// This is a verilog File Generated
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// By The C++ program That Generates
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// Reed Solomon Controller
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// Barlekamp Messay Controller
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module RS8FreqDecode(clk_i, rst_i,
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valid_i, // input valid signal
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enc_data_i, // encoded data
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dec_data_o, // decoded output
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valid_o, // decoded output
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busy_o
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);
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// Declaration of the inputs
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input clk_i, rst_i;
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input valid_i;
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input [7:0] enc_data_i;
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output wire [7:0] dec_data_o;
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output wire valid_o;
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output wire busy_o;
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// Declaration of Wires And Register are here
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// Control Signal To Calculate S_0
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wire calc_S_0;
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// Control signals To Calculate fourier transforms
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wire [1:0] dft_sel; // select signal tells to calculate DFT or IDFT
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wire dft_calc; // enable signal
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// Control Signal to Calculate DELTA;
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wire en_fir;
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wire fir_sel;
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// Control Signal for errolocpoly;
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wire calc_bm_step;
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wire [7:0] step;
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wire done_bm_step;
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wire push_zero;
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// MEMORY CONTROL SIGNAL
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wire wren;
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wire [7:0] mem_address;
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wire busy;
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// MEMORY DATA SIGNAL
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wire [7:0] mem_data;
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// IDFT Zero Value CONTROL SIGNALS
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wire load_last;
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wire load_sel_out;
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wire done_dec;
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// Data Signal
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wire [71:0] sigma; // original error loc poly
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wire [71:0] sigma_0; // error loc poly with shifted right 8 bit and inv(sigma(0)) in the end
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wire [71:0] sigma_last; // error loc poly with sigma(0) inversed
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wire [71:0] fir_i_sigma;
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wire [7:0] synd;
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wire [7:0] fir_o;
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wire [7:0] add_res;
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wire [7:0] dft_all_in;
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wire [7:0] dft_in;
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wire [7:0] mem_data_o;
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// R 0 Calculator Signals
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wire [7:0] mem_loc; // mem address from the R_0 module is enabled when r_calc_sel is set to high
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wire r_calc_sel; // R_0_calculate Control signal from the controller to select R0 memmory address
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wire r_calc_done; // R_0_calculate control signal to the controller
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wire r_calc; // enable signal to calculate R0
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// R 0 Data signals
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wire [7:0] R_0;
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// Registers
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reg [7:0] delta;
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reg [7:0] last_in;
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reg [7:0] S_0;
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// mem address and control signal from the controler
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wire [7:0] mem_addr;
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wire mem_in;
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assign busy_o = busy;
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assign add_res = delta^synd;
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// Decoder output
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assign dec_data_o = load_sel_out?last_in:synd;
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// MUX TO INPUT SIGMA OR SIGMA_O DEPENDING ON OPERATION
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assign fir_i_sigma = fir_sel ? sigma_0: sigma;
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// MUX FOR THE INPUT OF DFT_IDFT BLOCK
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assign dft_in = dft_sel[1] ? mem_data_o:enc_data_i;
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assign dft_all_in = push_zero ? 8'b00000000:dft_in;
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// MEMORY MUXES
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assign mem_address = r_calc_sel ? mem_loc:mem_addr;
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assign mem_data = mem_in ? synd:add_res; //input first 16 syndrom of add_res
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// SEQUENTIAL BODY
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always @(posedge clk_i) begin
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if((rst_i)||(done_dec))begin
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S_0 <= 0;
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end
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else if (calc_S_0) begin
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S_0 <= S_0^enc_data_i;
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end
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end
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always @(posedge clk_i) begin
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if((rst_i)||(done_dec))begin
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last_in <= 0;
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end
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else if (load_last) begin
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last_in <= last_in^add_res;
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end
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end
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always @(posedge clk_i) begin
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if ((rst_i)||(done_dec))
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delta <= 0;
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else
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delta <= fir_o;
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end
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// STRUCTURAL MODEL OF RS DECODER
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// MEMORY EVALUALTOR
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Memmory EVALMEM(
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.clk (clk_i),
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.addr (mem_address),
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.data (mem_data),
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.we (wren),
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.q ( mem_data_o )
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);
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GF8Dft_Idft DFTIDFT(.clk_i(clk_i), .rst_i(rst_i),
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.dft_sel_i(dft_sel[0]), // Control Signal calculates dft if dft_idft = 0 else idft if dft_idft = 1
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.en_i(dft_calc), // Control Signal
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.dft_i(dft_all_in), // Gallios Field Register input 1
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.dft_o(synd) // Gallios Field Register output
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);
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RS8Controller CNTRLER(.clk_i(clk_i),.rst_i(rst_i),
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.valid_i(valid_i), // Controller input valid
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.calc_S_0_o(calc_S_0), // Control Signal to Calculate S_0
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.dft_sel_o(dft_sel), // select FFT or IFFT
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.dft_calc_o(dft_calc), // calculate fourier transform
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.mem_in_o(mem_in), // memory data selection control signal
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.en_fir_o(en_fir), // calculate new delta
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.fir_sel_o(fir_sel), // calculate new delta
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.calc_bm_step_o(calc_bm_step), // Calculate BM Step
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.step_o(step), // current_step
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.done_bm_step_i(done_bm_step), // update from BM circuit
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.elp_busy_i(elp_busy), // Controller input busy signal from error loc poly
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.r_calc_o(r_calc), // TO Enable R0 calculator
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.r_calc_sel_o(r_calc_sel), // To selsect R0 MEMORY ADDRESS
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.r_calc_done_i(r_calc_done), // When R0 has completed the operation
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.push_o(push_zero), // push data in syndrom
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.mem_addr_o(mem_addr), // Memmory Address
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.wren_o(wren), // Write Data IN memmory
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.load_last_o(load_last), // Load Last
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.last_in_sel_o(load_sel_out), // ouput data 0
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.valid_o_o(valid_o), // Output from the Decode
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.busy_o(busy), // Output from the Decoder
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.done_dec_o(done_dec) // When The Complete Decoding is done
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);
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RS8ErrLocPoly8t CALCERRLOCPOLY(.clk_i(clk_i),.rst_i(rst_i),
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.valid_i(calc_bm_step), // input 1
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.delta_i(delta), // input 1
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.step_i(step), // input 1
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.done_dec_i(done_dec), // input 1
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.valid_o(done_bm_step), // output
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.sigma_0_o(sigma_0), // output
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.sigma_o(sigma), // output
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.sigma_last_o(sigma_last), // output
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.busy_o(elp_busy) // Busy signal indication for processing
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);
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GF8Fir8t CALCDELTARE(
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.clk_i(clk_i),.rst_i(rst_i),
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.en_i(en_fir), // Gallios Field FIR Filter enable 1
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.fir_i(synd), // Gallios Field FIR Filter input 1
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.sel_i(fir_sel), // Gallios Field FIR Filter input 1
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.coeff_i(fir_i_sigma), // Gallios Field FIR Coefficient input 1
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.fir_o(fir_o), // Gallios Field FIR out
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.done_dec_i(done_dec) // This is to clear every thing in this module
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);
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RS8CALCR08 R0CALC(.clk_i(clk_i), .rst_i(rst_i),
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.en_i(r_calc), // Enable Signal
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.sigma_i(sigma_last), // sigma value in to calculate R0
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.syndrom_i(mem_data_o), // Syndrom value from the memory
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.loc_o(mem_loc), // mem_address
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.R_0_o(R_0), // Valid R_o when valid_o == 1
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.valid_o(r_calc_done), // When processing done
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.done_dec_i(done_dec) // input to clear all the registers
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);
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endmodule
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