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[/] [rsa_512/] [trunk/] [bench/] [test_512.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------- 
-- Company:  
-- Engineer: 
-- 
-- Create Date:   17:40:28 12/13/2009 
-- Design Name:    
-- Module Name:   
-- Project Name:  ciosspartan 
-- Target Device:   
-- Tool versions:   
-- Description:    
--  
-- VHDL Test Bench Created by ISE for module: rsa_top 
--  
-- Dependencies: 
--  
-- Revision: 
-- Revision 0.01 - File Created 
-- Additional Comments: 
-- 
-- Notes:  
-- This testbench has been automatically generated using types std_logic and 
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation  
-- simulation model. 
-------------------------------------------------------------------------------- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity test_rsa_512 is
end test_rsa_512;
 
architecture behavior of test_rsa_512 is
 
  -- Component Declaration for the Unit Under Test (UUT) 
 
  component rsa_top
    port(
      clk       : in  std_logic;
      reset     : in  std_logic;
      valid_in  : in  std_logic;
      x         : in  std_logic_vector(15 downto 0);
      y         : in  std_logic_vector(15 downto 0);
      m         : in  std_logic_vector(15 downto 0);
      r_c       : in  std_logic_vector(15 downto 0);
      n_c       : in  std_logic_vector(15 downto 0);
      s         : out std_logic_vector(15 downto 0);
      valid_out : out std_logic;
      bit_size  : in  std_logic_vector(15 downto 0)
      );
  end component;
 
 
  --Inputs 
  signal clk       : std_logic                     := '0';
  signal reset     : std_logic                     := '0';
  signal valid_in  : std_logic                     := '0';
  signal x         : std_logic_vector(15 downto 0) := (others => '0');
  signal y         : std_logic_vector(15 downto 0) := (others => '0');
  signal m         : std_logic_vector(15 downto 0) := (others => '0');
  signal r_c       : std_logic_vector(15 downto 0) := (others => '0');
  signal n_c       : std_logic_vector(15 downto 0) := (others => '0');
  signal bit_size  : std_logic_vector(15 downto 0) := x"0200";
  --Outputs 
  signal s         : std_logic_vector(15 downto 0);
  signal valid_out : std_logic;
 
  -- Clock period definitions 
  constant clk_period : time := 1ns;
 
begin
 
  -- Instantiate the Unit Under Test (UUT) 
  uut : rsa_top port map (
    clk       => clk,
    reset     => reset,
    valid_in  => valid_in,
    x         => x,
    y         => y,
    m         => m,
    r_c       => r_c,
    n_c       => n_c,
    s         => s,
    valid_out => valid_out,
    bit_size  => bit_size
    );
 
  -- Clock process definitions 
  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;
 
 
  -- Stimulus process 
  stim_proc : process
  begin
    valid_in <= '0';
    -- hold reset state for 100ms. 
    reset    <= '1';
    wait for 10ns;
    reset    <= '0';
    wait for clk_period*10;
 
    -- insert stimulus here  
 
--n_c and valid signal and the r_c constant are also required
    n_c      <= x"738f";
    valid_in <= '1';
    x        <= x"f3ad";
    y        <= x"42b1";
    m        <= x"b491";
    r_c      <= x"f579";
    wait for clk_period;
    x        <= x"8e40";
    y        <= x"1ad3";
    m        <= x"1417";
    r_c      <= x"6ee9";
    wait for clk_period;
    x        <= x"6af9";
    y        <= x"a827";
    m        <= x"b498";
    r_c      <= x"972d";
    wait for clk_period;
    x        <= x"4e63";
    y        <= x"0d64";
    m        <= x"e1b7";
    r_c      <= x"5052";
    wait for clk_period;
    x        <= x"9600";
    y        <= x"3f76";
    m        <= x"e47c";
    r_c      <= x"1dca";
    wait for clk_period;
    x        <= x"68f4";
    y        <= x"6670";
    m        <= x"b186";
    r_c      <= x"bc81";
    wait for clk_period;
    x        <= x"5a12";
    y        <= x"5a1c";
    m        <= x"93f0";
    r_c      <= x"377e";
    wait for clk_period;
    x        <= x"d62e";
    y        <= x"4844";
    m        <= x"b183";
    r_c      <= x"04ef";
    wait for clk_period;
    x        <= x"8fc1";
    y        <= x"d5f2";
    m        <= x"f8f1";
    r_c      <= x"3a2a";
    wait for clk_period;
    x        <= x"031d";
    y        <= x"b65a";
    m        <= x"eed1";
    r_c      <= x"291b";
    wait for clk_period;
    x        <= x"f496";
    y        <= x"034f";
    m        <= x"0083";
    r_c      <= x"c159";
    wait for clk_period;
    x        <= x"1268";
    y        <= x"9635";
    m        <= x"981c";
    r_c      <= x"9336";
    wait for clk_period;
    x        <= x"2e5a";
    y        <= x"386e";
    m        <= x"6441";
    r_c      <= x"1bd0";
    wait for clk_period;
    x        <= x"c1d6";
    y        <= x"fb73";
    m        <= x"fcd8";
    r_c      <= x"317d";
    wait for clk_period;
    x        <= x"cd8f";
    y        <= x"5623";
    m        <= x"cbf0";
    r_c      <= x"64b4";
    wait for clk_period;
    x        <= x"e4d2";
    y        <= x"9041";
    m        <= x"e3ca";
    r_c      <= x"8793";
    wait for clk_period;
    x        <= x"36c6";
    y        <= x"99da";
    m        <= x"41d9";
    r_c      <= x"85f5";
    wait for clk_period;
    x        <= x"df4a";
    y        <= x"cd68";
    m        <= x"b7a0";
    r_c      <= x"7c8d";
    wait for clk_period;
    x        <= x"8e40";
    y        <= x"9a94";
    m        <= x"146e";
    r_c      <= x"64d9";
    wait for clk_period;
    x        <= x"6af9";
    y        <= x"ccc8";
    m        <= x"4776";
    r_c      <= x"c7f6";
    wait for clk_period;
    x        <= x"4e63";
    y        <= x"ed49";
    m        <= x"ec50";
    r_c      <= x"fba0";
    wait for clk_period;
    x        <= x"9600";
    y        <= x"4d25";
    m        <= x"c07c";
    r_c      <= x"e3e0";
    wait for clk_period;
    x        <= x"68f4";
    y        <= x"3b8e";
    m        <= x"e698";
    r_c      <= x"b567";
    wait for clk_period;
    x        <= x"5a12";
    y        <= x"36d5";
    m        <= x"d85f";
    r_c      <= x"3172";
    wait for clk_period;
    x        <= x"d62e";
    y        <= x"3a75";
    m        <= x"729c";
    r_c      <= x"111a";
    wait for clk_period;
    x        <= x"8fc1";
    y        <= x"77a3";
    m        <= x"19b6";
    r_c      <= x"1971";
    wait for clk_period;
    x        <= x"d2cd";
    y        <= x"367f";
    m        <= x"05d3";
    r_c      <= x"9f9b";
    wait for clk_period;
    x        <= x"c6e4";
    y        <= x"68de";
    m        <= x"cacd";
    r_c      <= x"b574";
    wait for clk_period;
    x        <= x"4a36";
    y        <= x"59a4";
    m        <= x"e16f";
    r_c      <= x"4a50";
    wait for clk_period;
    x        <= x"f6df";
    y        <= x"9f89";
    m        <= x"f67b";
    r_c      <= x"6d56";
    wait for clk_period;
    x        <= x"061c";
    y        <= x"ed71";
    m        <= x"7066";
    r_c      <= x"bdc6";
    wait for clk_period;
    x        <= x"06c8";
    y        <= x"059f";
    m        <= x"08de";
    r_c      <= x"0400";
    wait for clk_period;
    valid_in <= '0';
 
--valid_in <='0';
    wait for clk_period*200000;
 
    --Now with the public key x"10001"; 
 
    bit_size <= x"0011";
    valid_in <= '1';
    x        <= x"f3ad";
    y        <= x"0001";
    m        <= x"b491";
    r_c      <= x"f579";
    wait for clk_period;
    x        <= x"8e40";
    y        <= x"0001";
    m        <= x"1417";
    r_c      <= x"6ee9";
    wait for clk_period;
    x        <= x"6af9";
    y        <= x"0000";
    m        <= x"b498";
    r_c      <= x"972d";
    wait for clk_period;
    x        <= x"4e63";
    m        <= x"e1b7";
    r_c      <= x"5052";
    wait for clk_period;
    x        <= x"9600";
    m        <= x"e47c";
    r_c      <= x"1dca";
    wait for clk_period;
    x        <= x"68f4";
    m        <= x"b186";
    r_c      <= x"bc81";
    wait for clk_period;
    x        <= x"5a12";
    m        <= x"93f0";
    r_c      <= x"377e";
    wait for clk_period;
    x        <= x"d62e";
    m        <= x"b183";
    r_c      <= x"04ef";
    wait for clk_period;
    x        <= x"8fc1";
    m        <= x"f8f1";
    r_c      <= x"3a2a";
    wait for clk_period;
    x        <= x"031d";
    m        <= x"eed1";
    r_c      <= x"291b";
    wait for clk_period;
    x        <= x"f496";
    m        <= x"0083";
    r_c      <= x"c159";
    wait for clk_period;
    x        <= x"1268";
 
    m   <= x"981c";
    r_c <= x"9336";
    wait for clk_period;
    x   <= x"2e5a";
 
    m   <= x"6441";
    r_c <= x"1bd0";
    wait for clk_period;
    x   <= x"c1d6";
 
    m   <= x"fcd8";
    r_c <= x"317d";
    wait for clk_period;
    x   <= x"cd8f";
 
    m   <= x"cbf0";
    r_c <= x"64b4";
    wait for clk_period;
    x   <= x"e4d2";
 
    m   <= x"e3ca";
    r_c <= x"8793";
    wait for clk_period;
    x   <= x"36c6";
 
    m   <= x"41d9";
    r_c <= x"85f5";
    wait for clk_period;
    x   <= x"df4a";
 
    m   <= x"b7a0";
    r_c <= x"7c8d";
    wait for clk_period;
    x   <= x"8e40";
 
    m   <= x"146e";
    r_c <= x"64d9";
    wait for clk_period;
    x   <= x"6af9";
 
    m   <= x"4776";
    r_c <= x"c7f6";
    wait for clk_period;
    x   <= x"4e63";
 
    m   <= x"ec50";
    r_c <= x"fba0";
    wait for clk_period;
    x   <= x"9600";
 
    m   <= x"c07c";
    r_c <= x"e3e0";
    wait for clk_period;
    x   <= x"68f4";
 
    m   <= x"e698";
    r_c <= x"b567";
    wait for clk_period;
    x   <= x"5a12";
 
    m   <= x"d85f";
    r_c <= x"3172";
    wait for clk_period;
    x   <= x"d62e";
 
    m   <= x"729c";
    r_c <= x"111a";
    wait for clk_period;
    x   <= x"8fc1";
 
    m   <= x"19b6";
    r_c <= x"1971";
    wait for clk_period;
    x   <= x"d2cd";
 
    m   <= x"05d3";
    r_c <= x"9f9b";
    wait for clk_period;
    x <= x"c6e4";
 
    m <= x"cacd";
    r_c <= x"b574";
    wait for clk_period;
    x <= x"4a36";
 
    m <= x"e16f";
    r_c <= x"4a50";
    wait for clk_period;
    x <= x"f6df";
 
    m <= x"f67b";
    r_c <= x"6d56";
    wait for clk_period;
    x <= x"061c";
 
    m <= x"7066";
    r_c <= x"bdc6";
    wait for clk_period;
    x <= x"06c8";
 
    m <= x"08de";
    r_c <= x"0400";
    wait for clk_period;
    valid_in <= '0';
 
    wait;
  end process;
 
END;

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Subversion Repositories rsa_512

[/] [rsa_512/] [trunk/] [bench/] [test_512.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	jcastillo	`--------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 17:40:28 12/13/2009`
6			`-- Design Name:`
7			`-- Module Name:`
8			`-- Project Name: ciosspartan`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- VHDL Test Bench Created by ISE for module: rsa_top`
14			`--`
15			`-- Dependencies:`
16			`--`
17			`-- Revision:`
18			`-- Revision 0.01 - File Created`
19			`-- Additional Comments:`
20			`--`
21			`-- Notes:`
22			`-- This testbench has been automatically generated using types std_logic and`
23			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
24			`-- that these types always be used for the top-level I/O of a design in order`
25			`-- to guarantee that the testbench will bind correctly to the post-implementation`
26			`-- simulation model.`
27			`--------------------------------------------------------------------------------`
28			`library ieee;`
29			`use ieee.std_logic_1164.all;`
30			`use ieee.std_logic_unsigned.all;`
31			`use ieee.numeric_std.all;`
32
33			`entity test_rsa_512 is`
34			`end test_rsa_512;`
35
36			`architecture behavior of test_rsa_512 is`
37
38			`-- Component Declaration for the Unit Under Test (UUT)`
39
40			`component rsa_top`
41			`port(`
42			`clk : in std_logic;`
43			`reset : in std_logic;`
44			`valid_in : in std_logic;`
45			`x : in std_logic_vector(15 downto 0);`
46			`y : in std_logic_vector(15 downto 0);`
47			`m : in std_logic_vector(15 downto 0);`
48			`r_c : in std_logic_vector(15 downto 0);`
49			`n_c : in std_logic_vector(15 downto 0);`
50			`s : out std_logic_vector(15 downto 0);`
51			`valid_out : out std_logic;`
52			`bit_size : in std_logic_vector(15 downto 0)`
53			`);`
54			`end component;`
55
56
57			`--Inputs`
58			`signal clk : std_logic := '0';`
59			`signal reset : std_logic := '0';`
60			`signal valid_in : std_logic := '0';`
61			`signal x : std_logic_vector(15 downto 0) := (others => '0');`
62			`signal y : std_logic_vector(15 downto 0) := (others => '0');`
63			`signal m : std_logic_vector(15 downto 0) := (others => '0');`
64			`signal r_c : std_logic_vector(15 downto 0) := (others => '0');`
65			`signal n_c : std_logic_vector(15 downto 0) := (others => '0');`
66			`signal bit_size : std_logic_vector(15 downto 0) := x"0200";`
67			`--Outputs`
68			`signal s : std_logic_vector(15 downto 0);`
69			`signal valid_out : std_logic;`
70
71			`-- Clock period definitions`
72			`constant clk_period : time := 1ns;`
73
74			`begin`
75
76			`-- Instantiate the Unit Under Test (UUT)`
77			`uut : rsa_top port map (`
78			`clk => clk,`
79			`reset => reset,`
80			`valid_in => valid_in,`
81			`x => x,`
82			`y => y,`
83			`m => m,`
84			`r_c => r_c,`
85			`n_c => n_c,`
86			`s => s,`
87			`valid_out => valid_out,`
88			`bit_size => bit_size`
89			`);`
90
91			`-- Clock process definitions`
92			`clk_process : process`
93			`begin`
94			`clk <= '0';`
95			`wait for clk_period/2;`
96			`clk <= '1';`
97			`wait for clk_period/2;`
98			`end process;`
99
100
101			`-- Stimulus process`
102			`stim_proc : process`
103			`begin`
104			`valid_in <= '0';`
105			`-- hold reset state for 100ms.`
106			`reset <= '1';`
107			`wait for 10ns;`
108			`reset <= '0';`
109			`wait for clk_period*10;`
110
111			`-- insert stimulus here`
112
113			`--n_c and valid signal and the r_c constant are also required`
114			`n_c <= x"738f";`
115			`valid_in <= '1';`
116			`x <= x"f3ad";`
117			`y <= x"42b1";`
118			`m <= x"b491";`
119			`r_c <= x"f579";`
120			`wait for clk_period;`
121			`x <= x"8e40";`
122			`y <= x"1ad3";`
123			`m <= x"1417";`
124			`r_c <= x"6ee9";`
125			`wait for clk_period;`
126			`x <= x"6af9";`
127			`y <= x"a827";`
128			`m <= x"b498";`
129			`r_c <= x"972d";`
130			`wait for clk_period;`
131			`x <= x"4e63";`
132			`y <= x"0d64";`
133			`m <= x"e1b7";`
134			`r_c <= x"5052";`
135			`wait for clk_period;`
136			`x <= x"9600";`
137			`y <= x"3f76";`
138			`m <= x"e47c";`
139			`r_c <= x"1dca";`
140			`wait for clk_period;`
141			`x <= x"68f4";`
142			`y <= x"6670";`
143			`m <= x"b186";`
144			`r_c <= x"bc81";`
145			`wait for clk_period;`
146			`x <= x"5a12";`
147			`y <= x"5a1c";`
148			`m <= x"93f0";`
149			`r_c <= x"377e";`
150			`wait for clk_period;`
151			`x <= x"d62e";`
152			`y <= x"4844";`
153			`m <= x"b183";`
154			`r_c <= x"04ef";`
155			`wait for clk_period;`
156			`x <= x"8fc1";`
157			`y <= x"d5f2";`
158			`m <= x"f8f1";`
159			`r_c <= x"3a2a";`
160			`wait for clk_period;`
161			`x <= x"031d";`
162			`y <= x"b65a";`
163			`m <= x"eed1";`
164			`r_c <= x"291b";`
165			`wait for clk_period;`
166			`x <= x"f496";`
167			`y <= x"034f";`
168			`m <= x"0083";`
169			`r_c <= x"c159";`
170			`wait for clk_period;`
171			`x <= x"1268";`
172			`y <= x"9635";`
173			`m <= x"981c";`
174			`r_c <= x"9336";`
175			`wait for clk_period;`
176			`x <= x"2e5a";`
177			`y <= x"386e";`
178			`m <= x"6441";`
179			`r_c <= x"1bd0";`
180			`wait for clk_period;`
181			`x <= x"c1d6";`
182			`y <= x"fb73";`
183			`m <= x"fcd8";`
184			`r_c <= x"317d";`
185			`wait for clk_period;`
186			`x <= x"cd8f";`
187			`y <= x"5623";`
188			`m <= x"cbf0";`
189			`r_c <= x"64b4";`
190			`wait for clk_period;`
191			`x <= x"e4d2";`
192			`y <= x"9041";`
193			`m <= x"e3ca";`
194			`r_c <= x"8793";`
195			`wait for clk_period;`
196			`x <= x"36c6";`
197			`y <= x"99da";`
198			`m <= x"41d9";`
199			`r_c <= x"85f5";`
200			`wait for clk_period;`
201			`x <= x"df4a";`
202			`y <= x"cd68";`
203			`m <= x"b7a0";`
204			`r_c <= x"7c8d";`
205			`wait for clk_period;`
206			`x <= x"8e40";`
207			`y <= x"9a94";`
208			`m <= x"146e";`
209			`r_c <= x"64d9";`
210			`wait for clk_period;`
211			`x <= x"6af9";`
212			`y <= x"ccc8";`
213			`m <= x"4776";`
214			`r_c <= x"c7f6";`
215			`wait for clk_period;`
216			`x <= x"4e63";`
217			`y <= x"ed49";`
218			`m <= x"ec50";`
219			`r_c <= x"fba0";`
220			`wait for clk_period;`
221			`x <= x"9600";`
222			`y <= x"4d25";`
223			`m <= x"c07c";`
224			`r_c <= x"e3e0";`
225			`wait for clk_period;`
226			`x <= x"68f4";`
227			`y <= x"3b8e";`
228			`m <= x"e698";`
229			`r_c <= x"b567";`
230			`wait for clk_period;`
231			`x <= x"5a12";`
232			`y <= x"36d5";`
233			`m <= x"d85f";`
234			`r_c <= x"3172";`
235			`wait for clk_period;`
236			`x <= x"d62e";`
237			`y <= x"3a75";`
238			`m <= x"729c";`
239			`r_c <= x"111a";`
240			`wait for clk_period;`
241			`x <= x"8fc1";`
242			`y <= x"77a3";`
243			`m <= x"19b6";`
244			`r_c <= x"1971";`
245			`wait for clk_period;`
246			`x <= x"d2cd";`
247			`y <= x"367f";`
248			`m <= x"05d3";`
249			`r_c <= x"9f9b";`
250			`wait for clk_period;`
251			`x <= x"c6e4";`
252			`y <= x"68de";`
253			`m <= x"cacd";`
254			`r_c <= x"b574";`
255			`wait for clk_period;`
256			`x <= x"4a36";`
257			`y <= x"59a4";`
258			`m <= x"e16f";`
259			`r_c <= x"4a50";`
260			`wait for clk_period;`
261			`x <= x"f6df";`
262			`y <= x"9f89";`
263			`m <= x"f67b";`
264			`r_c <= x"6d56";`
265			`wait for clk_period;`
266			`x <= x"061c";`
267			`y <= x"ed71";`
268			`m <= x"7066";`
269			`r_c <= x"bdc6";`
270			`wait for clk_period;`
271			`x <= x"06c8";`
272			`y <= x"059f";`
273			`m <= x"08de";`
274			`r_c <= x"0400";`
275			`wait for clk_period;`
276			`valid_in <= '0';`
277
278			`--valid_in <='0';`
279			`wait for clk_period*200000;`
280
281			`--Now with the public key x"10001";`
282
283			`bit_size <= x"0011";`
284			`valid_in <= '1';`
285			`x <= x"f3ad";`
286			`y <= x"0001";`
287			`m <= x"b491";`
288			`r_c <= x"f579";`
289			`wait for clk_period;`
290			`x <= x"8e40";`
291			`y <= x"0001";`
292			`m <= x"1417";`
293			`r_c <= x"6ee9";`
294			`wait for clk_period;`
295			`x <= x"6af9";`
296			`y <= x"0000";`
297			`m <= x"b498";`
298			`r_c <= x"972d";`
299			`wait for clk_period;`
300			`x <= x"4e63";`
301			`m <= x"e1b7";`
302			`r_c <= x"5052";`
303			`wait for clk_period;`
304			`x <= x"9600";`
305			`m <= x"e47c";`
306			`r_c <= x"1dca";`
307			`wait for clk_period;`
308			`x <= x"68f4";`
309			`m <= x"b186";`
310			`r_c <= x"bc81";`
311			`wait for clk_period;`
312			`x <= x"5a12";`
313			`m <= x"93f0";`
314			`r_c <= x"377e";`
315			`wait for clk_period;`
316			`x <= x"d62e";`
317			`m <= x"b183";`
318			`r_c <= x"04ef";`
319			`wait for clk_period;`
320			`x <= x"8fc1";`
321			`m <= x"f8f1";`
322			`r_c <= x"3a2a";`
323			`wait for clk_period;`
324			`x <= x"031d";`
325			`m <= x"eed1";`
326			`r_c <= x"291b";`
327			`wait for clk_period;`
328			`x <= x"f496";`
329			`m <= x"0083";`
330			`r_c <= x"c159";`
331			`wait for clk_period;`
332			`x <= x"1268";`
333
334			`m <= x"981c";`
335			`r_c <= x"9336";`
336			`wait for clk_period;`
337			`x <= x"2e5a";`
338
339			`m <= x"6441";`
340			`r_c <= x"1bd0";`
341			`wait for clk_period;`
342			`x <= x"c1d6";`
343
344			`m <= x"fcd8";`
345			`r_c <= x"317d";`
346			`wait for clk_period;`
347			`x <= x"cd8f";`
348
349			`m <= x"cbf0";`
350			`r_c <= x"64b4";`
351			`wait for clk_period;`
352			`x <= x"e4d2";`
353
354			`m <= x"e3ca";`
355			`r_c <= x"8793";`
356			`wait for clk_period;`
357			`x <= x"36c6";`
358
359			`m <= x"41d9";`
360			`r_c <= x"85f5";`
361			`wait for clk_period;`
362			`x <= x"df4a";`
363
364			`m <= x"b7a0";`
365			`r_c <= x"7c8d";`
366			`wait for clk_period;`
367			`x <= x"8e40";`
368
369			`m <= x"146e";`
370			`r_c <= x"64d9";`
371			`wait for clk_period;`
372			`x <= x"6af9";`
373
374			`m <= x"4776";`
375			`r_c <= x"c7f6";`
376			`wait for clk_period;`
377			`x <= x"4e63";`
378
379			`m <= x"ec50";`
380			`r_c <= x"fba0";`
381			`wait for clk_period;`
382			`x <= x"9600";`
383
384			`m <= x"c07c";`
385			`r_c <= x"e3e0";`
386			`wait for clk_period;`
387			`x <= x"68f4";`
388
389			`m <= x"e698";`
390			`r_c <= x"b567";`
391			`wait for clk_period;`
392			`x <= x"5a12";`
393
394			`m <= x"d85f";`
395			`r_c <= x"3172";`
396			`wait for clk_period;`
397			`x <= x"d62e";`
398
399			`m <= x"729c";`
400			`r_c <= x"111a";`
401			`wait for clk_period;`
402			`x <= x"8fc1";`
403
404			`m <= x"19b6";`
405			`r_c <= x"1971";`
406			`wait for clk_period;`
407			`x <= x"d2cd";`
408
409			`m <= x"05d3";`
410			`r_c <= x"9f9b";`
411			`wait for clk_period;`
412			`x <= x"c6e4";`
413
414			`m <= x"cacd";`
415			`r_c <= x"b574";`
416			`wait for clk_period;`
417			`x <= x"4a36";`
418
419			`m <= x"e16f";`
420			`r_c <= x"4a50";`
421			`wait for clk_period;`
422			`x <= x"f6df";`
423
424			`m <= x"f67b";`
425			`r_c <= x"6d56";`
426			`wait for clk_period;`
427			`x <= x"061c";`
428
429			`m <= x"7066";`
430			`r_c <= x"bdc6";`
431			`wait for clk_period;`
432			`x <= x"06c8";`
433
434			`m <= x"08de";`
435			`r_c <= x"0400";`
436			`wait for clk_period;`
437			`valid_in <= '0';`
438
439			`wait;`
440			`end process;`
441
442			`END;`