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[/] [rtc/] [trunk/] [rtl/] [verilog/] [rtc_defines.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  WISHBONE Real-Time Clock Definitions                        ////
////                                                              ////
////  This file is part of the RTC project                        ////
////  http://www.opencores.org/cores/rtc/                         ////
////                                                              ////
////  Description                                                 ////
////  RTC definitions.                                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/21 12:53:11  lampret
// Changed directory structure, uniquified defines and changed design's port names.
//
// Revision 1.2  2001/07/16 01:08:45  lampret
// Added additional parameters to make RTL more configurable. Added bunch of comments to defines.v
//
// Revision 1.1  2001/06/05 07:45:43  lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
//
// Undefine this one if you don't want to remove RTC block from your design
// but you also don't need it. When it is undefined, all RTC ports still
// remain valid and the core can be synthesized however internally there is
// no RTC funationality.
//
// Defined by default (duhh !).
//
`define RTC_IMPLEMENTED
 
//
// Undefine if you don't need to read RTC registers.
// When it is undefined all reads of RTC registers return zero. This
// is usually useful if you want really small area (for example when
// implemented in FPGA).
//
// To follow RTC IP core specification document this one must be defined.
// Also to successfully run the test bench it must be defined. By default
// it is defined.
//
`define RTC_READREGS
 
//
// Undefine if you don't need RTC internal clock divider circuitry. Without
// divider RTC is clocked directly by WISHBONE or external clock.
//
// To follow RTC IP core specification document this one must be defined. Also to
// successfully run the test bench it must be defined. By default it is defined.
//
`define RTC_DIVIDER
 
//
// Full WISHBONE address decoding
//
// It is is undefined, partial WISHBONE address decoding is performed.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define RTC_FULL_DECODE
 
//
// Strict 32-bit WISHBONE access
//
// If this one is defined, all WISHBONE accesses must be 32-bit. If it is
// not defined, err_o is asserted whenever 8- or 16-bit access is made.
// Undefine it if you need to save some area.
//
// By default it is defined.
//
`define RTC_STRICT_32BIT_ACCESS
 
//
// WISHBONE address bits used for full decoding of RTC registers.
//
`define RTC_ADDRHH 15
`define RTC_ADDRHL 5
`define RTC_ADDRLH 1
`define RTC_ADDRLL 0
 
//
// Bits of WISHBONE address used for partial decoding of RTC registers.
//
// Default 4:2.
//
`define RTC_OFS_BITS    `RTC_ADDRHL-1:`RTC_ADDRLH+1
 
//
// Addresses of RTC registers
//
// To comply with RTC IP core specification document they must go from
// address 0 to address 0x10 in the following order: RRTC_TIME, RRTC_DATE,
// RRTC_TALRM, RRTC_DALRM and RRTC_CTRL
//
// If particular alarm/ctrl register is not needed, it's address definition
// can be omitted and the register will not be implemented. Instead a fixed
// default value will
// be used.
//
`define RTC_RRTC_TIME   3'h0    // Address 0x00
`define RTC_RRTC_DATE   3'h1    // Address 0x04
`define RTC_RRTC_TALRM  3'h2    // Address 0x08
`define RTC_RRTC_DALRM  3'h3    // Address 0x0c
`define RTC_RRTC_CTRL   3'h4    // Address 0x10
 
//
// Default values for unimplemented RTC registers
//
`define RTC_DEF_RRTC_TALRM      32'h00000000    // No time alarms
`define RTC_DEF_RRTC_DALRM      31'h00000000    // No date alarms
`define RTC_DEF_RRTC_CTRL       32'h80000000    // RRTC_CTRL[EN] = 1
 
//
// RRTC_TIME bits
//
// To comply with the RTC IP core specification document they must go from
// bit 0 to bit 26 in the following order: TOS, S, TS, M, TM, H, TH, DOW
//
`define RTC_RRTC_TIME_TOS               3:0
`define RTC_RRTC_TIME_S                 7:4
`define RTC_RRTC_TIME_TS                10:8
`define RTC_RRTC_TIME_M                 14:11
`define RTC_RRTC_TIME_TM                17:15
`define RTC_RRTC_TIME_H                 21:18
`define RTC_RRTC_TIME_TH                23:22
`define RTC_RRTC_TIME_DOW               26:24
 
//
// RRTC_DATE bits
//
// To comply with the RTC IP core specification document they must go from
// bit 0 to bit 26 in the following order: D, TD, M, TM, Y, TY, C, TC
//
`define RTC_RRTC_DATE_D                 3:0
`define RTC_RRTC_DATE_TD                5:4
`define RTC_RRTC_DATE_M                 9:6
`define RTC_RRTC_DATE_TM                10
`define RTC_RRTC_DATE_Y                 14:11
`define RTC_RRTC_DATE_TY                18:15
`define RTC_RRTC_DATE_C                 22:19
`define RTC_RRTC_DATE_TC                26:23
 
//
// RRTC_TALRM bits
//
// To comply with the RTC IP core specification document they must go from
// bit 0 to bit 31 in the following order: TOS, S, TS, M, TM, H, TH, DOW,
// CTOS, CS, CM, CH, CDOW
//
`define RTC_RRTC_TALRM_TOS              3:0
`define RTC_RRTC_TALRM_S                7:4
`define RTC_RRTC_TALRM_TS               10:8
`define RTC_RRTC_TALRM_M                14:11
`define RTC_RRTC_TALRM_TM               17:15
`define RTC_RRTC_TALRM_H                21:18
`define RTC_RRTC_TALRM_TH               23:22
`define RTC_RRTC_TALRM_DOW              26:24
`define RTC_RRTC_TALRM_CTOS             27
`define RTC_RRTC_TALRM_CS               28
`define RTC_RRTC_TALRM_CM               29
`define RTC_RRTC_TALRM_CH               30
`define RTC_RRTC_TALRM_CDOW             31
 
//
// RRTC_DALRM bits
//
// To comply with the RTC IP core specification document they must go from
// bit 0 to bit 30 in the following order: D, TD, M, TM, Y, TY, C, TC,
// CD, CM, CY, CC
//
`define RTC_RRTC_DALRM_D                3:0
`define RTC_RRTC_DALRM_TD               5:4
`define RTC_RRTC_DALRM_M                9:6
`define RTC_RRTC_DALRM_TM               10
`define RTC_RRTC_DALRM_Y                14:11
`define RTC_RRTC_DALRM_TY               18:15
`define RTC_RRTC_DALRM_C                22:19
`define RTC_RRTC_DALRM_TC               26:23
`define RTC_RRTC_DALRM_CD               27
`define RTC_RRTC_DALRM_CM               28
`define RTC_RRTC_DALRM_CY               29
`define RTC_RRTC_DALRM_CC               30
 
//
// RRTC_CTRL bits
//
// To comply with the RTC IP core specification document they must go from
// bit 0 to bit 31 in the following order: DIV, BTOS, ECLK, INTE, ALRM, EN
//
`define RTC_RRTC_CTRL_DIV               26:0
`define RTC_RRTC_CTRL_BTOS              27
`define RTC_RRTC_CTRL_ECLK              28
`define RTC_RRTC_CTRL_INTE              29
`define RTC_RRTC_CTRL_ALRM              30
`define RTC_RRTC_CTRL_EN                31

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[/] [rtc/] [trunk/] [rtl/] [verilog/] [rtc_defines.v] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// WISHBONE Real-Time Clock Definitions ////`
4			`//// ////`
5			`//// This file is part of the RTC project ////`
6			`//// http://www.opencores.org/cores/rtc/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// RTC definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2001/08/21 12:53:11 lampret`
48			`// Changed directory structure, uniquified defines and changed design's port names.`
49			`//`
50			`// Revision 1.2 2001/07/16 01:08:45 lampret`
51			`// Added additional parameters to make RTL more configurable. Added bunch of comments to defines.v`
52			`//`
53			`// Revision 1.1 2001/06/05 07:45:43 lampret`
54			`// Added initial RTL and test benches. There are still some issues with these files.`
55			`//`
56			`//`
57
58			`//`
59			`// Undefine this one if you don't want to remove RTC block from your design`
60			`// but you also don't need it. When it is undefined, all RTC ports still`
61			`// remain valid and the core can be synthesized however internally there is`
62			`// no RTC funationality.`
63			`//`
64			`// Defined by default (duhh !).`
65			`//`
66			`define RTC_IMPLEMENTED
67
68			`//`
69			`// Undefine if you don't need to read RTC registers.`
70			`// When it is undefined all reads of RTC registers return zero. This`
71			`// is usually useful if you want really small area (for example when`
72			`// implemented in FPGA).`
73			`//`
74			`// To follow RTC IP core specification document this one must be defined.`
75			`// Also to successfully run the test bench it must be defined. By default`
76			`// it is defined.`
77			`//`
78			`define RTC_READREGS
79
80			`//`
81			`// Undefine if you don't need RTC internal clock divider circuitry. Without`
82			`// divider RTC is clocked directly by WISHBONE or external clock.`
83			`//`
84			`// To follow RTC IP core specification document this one must be defined. Also to`
85			`// successfully run the test bench it must be defined. By default it is defined.`
86			`//`
87			`define RTC_DIVIDER
88
89			`//`
90			`// Full WISHBONE address decoding`
91			`//`
92			`// It is is undefined, partial WISHBONE address decoding is performed.`
93			`// Undefine it if you need to save some area.`
94			`//`
95			`// By default it is defined.`
96			`//`
97			`define RTC_FULL_DECODE
98
99			`//`
100			`// Strict 32-bit WISHBONE access`
101			`//`
102			`// If this one is defined, all WISHBONE accesses must be 32-bit. If it is`
103			`// not defined, err_o is asserted whenever 8- or 16-bit access is made.`
104			`// Undefine it if you need to save some area.`
105			`//`
106			`// By default it is defined.`
107			`//`
108			`define RTC_STRICT_32BIT_ACCESS
109
110			`//`
111			`// WISHBONE address bits used for full decoding of RTC registers.`
112			`//`
113			`define RTC_ADDRHH 15
114			`define RTC_ADDRHL 5
115			`define RTC_ADDRLH 1
116			`define RTC_ADDRLL 0
117
118			`//`
119			`// Bits of WISHBONE address used for partial decoding of RTC registers.`
120			`//`
121			`// Default 4:2.`
122			`//`
123			`define RTC_OFS_BITS `RTC_ADDRHL-1:`RTC_ADDRLH+1
124
125			`//`
126			`// Addresses of RTC registers`
127			`//`
128			`// To comply with RTC IP core specification document they must go from`
129			`// address 0 to address 0x10 in the following order: RRTC_TIME, RRTC_DATE,`
130			`// RRTC_TALRM, RRTC_DALRM and RRTC_CTRL`
131			`//`
132			`// If particular alarm/ctrl register is not needed, it's address definition`
133			`// can be omitted and the register will not be implemented. Instead a fixed`
134			`// default value will`
135			`// be used.`
136			`//`
137			`define RTC_RRTC_TIME 3'h0 // Address 0x00
138			`define RTC_RRTC_DATE 3'h1 // Address 0x04
139			`define RTC_RRTC_TALRM 3'h2 // Address 0x08
140			`define RTC_RRTC_DALRM 3'h3 // Address 0x0c
141			`define RTC_RRTC_CTRL 3'h4 // Address 0x10
142
143			`//`
144			`// Default values for unimplemented RTC registers`
145			`//`
146			`define RTC_DEF_RRTC_TALRM 32'h00000000 // No time alarms
147			`define RTC_DEF_RRTC_DALRM 31'h00000000 // No date alarms
148			`define RTC_DEF_RRTC_CTRL 32'h80000000 // RRTC_CTRL[EN] = 1
149
150			`//`
151			`// RRTC_TIME bits`
152			`//`
153			`// To comply with the RTC IP core specification document they must go from`
154			`// bit 0 to bit 26 in the following order: TOS, S, TS, M, TM, H, TH, DOW`
155			`//`
156			`define RTC_RRTC_TIME_TOS 3:0
157			`define RTC_RRTC_TIME_S 7:4
158			`define RTC_RRTC_TIME_TS 10:8
159			`define RTC_RRTC_TIME_M 14:11
160			`define RTC_RRTC_TIME_TM 17:15
161			`define RTC_RRTC_TIME_H 21:18
162			`define RTC_RRTC_TIME_TH 23:22
163			`define RTC_RRTC_TIME_DOW 26:24
164
165			`//`
166			`// RRTC_DATE bits`
167			`//`
168			`// To comply with the RTC IP core specification document they must go from`
169			`// bit 0 to bit 26 in the following order: D, TD, M, TM, Y, TY, C, TC`
170			`//`
171			`define RTC_RRTC_DATE_D 3:0
172			`define RTC_RRTC_DATE_TD 5:4
173			`define RTC_RRTC_DATE_M 9:6
174			`define RTC_RRTC_DATE_TM 10
175			`define RTC_RRTC_DATE_Y 14:11
176			`define RTC_RRTC_DATE_TY 18:15
177			`define RTC_RRTC_DATE_C 22:19
178			`define RTC_RRTC_DATE_TC 26:23
179
180			`//`
181			`// RRTC_TALRM bits`
182			`//`
183			`// To comply with the RTC IP core specification document they must go from`
184			`// bit 0 to bit 31 in the following order: TOS, S, TS, M, TM, H, TH, DOW,`
185			`// CTOS, CS, CM, CH, CDOW`
186			`//`
187			`define RTC_RRTC_TALRM_TOS 3:0
188			`define RTC_RRTC_TALRM_S 7:4
189			`define RTC_RRTC_TALRM_TS 10:8
190			`define RTC_RRTC_TALRM_M 14:11
191			`define RTC_RRTC_TALRM_TM 17:15
192			`define RTC_RRTC_TALRM_H 21:18
193			`define RTC_RRTC_TALRM_TH 23:22
194			`define RTC_RRTC_TALRM_DOW 26:24
195			`define RTC_RRTC_TALRM_CTOS 27
196			`define RTC_RRTC_TALRM_CS 28
197			`define RTC_RRTC_TALRM_CM 29
198			`define RTC_RRTC_TALRM_CH 30
199			`define RTC_RRTC_TALRM_CDOW 31
200
201			`//`
202			`// RRTC_DALRM bits`
203			`//`
204			`// To comply with the RTC IP core specification document they must go from`
205			`// bit 0 to bit 30 in the following order: D, TD, M, TM, Y, TY, C, TC,`
206			`// CD, CM, CY, CC`
207			`//`
208			`define RTC_RRTC_DALRM_D 3:0
209			`define RTC_RRTC_DALRM_TD 5:4
210			`define RTC_RRTC_DALRM_M 9:6
211			`define RTC_RRTC_DALRM_TM 10
212			`define RTC_RRTC_DALRM_Y 14:11
213			`define RTC_RRTC_DALRM_TY 18:15
214			`define RTC_RRTC_DALRM_C 22:19
215			`define RTC_RRTC_DALRM_TC 26:23
216			`define RTC_RRTC_DALRM_CD 27
217			`define RTC_RRTC_DALRM_CM 28
218			`define RTC_RRTC_DALRM_CY 29
219			`define RTC_RRTC_DALRM_CC 30
220
221			`//`
222			`// RRTC_CTRL bits`
223			`//`
224			`// To comply with the RTC IP core specification document they must go from`
225			`// bit 0 to bit 31 in the following order: DIV, BTOS, ECLK, INTE, ALRM, EN`
226			`//`
227			`define RTC_RRTC_CTRL_DIV 26:0
228			`define RTC_RRTC_CTRL_BTOS 27
229			`define RTC_RRTC_CTRL_ECLK 28
230			`define RTC_RRTC_CTRL_INTE 29
231			`define RTC_RRTC_CTRL_ALRM 30
232			`define RTC_RRTC_CTRL_EN 31