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lampret |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Real-Time Clock ////
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//// ////
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//// This file is part of the RTC project ////
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//// http://www.opencores.org/cores/rtc/ ////
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//// ////
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//// Description ////
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//// Implementation of Real-Time clock IP core according to ////
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//// RTC IP core specification document. Using async resets ////
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//// would make core even smaller. ////
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//// ////
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//// To Do: ////
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//// Nothing ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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17 |
lampret |
// Revision 1.1 2001/09/18 22:55:39 lampret
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// Changed rtc into rtc_top. Changed defines.v into rtc_defines.v. Fixed a bug with two defines for alarms.
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//
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lampret |
// Revision 1.2 2001/08/22 10:58:27 lampret
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// Changed synthesis translate_ to synopsys translate.
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//
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// Revision 1.1 2001/08/21 12:53:11 lampret
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// Changed directory structure, uniquified defines and changed design's port names.
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//
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// Revision 1.3 2001/07/17 00:02:55 lampret
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// Fixed reading of registers.
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//
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// Revision 1.2 2001/07/16 01:08:45 lampret
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// Added additional parameters to make RTL more configurable. Added bunch of comments to defines.v
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//
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// Revision 1.1 2001/06/05 07:45:43 lampret
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// Added initial RTL and test benches. There are still some issues with these files.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "rtc_defines.v"
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module rtc_top(
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// WISHBONE Interface
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wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
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wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
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// External RTC Interface
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clk_rtc_pad_i
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);
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parameter dw = 32;
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parameter aw = `RTC_ADDRHH+1;
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//
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// WISHBONE Interface
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//
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input wb_clk_i; // Clock
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input wb_rst_i; // Reset
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input wb_cyc_i; // cycle valid input
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input [aw-1:0] wb_adr_i; // address bus inputs
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input [dw-1:0] wb_dat_i; // input data bus
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input [3:0] wb_sel_i; // byte select inputs
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input wb_we_i; // indicates write transfer
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input wb_stb_i; // strobe input
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output [dw-1:0] wb_dat_o; // output data bus
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output wb_ack_o; // normal termination
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output wb_err_o; // termination w/ error
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output wb_inta_o; // Interrupt request output
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//
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// External RTC Interface
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//
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input clk_rtc_pad_i; // External clock
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`ifdef RTC_IMPLEMENTED
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//
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// Counters of RTC Time Register
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//
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reg [3:0] time_tos; // Tenth of second counter
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reg [3:0] time_s; // Seconds counter
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reg [2:0] time_ts; // Ten seconds counter
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reg [3:0] time_m; // Minutes counter
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reg [2:0] time_tm; // Ten minutes counter
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reg [3:0] time_h; // Hours counter
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reg [1:0] time_th; // Ten hours counter
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reg [2:0] time_dow; // Day of week counter
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//
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// Counter of RTC Date Register
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//
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reg [3:0] date_d; // Days counter
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reg [1:0] date_td; // Ten days counter
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reg [3:0] date_m; // Months counter
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reg date_tm; // Ten months counter
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reg [3:0] date_y; // Years counter
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reg [3:0] date_ty; // Ten years counter
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reg [3:0] date_c; // Centuries counter
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reg [3:0] date_tc; // Ten centuries counter
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//
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// Clock division counter
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//
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`ifdef RTC_DIVIDER
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reg [26:0] cntr_div; // Division counter
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reg div_clk; // Tenth of a second clock
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`else
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wire div_clk; // Tenth of a second clock
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`endif
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//
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// RTC TALRM Register
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//
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`ifdef RTC_RRTC_TALRM
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reg [31:0] rrtc_talrm; // RRTC_TALRM register
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`else
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wire [31:0] rrtc_talrm; // No register
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`endif
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//
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// RTC DALRM Register
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//
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`ifdef RTC_RRTC_DALRM
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reg [30:0] rrtc_dalrm; // RRTC_DALRM register
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`else
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wire [30:0] rrtc_dalrm; // No register
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`endif
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//
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// RTC CTRL register
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//
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reg [31:0] rrtc_ctrl; // RRTC_CTRL register
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//
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// Internal wires & regs
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//
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wire [31:0] rrtc_time; // Alias
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wire [31:0] rrtc_date; // Alias
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wire rrtc_time_sel; // RRTC_TIME select
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wire rrtc_date_sel; // RRTC_DATE select
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wire rrtc_talrm_sel; // RRTC_TALRM select
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wire rrtc_dalrm_sel; // RRTC_DALRM select
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wire rrtc_ctrl_sel; // RRTC_CTRL select
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wire match_tos; // Tenth of second match
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wire match_secs; // Seconds match
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wire match_mins; // Minutes match
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wire match_hrs; // Hours match
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wire match_dow; // Day of week match
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wire match_days; // Days match
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wire match_months; // Months match
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wire match_yrs; // Years match
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wire match_cents; // Centuries match
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wire rst_time_tos; // Reset RRTC_TIME[TOS]
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wire rst_time_s; // Reset RRTC_TIME[S]
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wire rst_time_ts; // Reset RRTC_TIME[TS]
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wire rst_time_m; // Reset RRTC_TIME[M]
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wire rst_time_tm; // Reset RRTC_TIME[TM]
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wire rst_time_h; // Reset RRTC_TIME[H]
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wire rst_time_th; // Reset RRTC_TIME[TH]
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wire rst_time_dow; // Reset RRTC_TIME[DOW]
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wire rst_date_d; // Reset RRTC_DATE[D]
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wire rst_date_td; // Reset RRTC_DATE[TD]
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wire rst_date_m; // Reset RRTC_DATE[M]
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wire rst_date_tm; // Reset RRTC_DATE[TM]
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wire rst_date_y; // Reset RRTC_DATE[Y]
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wire rst_date_ty; // Reset RRTC_DATE[TY]
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wire rst_date_c; // Reset RRTC_DATE[C]
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wire rst_date_tc; // Reset RRTC_DATE[TC]
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wire inc_time_tos; // Enable counter RRTC_TIME[TOS]
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wire inc_time_s; // Enable counter RRTC_TIME[S]
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wire inc_time_ts; // Enable counter RRTC_TIME[TS]
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wire inc_time_m; // Enable counter RRTC_TIME[M]
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wire inc_time_tm; // Enable counter RRTC_TIME[TM]
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wire inc_time_h; // Enable counter RRTC_TIME[H]
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wire inc_time_th; // Enable counter RRTC_TIME[TH]
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wire inc_time_dow; // Enable counter RRTC_TIME[DOW]
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wire inc_date_d; // Enable counter RRTC_DATE[D]
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wire inc_date_td; // Enable counter RRTC_DATE[TD]
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wire inc_date_m; // Enable counter RRTC_DATE[M]
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wire inc_date_tm; // Enable counter RRTC_DATE[TM]
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wire inc_date_y; // Enable counter RRTC_DATE[Y]
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wire inc_date_ty; // Enable counter RRTC_DATE[TY]
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wire inc_date_c; // Enable counter RRTC_DATE[C]
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wire inc_date_tc; // Enable counter RRTC_DATE[TC]
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wire one_date_d; // Set RRTC_DATE[D] to 1
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wire one_date_m; // Set RRTC_DATE[M] to 1
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wire hi_clk; // Hi freq clock
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wire lo_clk; // Lo freq clock
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wire alarm; // Alarm condition
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wire leapyear; // Leap year
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wire full_decoding; // Full address decoding qualification
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reg [dw-1:0] wb_dat_o; // Data out
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//
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// All WISHBONE transfer terminations are successful except when:
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// a) full address decoding is enabled and address doesn't match
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// any of the RTC registers
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// b) sel_i evaluation is enabled and one of the sel_i inputs is zero
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//
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assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
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`ifdef RTC_FULL_DECODE
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`ifdef RTC_STRICT_32BIT_ACCESS
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lampret |
assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
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lampret |
`else
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assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
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`endif
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`else
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`ifdef RTC_STRICT_32BIT_ACCESS
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lampret |
assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
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`else
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assign wb_err_o = 1'b0;
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`endif
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`endif
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//
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// Hi freq clock is selected by RRTC_CTRL[ECLK]. When it is set,
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// external clock is used.
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//
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assign hi_clk = rrtc_ctrl[`RTC_RRTC_CTRL_ECLK] ? clk_rtc_pad_i : wb_clk_i;
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//
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// Lo freq clock divided hi freq clock when RRTC_CTRL[EN] is set.
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// When RRTC_CTRL[EN] is cleared, lo freq clock is equal WISHBONE
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// clock to allow writes into registers.
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//
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assign lo_clk = rrtc_ctrl[`RTC_RRTC_CTRL_EN] ? div_clk : wb_clk_i;
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//
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// Full address decoder
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//
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`ifdef RTC_FULL_DECODE
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assign full_decoding = (wb_adr_i[`RTC_ADDRHH:`RTC_ADDRHL] == {`RTC_ADDRHH-`RTC_ADDRHL+1{1'b0}}) &
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(wb_adr_i[`RTC_ADDRLH:`RTC_ADDRLL] == {`RTC_ADDRLH-`RTC_ADDRLL+1{1'b0}});
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`else
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assign full_decoding = 1'b1;
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`endif
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//
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// RTC registers address decoder
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//
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| 273 |
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assign rrtc_time_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`RTC_OFS_BITS] ==
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`RTC_RRTC_TIME) & full_decoding;
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| 275 |
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assign rrtc_date_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`RTC_OFS_BITS] == `RTC_RRTC_DATE) & full_decoding;
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assign rrtc_talrm_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`RTC_OFS_BITS] == `RTC_RRTC_TALRM) & full_decoding;
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assign rrtc_dalrm_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`RTC_OFS_BITS] == `RTC_RRTC_DALRM) & full_decoding;
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| 278 |
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assign rrtc_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`RTC_OFS_BITS] == `RTC_RRTC_CTRL) & full_decoding;
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| 279 |
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| 280 |
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//
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| 281 |
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// Grouping of seperate fields into registers
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//
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| 283 |
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assign rrtc_time = {5'b0, time_dow, time_th, time_h, time_tm,
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| 284 |
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time_m, time_ts, time_s, time_tos};
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| 285 |
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assign rrtc_date = {5'b0, date_tc, date_c, date_ty, date_y,
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| 286 |
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date_tm, date_m, date_td, date_d};
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| 287 |
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| 288 |
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//
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| 289 |
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// Write to RRTC_CTRL or update of RRTC_CTRL[ALRM] bit
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| 290 |
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//
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| 291 |
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`ifdef RTC_RRTC_CTRL
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| 292 |
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always @(posedge wb_clk_i or posedge wb_rst_i)
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| 293 |
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if (wb_rst_i)
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| 294 |
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rrtc_ctrl <= #1 32'b0;
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| 295 |
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else if (rrtc_ctrl_sel && wb_we_i)
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| 296 |
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rrtc_ctrl <= #1 wb_dat_i;
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| 297 |
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else if (rrtc_ctrl[`RTC_RRTC_CTRL_EN])
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rrtc_ctrl[`RTC_RRTC_CTRL_ALRM] <= #1 rrtc_ctrl[`RTC_RRTC_CTRL_ALRM] | alarm;
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| 299 |
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`else
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| 300 |
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assign rrtc_ctrl = `RTC_DEF_RRTC_CTRL;
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`endif
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| 302 |
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//
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| 304 |
|
|
// Clock divider
|
| 305 |
|
|
//
|
| 306 |
|
|
`ifdef RTC_DIVIDER
|
| 307 |
|
|
always @(posedge hi_clk or posedge wb_rst_i)
|
| 308 |
|
|
if (wb_rst_i) begin
|
| 309 |
|
|
cntr_div <= #1 27'b0;
|
| 310 |
|
|
div_clk <= #1 1'b0;
|
| 311 |
|
|
end else if (!cntr_div) begin
|
| 312 |
|
|
cntr_div <= #1 rrtc_ctrl[`RTC_RRTC_CTRL_DIV];
|
| 313 |
|
|
div_clk <= #1 ~div_clk;
|
| 314 |
|
|
end else if (rrtc_ctrl[`RTC_RRTC_CTRL_EN])
|
| 315 |
|
|
cntr_div <= #1 cntr_div - 1;
|
| 316 |
|
|
`else
|
| 317 |
|
|
assign div_clk = hi_clk;
|
| 318 |
|
|
`endif
|
| 319 |
|
|
|
| 320 |
|
|
//
|
| 321 |
|
|
// Write to RRTC_TALRM
|
| 322 |
|
|
//
|
| 323 |
|
|
`ifdef RTC_RRTC_TALRM
|
| 324 |
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
| 325 |
|
|
if (wb_rst_i)
|
| 326 |
|
|
rrtc_talrm <= #1 32'b0;
|
| 327 |
|
|
else if (rrtc_talrm_sel && wb_we_i)
|
| 328 |
|
|
rrtc_talrm <= #1 wb_dat_i;
|
| 329 |
|
|
`else
|
| 330 |
|
|
assign rrtc_talrm = `RTC_DEF_RRTC_TALRM;
|
| 331 |
|
|
`endif
|
| 332 |
|
|
|
| 333 |
|
|
//
|
| 334 |
|
|
// Write to RRTC_DALRM
|
| 335 |
|
|
//
|
| 336 |
|
|
`ifdef RTC_RRTC_DALRM
|
| 337 |
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
| 338 |
|
|
if (wb_rst_i)
|
| 339 |
|
|
rrtc_dalrm <= #1 31'b0;
|
| 340 |
|
|
else if (rrtc_dalrm_sel && wb_we_i)
|
| 341 |
|
|
rrtc_dalrm <= #1 wb_dat_i[30:0];
|
| 342 |
|
|
`else
|
| 343 |
|
|
assign rrtc_dalrm = `RTC_DEF_RRTC_DALRM;
|
| 344 |
|
|
`endif
|
| 345 |
|
|
|
| 346 |
|
|
//
|
| 347 |
|
|
// RRTC_TIME[TOS]
|
| 348 |
|
|
//
|
| 349 |
|
|
always @(posedge lo_clk)
|
| 350 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 351 |
|
|
time_tos <= #1 wb_dat_i[`RTC_RRTC_TIME_TOS];
|
| 352 |
|
|
else if (rst_time_tos)
|
| 353 |
|
|
time_tos <= #1 4'b0;
|
| 354 |
|
|
else if (inc_time_tos)
|
| 355 |
|
|
time_tos <= #1 time_tos + 1;
|
| 356 |
|
|
|
| 357 |
|
|
//
|
| 358 |
|
|
// RRTC_TIME[S]
|
| 359 |
|
|
//
|
| 360 |
|
|
always @(posedge lo_clk)
|
| 361 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 362 |
|
|
time_s <= #1 wb_dat_i[`RTC_RRTC_TIME_S];
|
| 363 |
|
|
else if (rst_time_s)
|
| 364 |
|
|
time_s <= #1 4'b0;
|
| 365 |
|
|
else if (inc_time_s)
|
| 366 |
|
|
time_s <= #1 time_s + 1;
|
| 367 |
|
|
|
| 368 |
|
|
//
|
| 369 |
|
|
// RRTC_TIME[TS]
|
| 370 |
|
|
//
|
| 371 |
|
|
always @(posedge lo_clk)
|
| 372 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 373 |
|
|
time_ts <= #1 wb_dat_i[`RTC_RRTC_TIME_TS];
|
| 374 |
|
|
else if (rst_time_ts)
|
| 375 |
|
|
time_ts <= #1 3'b0;
|
| 376 |
|
|
else if (inc_time_ts)
|
| 377 |
|
|
time_ts <= #1 time_ts + 1;
|
| 378 |
|
|
|
| 379 |
|
|
//
|
| 380 |
|
|
// RRTC_TIME[M]
|
| 381 |
|
|
//
|
| 382 |
|
|
always @(posedge lo_clk)
|
| 383 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 384 |
|
|
time_m <= #1 wb_dat_i[`RTC_RRTC_TIME_M];
|
| 385 |
|
|
else if (rst_time_m)
|
| 386 |
|
|
time_m <= #1 4'b0;
|
| 387 |
|
|
else if (inc_time_m)
|
| 388 |
|
|
time_m <= #1 time_m + 1;
|
| 389 |
|
|
|
| 390 |
|
|
//
|
| 391 |
|
|
// RRTC_TIME[TM]
|
| 392 |
|
|
//
|
| 393 |
|
|
always @(posedge lo_clk)
|
| 394 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 395 |
|
|
time_tm <= #1 wb_dat_i[`RTC_RRTC_TIME_TM];
|
| 396 |
|
|
else if (rst_time_tm)
|
| 397 |
|
|
time_tm <= #1 3'b0;
|
| 398 |
|
|
else if (inc_time_tm)
|
| 399 |
|
|
time_tm <= #1 time_tm + 1;
|
| 400 |
|
|
|
| 401 |
|
|
//
|
| 402 |
|
|
// RRTC_TIME[H]
|
| 403 |
|
|
//
|
| 404 |
|
|
always @(posedge lo_clk)
|
| 405 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 406 |
|
|
time_h <= #1 wb_dat_i[`RTC_RRTC_TIME_H];
|
| 407 |
|
|
else if (rst_time_h)
|
| 408 |
|
|
time_h <= #1 4'b0;
|
| 409 |
|
|
else if (inc_time_h)
|
| 410 |
|
|
time_h <= #1 time_h + 1;
|
| 411 |
|
|
|
| 412 |
|
|
//
|
| 413 |
|
|
// RRTC_TIME[TH]
|
| 414 |
|
|
//
|
| 415 |
|
|
always @(posedge lo_clk)
|
| 416 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 417 |
|
|
time_th <= #1 wb_dat_i[`RTC_RRTC_TIME_TH];
|
| 418 |
|
|
else if (rst_time_th)
|
| 419 |
|
|
time_th <= #1 2'b0;
|
| 420 |
|
|
else if (inc_time_th)
|
| 421 |
|
|
time_th <= #1 time_th + 1;
|
| 422 |
|
|
|
| 423 |
|
|
//
|
| 424 |
|
|
// RRTC_TIME[DOW]
|
| 425 |
|
|
//
|
| 426 |
|
|
always @(posedge lo_clk)
|
| 427 |
|
|
if (rrtc_time_sel && wb_we_i)
|
| 428 |
|
|
time_dow <= #1 wb_dat_i[`RTC_RRTC_TIME_DOW];
|
| 429 |
|
|
else if (rst_time_dow)
|
| 430 |
|
|
time_dow <= #1 3'h1;
|
| 431 |
|
|
else if (inc_time_dow)
|
| 432 |
|
|
time_dow <= #1 time_dow + 1;
|
| 433 |
|
|
|
| 434 |
|
|
//
|
| 435 |
|
|
// RRTC_DATE[D]
|
| 436 |
|
|
//
|
| 437 |
|
|
always @(posedge lo_clk)
|
| 438 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 439 |
|
|
date_d <= #1 wb_dat_i[`RTC_RRTC_DATE_D];
|
| 440 |
|
|
else if (one_date_d)
|
| 441 |
|
|
date_d <= #1 4'h1;
|
| 442 |
|
|
else if (rst_date_d)
|
| 443 |
|
|
date_d <= #1 4'h0;
|
| 444 |
|
|
else if (inc_date_d)
|
| 445 |
|
|
date_d <= #1 date_d + 1;
|
| 446 |
|
|
|
| 447 |
|
|
//
|
| 448 |
|
|
// RRTC_DATE[TD]
|
| 449 |
|
|
//
|
| 450 |
|
|
always @(posedge lo_clk)
|
| 451 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 452 |
|
|
date_td <= #1 wb_dat_i[`RTC_RRTC_DATE_TD];
|
| 453 |
|
|
else if (rst_date_td)
|
| 454 |
|
|
date_td <= #1 2'b0;
|
| 455 |
|
|
else if (inc_date_td)
|
| 456 |
|
|
date_td <= #1 date_td + 1;
|
| 457 |
|
|
|
| 458 |
|
|
//
|
| 459 |
|
|
// RRTC_DATE[M]
|
| 460 |
|
|
//
|
| 461 |
|
|
always @(posedge lo_clk)
|
| 462 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 463 |
|
|
date_m <= #1 wb_dat_i[`RTC_RRTC_DATE_M];
|
| 464 |
|
|
else if (one_date_m)
|
| 465 |
|
|
date_m <= #1 4'h1;
|
| 466 |
|
|
else if (rst_date_m)
|
| 467 |
|
|
date_m <= #1 4'h0;
|
| 468 |
|
|
else if (inc_date_m)
|
| 469 |
|
|
date_m <= #1 date_m + 1;
|
| 470 |
|
|
|
| 471 |
|
|
//
|
| 472 |
|
|
// RRTC_DATE[TM]
|
| 473 |
|
|
//
|
| 474 |
|
|
always @(posedge lo_clk)
|
| 475 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 476 |
|
|
date_tm <= #1 wb_dat_i[`RTC_RRTC_DATE_TM];
|
| 477 |
|
|
else if (rst_date_tm)
|
| 478 |
|
|
date_tm <= #1 1'b0;
|
| 479 |
|
|
else if (inc_date_tm)
|
| 480 |
|
|
date_tm <= #1 date_tm + 1;
|
| 481 |
|
|
|
| 482 |
|
|
//
|
| 483 |
|
|
// RRTC_DATE[Y]
|
| 484 |
|
|
//
|
| 485 |
|
|
always @(posedge lo_clk)
|
| 486 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 487 |
|
|
date_y <= #1 wb_dat_i[`RTC_RRTC_DATE_Y];
|
| 488 |
|
|
else if (rst_date_y)
|
| 489 |
|
|
date_y <= #1 4'b0;
|
| 490 |
|
|
else if (inc_date_y)
|
| 491 |
|
|
date_y <= #1 date_y + 1;
|
| 492 |
|
|
|
| 493 |
|
|
//
|
| 494 |
|
|
// RRTC_DATE[TY]
|
| 495 |
|
|
//
|
| 496 |
|
|
always @(posedge lo_clk)
|
| 497 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 498 |
|
|
date_ty <= #1 wb_dat_i[`RTC_RRTC_DATE_TY];
|
| 499 |
|
|
else if (rst_date_ty)
|
| 500 |
|
|
date_ty <= #1 4'b0;
|
| 501 |
|
|
else if (inc_date_ty)
|
| 502 |
|
|
date_ty <= #1 date_ty + 1;
|
| 503 |
|
|
|
| 504 |
|
|
//
|
| 505 |
|
|
// RRTC_DATE[C]
|
| 506 |
|
|
//
|
| 507 |
|
|
always @(posedge lo_clk)
|
| 508 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 509 |
|
|
date_c <= #1 wb_dat_i[`RTC_RRTC_DATE_C];
|
| 510 |
|
|
else if (rst_date_c)
|
| 511 |
|
|
date_c <= #1 4'b0;
|
| 512 |
|
|
else if (inc_date_c)
|
| 513 |
|
|
date_c <= #1 date_c + 1;
|
| 514 |
|
|
|
| 515 |
|
|
//
|
| 516 |
|
|
// RRTC_DATE[TC]
|
| 517 |
|
|
//
|
| 518 |
|
|
always @(posedge lo_clk)
|
| 519 |
|
|
if (rrtc_date_sel && wb_we_i)
|
| 520 |
|
|
date_tc <= #1 wb_dat_i[`RTC_RRTC_DATE_TC];
|
| 521 |
|
|
else if (rst_date_tc)
|
| 522 |
|
|
date_tc <= #1 4'b0;
|
| 523 |
|
|
else if (inc_date_tc)
|
| 524 |
|
|
date_tc <= #1 date_tc + 1;
|
| 525 |
|
|
|
| 526 |
|
|
//
|
| 527 |
|
|
// Read RTC registers
|
| 528 |
|
|
//
|
| 529 |
|
|
always @(wb_adr_i or rrtc_time or rrtc_date or rrtc_talrm or rrtc_dalrm or rrtc_ctrl)
|
| 530 |
|
|
case (wb_adr_i[`RTC_OFS_BITS]) // synopsys full_case parallel_case
|
| 531 |
|
|
`ifdef RTC_READREGS
|
| 532 |
|
|
`RTC_RRTC_TIME: wb_dat_o[dw-1:0] <= {{dw-27{1'b0}}, rrtc_time};
|
| 533 |
|
|
`RTC_RRTC_DATE: wb_dat_o[dw-1:0] <= {{dw-27{1'b0}}, rrtc_date};
|
| 534 |
|
|
`RTC_RRTC_TALRM: wb_dat_o[dw-1:0] <= rrtc_talrm;
|
| 535 |
|
|
`RTC_RRTC_DALRM: wb_dat_o[dw-1:0] <= {{dw-31{1'b0}}, rrtc_dalrm};
|
| 536 |
|
|
`endif
|
| 537 |
|
|
default: wb_dat_o <= rrtc_ctrl;
|
| 538 |
|
|
endcase
|
| 539 |
|
|
|
| 540 |
|
|
//
|
| 541 |
|
|
// Asserted high when correspoding RRTC_TIME/DATE fields match
|
| 542 |
|
|
// RRTC_T/DALRM fields
|
| 543 |
|
|
//
|
| 544 |
|
|
assign match_tos = (time_tos == rrtc_talrm[`RTC_RRTC_TALRM_TOS]);
|
| 545 |
|
|
assign match_secs = (time_s == rrtc_talrm[`RTC_RRTC_TALRM_S]) &
|
| 546 |
|
|
(time_ts == rrtc_talrm[`RTC_RRTC_TALRM_TS]);
|
| 547 |
|
|
assign match_mins = (time_m == rrtc_talrm[`RTC_RRTC_TALRM_M]) &
|
| 548 |
|
|
(time_tm == rrtc_talrm[`RTC_RRTC_TALRM_TM]);
|
| 549 |
|
|
assign match_hrs = (time_h == rrtc_talrm[`RTC_RRTC_TALRM_H]) &
|
| 550 |
|
|
(time_th == rrtc_talrm[`RTC_RRTC_TALRM_TH]);
|
| 551 |
|
|
assign match_dow = (time_dow == rrtc_talrm[`RTC_RRTC_TALRM_DOW]);
|
| 552 |
|
|
assign match_days = (date_d == rrtc_dalrm[`RTC_RRTC_DALRM_D]) &
|
| 553 |
|
|
(date_td == rrtc_dalrm[`RTC_RRTC_DALRM_TD]);
|
| 554 |
|
|
assign match_months = (date_m == rrtc_dalrm[`RTC_RRTC_DALRM_M]) &
|
| 555 |
|
|
(date_tm == rrtc_dalrm[`RTC_RRTC_DALRM_TM]);
|
| 556 |
|
|
assign match_yrs = (date_y == rrtc_dalrm[`RTC_RRTC_DALRM_Y]) &
|
| 557 |
|
|
(date_ty == rrtc_dalrm[`RTC_RRTC_DALRM_TY]);
|
| 558 |
|
|
assign match_cents = (date_c == rrtc_dalrm[`RTC_RRTC_DALRM_C]) &
|
| 559 |
|
|
(date_tc == rrtc_dalrm[`RTC_RRTC_DALRM_TC]);
|
| 560 |
|
|
|
| 561 |
|
|
//
|
| 562 |
|
|
// Generate an alarm when all enabled match conditions are asserted high
|
| 563 |
|
|
//
|
| 564 |
|
|
assign alarm = (match_tos | ~rrtc_talrm[`RTC_RRTC_TALRM_CTOS]) &
|
| 565 |
|
|
(match_secs | ~rrtc_talrm[`RTC_RRTC_TALRM_CS]) &
|
| 566 |
|
|
(match_mins | ~rrtc_talrm[`RTC_RRTC_TALRM_CM]) &
|
| 567 |
|
|
(match_hrs | ~rrtc_talrm[`RTC_RRTC_TALRM_CH]) &
|
| 568 |
|
|
(match_dow | ~rrtc_talrm[`RTC_RRTC_TALRM_CDOW]) &
|
| 569 |
|
|
(match_days | ~rrtc_dalrm[`RTC_RRTC_DALRM_CD]) &
|
| 570 |
|
|
(match_months | ~rrtc_dalrm[`RTC_RRTC_DALRM_CM]) &
|
| 571 |
|
|
(match_yrs | ~rrtc_dalrm[`RTC_RRTC_DALRM_CY]) &
|
| 572 |
|
|
(match_cents | ~rrtc_dalrm[`RTC_RRTC_DALRM_CC]) &
|
| 573 |
|
|
(rrtc_talrm[`RTC_RRTC_TALRM_CTOS] |
|
| 574 |
|
|
rrtc_talrm[`RTC_RRTC_TALRM_CS] |
|
| 575 |
|
|
rrtc_talrm[`RTC_RRTC_TALRM_CM] |
|
| 576 |
|
|
rrtc_talrm[`RTC_RRTC_TALRM_CH] |
|
| 577 |
|
|
rrtc_talrm[`RTC_RRTC_TALRM_CDOW] |
|
| 578 |
|
|
rrtc_dalrm[`RTC_RRTC_DALRM_CD] |
|
| 579 |
|
|
rrtc_dalrm[`RTC_RRTC_DALRM_CM] |
|
| 580 |
|
|
rrtc_dalrm[`RTC_RRTC_DALRM_CY] |
|
| 581 |
|
|
rrtc_dalrm[`RTC_RRTC_DALRM_CC]);
|
| 582 |
|
|
|
| 583 |
|
|
//
|
| 584 |
|
|
// Generate an interrupt request
|
| 585 |
|
|
//
|
| 586 |
|
|
assign wb_inta_o = rrtc_ctrl[`RTC_RRTC_CTRL_ALRM] & rrtc_ctrl[`RTC_RRTC_CTRL_INTE];
|
| 587 |
|
|
|
| 588 |
|
|
//
|
| 589 |
|
|
// Control of counters:
|
| 590 |
|
|
// Asserted high when correspoding RRTC_TIME/DATE fields reach
|
| 591 |
|
|
// boundary values and previous counters are cleared
|
| 592 |
|
|
//
|
| 593 |
|
|
assign rst_time_tos = (time_tos == 4'd9) | rrtc_ctrl[`RTC_RRTC_CTRL_BTOS] | wb_rst_i;
|
| 594 |
|
|
assign rst_time_s = (time_s == 4'd9) & rst_time_tos | wb_rst_i;
|
| 595 |
|
|
assign rst_time_ts = (time_ts == 3'd5) & rst_time_s | wb_rst_i;
|
| 596 |
|
|
assign rst_time_m = (time_m == 4'd9) & rst_time_ts | wb_rst_i;
|
| 597 |
|
|
assign rst_time_tm = (time_tm == 3'd5) & rst_time_m | wb_rst_i;
|
| 598 |
|
|
assign rst_time_h = (time_h == 4'd9) & rst_time_tm
|
| 599 |
|
|
| (time_th == 2'd2) & (time_h == 4'd3) & rst_time_tm
|
| 600 |
|
|
| wb_rst_i;
|
| 601 |
|
|
assign rst_time_th = (time_th == 2'd2) & rst_time_h | wb_rst_i;
|
| 602 |
|
|
assign rst_time_dow = (time_dow == 3'd7) & rst_time_th | wb_rst_i;
|
| 603 |
|
|
assign one_date_d =
|
| 604 |
|
|
({date_tm, date_m} == 8'h01 & date_td == 2'd3 & date_d == 4'd1 |
|
| 605 |
|
|
{date_tm, date_m} == 8'h02 & date_td == 2'd2 & date_d == 4'd8 & ~leapyear |
|
| 606 |
|
|
{date_tm, date_m} == 8'h02 & date_td == 2'd2 & date_d == 4'd9 & leapyear |
|
| 607 |
|
|
{date_tm, date_m} == 8'h03 & date_td == 2'd3 & date_d == 4'd1 |
|
| 608 |
|
|
{date_tm, date_m} == 8'h04 & date_td == 2'd3 & date_d == 4'd0 |
|
| 609 |
|
|
{date_tm, date_m} == 8'h05 & date_td == 2'd3 & date_d == 4'd1 |
|
| 610 |
|
|
{date_tm, date_m} == 8'h06 & date_td == 2'd3 & date_d == 4'd0 |
|
| 611 |
|
|
{date_tm, date_m} == 8'h07 & date_td == 2'd3 & date_d == 4'd1 |
|
| 612 |
|
|
{date_tm, date_m} == 8'h08 & date_td == 2'd3 & date_d == 4'd1 |
|
| 613 |
|
|
{date_tm, date_m} == 8'h09 & date_td == 2'd3 & date_d == 4'd0 |
|
| 614 |
|
|
{date_tm, date_m} == 8'h10 & date_td == 2'd3 & date_d == 4'd1 |
|
| 615 |
|
|
{date_tm, date_m} == 8'h11 & date_td == 2'd3 & date_d == 4'd0 |
|
| 616 |
|
|
{date_tm, date_m} == 8'h12 & date_td == 2'd3 & date_d == 4'd1 ) & rst_time_th |
|
| 617 |
|
|
wb_rst_i;
|
| 618 |
|
|
assign rst_date_d = date_d == 4'd9 & rst_time_th;
|
| 619 |
|
|
assign rst_date_td = ({date_tm, date_m} == 8'h02 & date_td[1] |
|
| 620 |
|
|
date_td == 2'h3) & (rst_date_d | one_date_d) |
|
| 621 |
|
|
wb_rst_i;
|
| 622 |
|
|
assign one_date_m = date_tm & (date_m == 4'd2) & rst_date_td | wb_rst_i;
|
| 623 |
|
|
assign rst_date_m = ~date_tm & (date_m == 4'd9) & rst_date_td;
|
| 624 |
|
|
assign rst_date_tm = date_tm & (rst_date_m | one_date_m) | wb_rst_i;
|
| 625 |
|
|
assign rst_date_y = (date_y == 4'd9) & rst_date_tm | wb_rst_i;
|
| 626 |
|
|
assign rst_date_ty = (date_ty == 4'd9)& rst_date_y | wb_rst_i;
|
| 627 |
|
|
assign rst_date_c = (date_c == 4'd9) & rst_date_ty | wb_rst_i;
|
| 628 |
|
|
assign rst_date_tc = (date_tc == 4'd9) & rst_date_c | wb_rst_i;
|
| 629 |
|
|
|
| 630 |
|
|
//
|
| 631 |
|
|
// Control for counter increment
|
| 632 |
|
|
//
|
| 633 |
|
|
assign inc_time_tos = rrtc_ctrl[`RTC_RRTC_CTRL_EN] & ~rrtc_ctrl[`RTC_RRTC_CTRL_BTOS];
|
| 634 |
|
|
assign inc_time_s = rst_time_tos | rrtc_ctrl[`RTC_RRTC_CTRL_BTOS] & rrtc_ctrl[`RTC_RRTC_CTRL_EN];
|
| 635 |
|
|
assign inc_time_ts = rst_time_s;
|
| 636 |
|
|
assign inc_time_m = rst_time_ts;
|
| 637 |
|
|
assign inc_time_tm = rst_time_m;
|
| 638 |
|
|
assign inc_time_h = rst_time_tm;
|
| 639 |
|
|
assign inc_time_th = rst_time_h;
|
| 640 |
|
|
assign inc_time_dow = rst_time_th;
|
| 641 |
|
|
assign inc_date_d = rst_time_th;
|
| 642 |
|
|
assign inc_date_td = rst_date_d;
|
| 643 |
|
|
assign inc_date_m = rst_date_td;
|
| 644 |
|
|
assign inc_date_tm = rst_date_m;
|
| 645 |
|
|
assign inc_date_y = rst_date_tm;
|
| 646 |
|
|
assign inc_date_ty = rst_date_y;
|
| 647 |
|
|
assign inc_date_c = rst_date_ty;
|
| 648 |
|
|
assign inc_date_tc = rst_date_c;
|
| 649 |
|
|
|
| 650 |
|
|
//
|
| 651 |
|
|
// Leap year calculation
|
| 652 |
|
|
//
|
| 653 |
|
|
assign leapyear =
|
| 654 |
|
|
(({date_ty, date_y} == 8'h00) & // xx00
|
| 655 |
|
|
(( date_tc[0] & ~date_c[3] & (date_c[1:0] == 2'b10)) | // 12xx, 16xx, 32xx ...
|
| 656 |
|
|
(~date_tc[0] & (date_c[1:0] == 2'b00) & // 00xx, 04xx, 08xx, 20xx, 24xx ...
|
| 657 |
|
|
((date_c[3:2] == 2'b01) | ~date_c[2])))) |
|
| 658 |
|
|
(~date_ty[0] & (date_y[1:0] == 2'b00) & ({date_ty, date_y} != 8'h00)) | // xx04, xx08, xx24 ...
|
| 659 |
|
|
(date_ty[0] & (date_y[1:0] == 2'b10)); // xx12, xx16, xx32 ...
|
| 660 |
|
|
|
| 661 |
|
|
|
| 662 |
|
|
`else
|
| 663 |
|
|
|
| 664 |
|
|
//
|
| 665 |
|
|
// When RTC is not implemented, drive all outputs as would when RRTC_CTRL
|
| 666 |
|
|
// is cleared and WISHBONE transfers complete with errors
|
| 667 |
|
|
//
|
| 668 |
|
|
assign wb_inta_o = 1'b0;
|
| 669 |
|
|
assign wb_ack_o = 1'b0;
|
| 670 |
|
|
assign wb_err_o = wb_cyc_i & wb_stb_i;
|
| 671 |
|
|
|
| 672 |
|
|
//
|
| 673 |
|
|
// Read RTC registers
|
| 674 |
|
|
//
|
| 675 |
|
|
assign wb_dat_o = {dw{1'b0}};
|
| 676 |
|
|
|
| 677 |
|
|
`endif
|
| 678 |
|
|
|
| 679 |
|
|
endmodule
|
