OpenCores
URL https://opencores.org/ocsvn/rtcclock/rtcclock/trunk

Subversion Repositories rtcclock

[/] [rtcclock/] [trunk/] [doc/] [src/] [spec.tex] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2
%%
3
%% Filename:    spec.tex
4
%%
5
%% Project:     A Wishbone Controlled Real-Time clock Core
6
%%
7
%% Purpose:     This LaTeX file contains all of the documentation/description
8
%%              currently provided with this FPGA Real-time Clock Core.
9
%%              It's not nearly as interesting as the PDF file it creates,
10
%%              so I'd recommend reading that before diving into this file.
11
%%              You should be able to find the PDF file in the SVN distribution
12
%%              together with this PDF file and a copy of the GPL-3.0 license
13
%%              this file is distributed under.  If not, just type 'make'
14
%%              in the doc directory and it (should) build without a problem.
15
%%
16
%%
17
%% Creator:     Dan Gisselquist
18
%%              Gisselquist Technology, LLC
19
%%
20
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
21
%%
22
%% Copyright (C) 2015, Gisselquist Technology, LLC
23
%%
24
%% This program is free software (firmware): you can redistribute it and/or
25
%% modify it under the terms of  the GNU General Public License as published
26
%% by the Free Software Foundation, either version 3 of the License, or (at
27
%% your option) any later version.
28
%%
29
%% This program is distributed in the hope that it will be useful, but WITHOUT
30
%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
%% for more details.
33
%%
34
%% You should have received a copy of the GNU General Public License along
35
%% with this program.  (It's in the $(ROOT)/doc directory, run make with no
36
%% target there if the PDF file isn't present.)  If not, see
37
%% <http://www.gnu.org/licenses/> for a copy.
38
%%
39
%% License:     GPL, v3, as defined and found on www.gnu.org,
40
%%              http://www.gnu.org/licenses/gpl.html
41
%%
42
%%
43
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
44
\documentclass{gqtekspec}
45
\project{Real-Time Clock}
46
\title{Specification}
47
\author{Dan Gisselquist, Ph.D.}
48 4 dgisselq
\email{dgisselq (at) opencores.org}
49 2 dgisselq
\revision{Rev.~0.1}
50
\begin{document}
51
\pagestyle{gqtekspecplain}
52
\titlepage
53
\begin{license}
54
Copyright (C) \theyear\today, Gisselquist Technology, LLC
55
 
56
This project is free software (firmware): you can redistribute it and/or
57
modify it under the terms of  the GNU General Public License as published
58
by the Free Software Foundation, either version 3 of the License, or (at
59
your option) any later version.
60
 
61
This program is distributed in the hope that it will be useful, but WITHOUT
62
ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
63
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
64
for more details.
65
 
66
You should have received a copy of the GNU General Public License along
67
with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a
68
copy.
69
\end{license}
70
\begin{revisionhistory}
71 7 dgisselq
0.3 & 11/07/2015 & Gisselquist & RTC--Light, and RTC--GPS added\\\hline
72 5 dgisselq
0.2 & 7/11/2015 & Gisselquist & Date interface added\\\hline
73 2 dgisselq
0.1 & 5/25/2015 & Gisselquist & First Draft \\\hline
74
\end{revisionhistory}
75
% Revision History
76
% Table of Contents, named Contents
77
\tableofcontents
78
% \listoffigures
79
\listoftables
80
\begin{preface}
81
Every FPGA project needs to start with a very simple core.  Then, working
82
from simplicity, more and more complex cores can be built until an eventual
83
application comes from all the tiny details.
84
 
85 5 dgisselq
This real time clock began with one such simple core.  All of the pieces to
86
this clock are simple.  Nothing is inherently complex.  However, placing this
87 2 dgisselq
clock into a larger FPGA structure requires a Wishbone bus, and being able
88
to command and control an FPGA over a wishbone bus is an achievement in
89
itself.  Further, the clock produces seven segment display output values
90
and LED output values.  These are also simple outputs, but still take a lot
91
of work to complete.  Finally, this clock will strobe an interrupt line.
92
Reading and processing that interrupt line requires a whole 'nuther bit of
93
logic and the ability to capture, recognize, and respond to interrupts.
94
Hence, once you get a simple clock working, you have a lot working.
95
\end{preface}
96
 
97
\chapter{Introduction}
98
\pagenumbering{arabic}
99
\setcounter{page}{1}
100
 
101
This Real--Time Clock implements a twenty four hour clock, count-down timer,
102 5 dgisselq
stopwatch and alarm.  It is designed to be configurable to adjust to whatever
103
clock speed the underlying architecture is running on, so with only minor
104
changes should run on any fundamental clock rate from about 66~kHz on up to
105 2 dgisselq
250~TeraHertz with varying levels of accuracy along the way.
106
 
107 5 dgisselq
Distributed with this clock is a similar Real--Time Date module.  This
108
second module can track the day, month, and year while properly accounting
109 7 dgisselq
for varying days in each month and leap years, when they happen.  Also
110
distributed with the clock are a light version of the clock, offering no
111
LED nor seven segment display capability, and a GPS version, with an
112
interface allowing it to be synchronized to a GPS module.
113 2 dgisselq
 
114 5 dgisselq
Together, the clock and date module offer a fairly full feature set of
115
capability: date, time, alarms, a countdown timer and a stopwatch, all
116
features which are available from the wishbone bus.
117
 
118 2 dgisselq
Other interfaces exist as well.
119
 
120 5 dgisselq
Should you wish to investigate your clock's stability or try to guarantee
121
its fine precision accuracy, it is possible to provide a time hack pulse to
122
the clock and subsequently read what all of the internal registers were set
123
to at that time.
124 2 dgisselq
 
125
When either the count--down timer reaches zero or the clock reaches the alarm
126 5 dgisselq
time (if set), the clock module will produce an impulse which can be used as
127
an interrupt trigger.
128 2 dgisselq
 
129
This clock will also provide outputs sufficient to drive an external seven
130
segment display driver and 16 LED's.
131
 
132
Future enhancements may allow for button control and fine precision clock
133
adjustment.
134
 
135
The layout of this specification follows the format set by OpenCores.
136
This introduction is the first chapter.  Following this introduction is
137
a short chapter describing how this clock is implemented,
138
Chapt.~\ref{chap:arch}.  Following this description, the Chapt.~\ref{chap:ops}
139
gives a brief overview of how to operate the clock.  Most of the details,
140
however, are in the registers and their definitions.  These you can find in
141
Chapt.~\ref{chap:regs}.  As for the wishbone, the wishbone spec requires a
142
wishbone datasheet which you can find in Chapt.~\ref{chap:wishbone}.
143
That leaves the final pertinent information necessary for implementing this
144
core in Chapt.~\ref{chap:ioports}, the definitions and meanings of the
145
various I/O ports.
146
 
147
As always, write me if you have any questions or problems.
148
 
149
\chapter{Architecture}\label{chap:arch}
150
 
151
Central to this real time clock architecture is a 48~bit sub--second register.
152
This register is incremented every clock by a user defined 32~bit value,
153 5 dgisselq
{\tt CKSPEED}.  When the register turns over at the end of each second, a
154
second has taken place and all of the various clock (and date) registers are
155
adjusted.
156 2 dgisselq
 
157
Well, not quite but almost.  The 48~bit register is actually split into a
158
lower 40~bit register that is common to all clock components, as well as
159
separate eight bit upper registers for the clock, timer, and stopwatch.  In
160
this fashion, these separate components can have different definitions for
161
when seconds begin and end, and with sufficient precision to satisfy most
162
applications.
163
 
164
The next thing to note about this architecture is the format of the various
165
clock registers: Binary Coded Decimal, or BCD.  Hence an {\tt 8'h59} refers
166
to a value of 59, rather than 89.  In this fashion, setting the time to
167
{\tt 24'h231520} will set it to 23~hours, 15~minutes, and 20~seconds.  The
168
only exception to this BCD format are the subseconds fields found in the
169
stopwatch and time hack registers.  Seconds and above are all encoded as BCD.
170
 
171
\chapter{Operation}\label{chap:ops}
172
 
173
\section{Time}
174
To set the time, simply write to the clock register the current value of the
175
time.  If the seconds hand is written as zero, subsecond time will be cleared
176
as well.  The new clock value takes place one clock period after the value
177
is written to the bus.
178
 
179
To set only some parts of the time and not others, such as the minutes but
180
not seconds or hours, write all '1's to the seconds and hours.  In this way,
181
writing a {\tt 24'h3f17ff} will set the minutes to 17, but not affect the
182
rest of the clock.
183
 
184
This is also the way to adjust the display without adjusting time.  Suppose
185
you wish to switch to display option '1', just write a {\tt 32'h013fffff} to
186
the register and the display will switch without adjusting time.
187
 
188
\section{Count-down Timer}
189
To use the count down timer, set it to the amount of time you wish to count
190
down for.  When ready, or even in the same cycle, enable the count--down
191
timer by setting the RUN bit high.  At this point in time, the count--down
192
timer is running.  When it gets to zero, it will stop and trigger an interrupt.
193
You can tell if the alarm has been triggered by the TRIGGER bit being set.
194
Any write to the timer register will clear the alarm condition.
195
 
196
While the timer is running, writing a '0' to the timer register will stop it
197
without clearing the time remaining.  In this state, writing to the register
198
the RUN bit by itself will restart the timer, while anything else will set the
199
timer to a new value.  Further, if the timer is stopped at zero, then writing
200
zero to the timer will reset the timer to the last start time it had.
201
 
202
\section{Stopwatch}
203
The stop watch supports three operations: start, stop, and clear.  Writing a
204
'1' to the stop watch register will start the stopwatch, while writing a '0'
205
will stop it.  When it starts next, it will start where it left off unless the
206
register is cleared.  To clear the register and set it back to zero, write a
207
'2' to the register.  This will effectively stop the register and clear it in
208
one step.  If the register is already stopped, writing a '3' will clear and
209
start it in one step.  However, the register can only be cleared while stopped.
210
If the register is running, writing a '3' will have no effect.
211
 
212
\section{Alarm}
213
To set the alarm, just write the alarm time to the alarm register together
214
with alarm enable bit.  As with the time register, setting any field,
215
whether hours, minutes, or seconds, to {\tt 8'hff} has no effect on that
216
field.  Hence, the alarm may be activated by writing {\tt 25'h13fffff} to
217
the register and deactivated by writing {\tt 25'h03fffff}.
218
 
219
Once the alarm is tripped, the RTC core will generate an interrupt.  Further,
220
the tripped bit in the alarm register will be set.  To clear this bit and the
221
alarm tripped condition, either disable the alarm or write a '1' to this bit.
222
 
223
\section{Time Hacks}
224
 
225
For finer precision timing, the RTC module allows for setting a time
226
hack and reading the value from the device.  On the clock following the
227
time hack being high, the internal state, to include the time and the 48~bit
228
counter, will be recorded and may then be read out.  In this fashion,
229
it is possible to capture, with as much precision as the device offers,
230
the current time within the device.
231
 
232
It is the users responsibility to read the time hack registers before a
233
subsequent time hack pulse sets them to new values.
234
 
235 5 dgisselq
\section{Date}
236
The Real--Time Date module is really a separate module from the Real--Time
237
Clock module, but that doesn't prevent it from working just like the others.
238
To set the date, just write the new date value to the address of the date.
239
Further, as with the clock time, setting any particular field of the date to
240
all ones, such as setting the month to {\tt 8'hff}, will cause that portion of
241
the date to retain it's current value.  In this way, one part of the date
242
may be set and not others.
243
 
244 7 dgisselq
\section{RTC--Light}
245
The RTC Light module is nearly identical to the RTC clock module, save that
246
it has been simplified for environments that have neither LED outputs nor
247
seven segment display to drive.  Further, the time hack registers have been
248
replaced with read--only zero producing registers.  Further, if the high
249
order bit of the wishbone address is fixed to zero, the clock speed will no
250
longer be adjustable--reducing the logic even further.
251
 
252
This module is independent of the RTC clock module.
253
 
254
\section{RTC GPS}
255
As part of a GPS driven RTC solution, the RTC GPS module is provided.  This
256
module will use an externally provided PPS signal, one clock pulse wide and
257
synchronized with the system clock, as well as an externally provided
258
clock speed register.  It has no time hack capability.  Further, when the
259
external GPS valid line is true, these additional two inputs will drive the
260
clock.
261
 
262
Operating this clock requires a variety of external GPS circuitry: a clocked
263
PPS generator to generate both the PPS signal and the system clock speed
264
reference, and a serial port processor to read the GPS time from the
265
NMEA stream and to set the time value.  With these external circuits, this
266
clock will then have sub--millisecond accuracy.
267
 
268 2 dgisselq
\chapter{Registers}\label{chap:regs}
269
This RTC clock module supports eight registers, as listed in
270
Tbl.~\ref{tbl:reglist}.  Of these eight, the first four have been so placed
271
as to be the more routine or user used registers, while the latter four are
272
more lower level.
273
\begin{table}[htbp]
274
\begin{center}
275
\begin{reglist}
276
CLOCK   & 0 & 32 & R/W & Wall clock time register\\\hline
277
TIMER   & 1 & 32 & R/W & Count--down timer\\\hline
278
STPWTCH & 2 & 32 & R/W & Stopwatch control and value\\\hline
279
ALARM   & 3 & 32 & R/W & Alarm time, and setting\\\hline\hline
280
CKSPEED & 4 & 32 & R/W & Clock speed control.\\\hline
281
HACKTIME &5 & 32 & R & Wall clock time at last hack.\\\hline
282
HACKCNTHI&6 & 32 & R & Wall clock time.\\\hline
283
HACKCNTLO&7 & 32 & R & Wall clock time.\\\hline
284
\end{reglist}\caption{List of Registers}\label{tbl:reglist}
285
\end{center}\end{table}
286
Each register will be discussed in detail in this chapter.
287
 
288 7 dgisselq
The Date module supports its own register, listed in
289 5 dgisselq
Tbl.~\ref{tbl:datereg}.
290
\begin{table}[htbp]
291
\begin{center}
292
\begin{reglist}
293
DATE    & 0 & 32 & R/W & Calendar date register\\\hline
294
\end{reglist}\caption{Date Register}\label{tbl:datereg}
295
\end{center}\end{table}
296
This register will be discussed after we discuss the time registers.
297
 
298 2 dgisselq
\section{Clock Time Register}
299
The various bit fields associated with the current time may be found in
300
the {\tt CLOCK} register, shown in Tbl.~\ref{tbl:clockreg}.
301
\begin{table}[htbp]\begin{center}
302
\begin{bitlist}
303 7 dgisselq
26--31 & R & Always return zero.\\\hline
304
24--25 & R/W & Seven Segment Display Mode.\\\hline
305 2 dgisselq
22--23 & R & Always return zero.\\\hline
306
16--21 & R/W & Current time, BCD hours\\\hline
307
8--15 & R/W & Current time, BCD minutes\\\hline
308
0--7 & R/W & Current time, BCD seconds\\\hline
309
\end{bitlist}
310
\caption{Clock Time Register Bit Definitions}\label{tbl:clockreg}
311
\end{center}\end{table}
312
This register contains six clock digits: two each for hours, minutes, and
313
seconds.  Each of these digits is encoded in Binary Coded Decimal (BCD).
314
Therefore, 23~hours would be encoded as 6'h23 and not 6'h17.  Writes to each
315
of the various subcomponent registers will set that register, unless the
316
write value is a 8'hff.  The behaviour of the clock when non--decimal
317
values are written, other than all F's, is undefined.
318
 
319
Separate from the time, however, is the seven segment display mode.  Four
320 7 dgisselq
values are currently supported: 2'h0 to display the hours and minutes,
321
2'h1 to display the timer in minutes and seconds, 2'h2 to display the
322 2 dgisselq
stopwatch in lower order minutes, seconds, and sixteenths of a second, and
323 7 dgisselq
2'h3 to display the minutes and seconds of the current time.  In all cases,
324 2 dgisselq
the decimal point will appear to the right of the lowest order digit
325
and will blink with the second hand.  That is, the decimal will be high for
326
the second half of any second, and low at the top of the second.
327
 
328 7 dgisselq
In the case of the RTC light, the seven segment display controller bits have
329
been wired to zeros.
330
 
331
In the case of the RTC modified for GPS, the most significant bit \#31 has
332
been modified to produce a zero if the GPS lock signal is true, or a one
333
for an error condition.
334
 
335 2 dgisselq
\section{Countdown Timer Register}
336
The countdown timer register, whose bit--wise values are shown in
337
Tbl.~\ref{tbl:timer},
338
\begin{table}[htbp]
339
\begin{center}
340
\begin{bitlist}
341
26--31 & R & Unused, always read as '0'.\\\hline
342
25 & R/W & Alarm condition.  Write a '1' to clear.\\\hline
343
24 & R/W & Running, stopped on '0'\\\hline
344
16--23 & R/W & BCD Hours\\\hline
345
8--15 & R/W & BCD Minutes\\\hline
346
0--7 & R/W & BCD Seconds\\\hline
347
\end{bitlist}
348
\caption{Count--down Timer register}\label{tbl:timer}
349
\end{center}\end{table}
350
controls the operation of the count--down timer.  To use this timer, write
351
some amount of time to the register, then write zeros with bit 24 set.  The
352
register will then reach an alarm condition after counting down that amount
353
of time.  (Alternatively, you could set bit 24 while writing the register,
354
to set and start it in one operation.)  To stop the register while it is
355
running, just write all zeros.  To restart the register, provided more than a
356
second remains, write a {\tt 26'h1000000} to set it running again.  Once
357
the timer alarms, the timer will stop and the alarm condition will be set.
358
Any write to the timer register after the alarm condition has been set will
359
clear the alarm condition.
360
 
361
\section{Stopwatch Register}
362
The various bits of the stopwatch register are shown in
363
Tbl.~\ref{tbl:stopwatch}.
364
\begin{table}[htbp]
365
\begin{center}
366
\begin{bitlist}
367
24--31 & R & Hours\\\hline
368
16--23 & R & Minutes\\\hline
369
8--15 & R & Sub Seconds\\\hline
370
1--7 & R & Sub Seconds\\\hline
371
1 & W & Clear\\\hline
372
 
373
\end{bitlist}
374
\caption{Stopwatch Register}\label{tbl:stopwatch}
375
\end{center}\end{table}
376
Of note is the bottom bit that, when set, means the stop watch is running.
377
Set this bit to '1' to start the stopwatch, or to '0' to stop the stopwatch.
378
Further, while the stopwatch is stopped, a '1' can be written to the clear
379
bit.  This will zero out the stopwatch and set it back to zero.
380
 
381
\section{Alarm Register}
382
The various bits of the alarm register are shown in Tbl.~\ref{tbl:alarm}.
383
\begin{table}[htbp]
384
\begin{center}
385
\begin{bitlist}
386
26--31 & R & Always reads zeros. \\\hline
387
25 & R/W & Alarm tripped.  Write a '1' to this register to clear any alarm
388
        condition.  (A tripped alarm will not trip again.)\\\hline
389
24 & R/W & Alarm enabled\\\hline
390
16--23 & R & Alarm time, BCD hours\\\hline
391
8--15 & R & Alarm time, BCD minutes\\\hline
392
0--7 & R/W & Alarm time, BCD Seconds\\\hline
393
\end{bitlist}
394
\caption{Alarm Register}\label{tbl:alarm}
395
\end{center}\end{table}
396
Basically, the alarm register consists a time and two more bits.  The extra
397
two bits encode whether or not the alarm is enabled, and whether or not it has
398
been tripped.  The alarm will be {\em tripped} whenever it is enabled, and the
399
time changes to equal the alarm time.  Once tripped, the alarm will stay
400
in the alarmed or tripped condition until either a '1' is written to the
401
tripped bit, or the alarm is disabled.
402
 
403
As with the clock and timer registers, writing eight ones to any of the
404
BCD fields when writing to this register will leave those fields untouched.
405
 
406
\section{Clock Speed Register}
407
The actual speed of the clock is controlled by the {\tt CKSPEED} register,
408
shown in Tbl.~\ref{tbl:ckspeed}.
409
\begin{table}[htbp]
410
\begin{center}
411
\begin{bitlist}
412
0--31 & R/W & 48~bit counter time increment\\\hline
413
\end{bitlist}
414
\caption{Clock Speed Register}\label{tbl:ckspeed}
415
\end{center}\end{table}
416
This register contains a simple 32~bit unsigned value.  To step the clock,
417
this value is extended to 48~bits and added to the fractional seconds value.
418
 
419
This value should be set to $2^{48}$ divided by the clock frequency of the
420
controlling clock.  Hence, for a 100~MHz clock, this value would be set to
421
{\tt 32'd2814750}.  For clocks near 100~MHz, this allows adjusting speed
422
within about 40~clocks per second.  For clocks near 500~MHz, this allows
423
time adjustment to an accuracy of about about 800~clocks per second.  In
424
both cases, this is good enough to maintain a clock with less than a
425
microsecond loss over the course of a year.  Hence, this RTC module provides
426
more logical stability than most hardware clocks on the market today.
427
 
428
\section{Time--hack time}
429
To support finer precision clock control, the time--hack capability exists.
430
This capability consists of three registers, the time--hack time register
431
shown in Tbl.~\ref{tbl:hacktime},
432
\begin{table}[htbp]
433
\begin{center}
434
\begin{bitlist}
435
24--31 & R & BCD Hours.\\\hline
436
16--23 & R & BCD Minutes.\\\hline
437
8--15 & R & BCD seconds.\\\hline
438
0--7 & R & Subseconds, encoded in 256ths of a second\\\hline
439
\end{bitlist}
440
\caption{Time Hack Time Register}\label{tbl:hacktime}
441
\end{center}\end{table}
442
and two registers (Tbls.~\ref{tbl:hackcnthi}
443
\begin{table}[htbp]
444
\begin{center}
445
\begin{bitlist}
446
0--31 & R & Upper 32 bits of the internal 40~bit counter.\\\hline
447
\end{bitlist}
448
\caption{Time Hack Counter, High}\label{tbl:hackcnthi}
449
\end{center}\end{table}
450
and~\ref{tbl:hackcntlo})
451
\begin{table}[htbp]
452
\begin{center}
453
\begin{bitlist}
454
24--31 & R & Bottom 8~bits of the internal 40~bit counter.\\\hline
455
0--23 & R & Always read as '0'.\\\hline
456
\end{bitlist}
457
\caption{Time Hack Counter, Low}\label{tbl:hackcntlo}
458
\end{center}\end{table}
459
capturing the contents of the 40~bit internal counter at the time of the hack.
460
 
461
The time--hack time register is perhaps the simplest to understand.  This
462
captures the time of the time--hack in hours, minutes, seconds, and 8~fractional
463
subsecond bits.  The top 24~bits of this register will match the bottom 24~bits
464
of the clock~time register at the time of the time hack.  The bottom eight
465
bits are the top eight bits of the 48~bit subsecond time counter.  The
466
rest of those 48~bits may then be returned in the other two time hack counter
467
registers.
468
 
469
At present, this functionality isn't yet truly fully featured.  Once fully
470
featured, there will (should) be a mechanism for adjusting this counter based
471
upon information gleaned from the hack time.  Implementation details have
472
to date prevented this portion of the design from being implemented.
473
 
474 5 dgisselq
\section{Date Register}
475
The year, month, and day of month fields may all be found within the
476
{\tt DATE} register of the Real--Time Date module, shown in
477
Tbl.~\ref{tbl:datebits}.
478
\begin{table}[htbp]\begin{center}
479
\begin{bitlist}
480
30--31 & R & Always return zero.\\\hline
481
16--29 & R/W & Four digit BCD year\\\hline
482
13--15 & R & Always return zero.\\\hline
483
8--12 & R/W & Two digit BCD month\\\hline
484
6--7 & R & Always return zero.\\\hline
485
0--5 & R/W & Two digit BCD day of month\\\hline
486
\end{bitlist}
487
\caption{Date Register Bit Definitions}\label{tbl:datebits}
488
\end{center}\end{table}
489
Further, according to the common calendar convention, the minimum day and month
490
are one and not zero.
491
 
492 2 dgisselq
\chapter{Wishbone Datasheet}\label{chap:wishbone}
493
Tbl.~\ref{tbl:wishbone}
494
\begin{table}[htbp]
495
\begin{center}
496
\begin{wishboneds}
497
Revision level of wishbone & WB B4 spec \\\hline
498
Type of interface & Slave, Read/Write \\\hline
499
Port size & 32--bit \\\hline
500
Port granularity & 32--bit \\\hline
501
Maximum Operand Size & 32--bit \\\hline
502
Data transfer ordering & (Irrelevant) \\\hline
503
Clock constraints & Faster than 66~kHz \\\hline
504
Signal Names & \begin{tabular}{ll}
505
                Signal Name & Wishbone Equivalent \\\hline
506
                {\tt i\_clk} & {\tt CLK\_I} \\
507
                {\tt i\_wb\_cyc} & {\tt CYC\_I} \\
508
                {\tt i\_wb\_stb} & {\tt STB\_I} \\
509
                {\tt i\_wb\_we} & {\tt WE\_I} \\
510
                {\tt i\_wb\_addr} & {\tt ADR\_I} \\
511
                {\tt i\_wb\_data} & {\tt DAT\_I} \\
512
                {\tt o\_wb\_ack} & {\tt ACK\_O} \\
513
                {\tt o\_wb\_stall} & {\tt STALL\_O} \\
514
                {\tt o\_wb\_data} & {\tt DAT\_O}
515
                \end{tabular}\\\hline
516
\end{wishboneds}
517
\caption{Wishbone Datasheet}\label{tbl:wishbone}
518
\end{center}\end{table}
519
is required by the wishbone specification, and so
520 5 dgisselq
it is included here.  The big thing to notice is that both the real time clock
521
and the real time date modules act as wishbone slaves, and that all accesses
522
to the registers of either module are 32--bit reads and writes.  The address
523
bus does not offer
524 2 dgisselq
byte level, but rather 32--bit word level resolution.  Select lines are not
525
implemented.  Bit ordering is the normal ordering where bit~31 is the most
526
significant bit and so forth.  Although the stall line is implemented, it is
527
always zero.  Access delays are a single clock, so the clock after a read or
528
write is placed on the bus the {\tt i\_wb\_ack} line will be high.
529
 
530
\iffalse
531
\chapter{Clocks}\label{chap:clocks}
532
 
533
This core is based upon the Basys--3 design.  The Basys--3 development board
534
contains one external 100~MHz clock, which is sufficient to run this
535
core.  The logic within the core can also be run faster, or slower, as is
536
necessary to meet the timing constraints associated with the internal
537
operations of the core and it's surrounding environment.  See
538
Table.~\ref{tbl:clocks}.
539
\begin{table}[htbp]
540
\begin{center}
541
\begin{clocklist}
542
i\_clk & External & 250~THz & 66~kHz & System clock.\\\hline
543
\end{clocklist}
544
\caption{List of Clocks}\label{tbl:clocks}
545
\end{center}\end{table}
546
 
547
\fi
548
 
549
\chapter{I/O Ports}\label{chap:ioports}
550 5 dgisselq
The I/O ports for this clock are shown in Tbls.~\ref{tbl:iowishbone}
551 2 dgisselq
\begin{table}[htbp]
552
\begin{center}
553
\begin{portlist}
554 5 dgisselq
i\_clk & 1 & Input & System clock, used for time and wishbone interfaces.\\\hline
555 2 dgisselq
i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline
556
i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
557
i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
558
i\_wb\_addr & 5 & Input & Wishbone address.\\\hline
559
i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
560
        (configuring) the core from the bus.\\\hline
561
o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or
562
                signifying valid data in the case of a wishbone read request.
563
                \\\hline
564
o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another
565
                wishbone access, effectively stalling the bus.\\\hline
566
o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read
567
                from the interface.\\\hline
568
\end{portlist}
569
\caption{Wishbone I/O Ports}\label{tbl:iowishbone}
570
\end{center}\end{table}
571
and~Tbl.~\ref{tbl:ioother}.
572
\begin{table}[htbp]
573
\begin{center}
574
\begin{portlist}
575
o\_sseg & 32 & Output & Lines to control a seven segment display, to be
576
                sent to that display's driver.  Each eight bit byte controls
577
                one digit in the display, with the bottom bit in the byte
578
                controlling the decimal point.\\\hline
579
o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting
580
                from zero to all ones each minute, and synchronized with each
581
                minute so as to create an indicator of when the next minute
582
                will take place when only the hours and minutes can be
583
                displayed.\\\hline
584
o\_interrupt & 1 & Output & A pulsed/strobed interrupt line.  When the
585
                clock needs to generate an interrupt, it will set this line
586
                high for one clock cycle.  \\\hline
587 5 dgisselq
o\_ppd & 1 & Output & A `pulse per day' signal which can be fed into the
588
        real--time date module.  This line will be high on the clock before
589
        the stroke of midnight, allowing the date module to turn over to the
590
        next day at exactly the same time the clock module turns over to the
591
        next day.\\\hline
592 2 dgisselq
i\_hack & 1 & Input & When this line is raised, copies are made of the
593
        internal state registers on the next clock.  These registers can then
594
        be used for an accurate time hack regarding the state of the clock
595
        at the time this line was strobed.\\\hline
596
\end{portlist}
597
\caption{Other I/O Ports}\label{tbl:ioother}
598
\end{center}\end{table}
599
Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in
600
Chapt.~\ref{chap:wishbone}, and so need no further discussion here.
601
 
602
This clock is designed for command and control via the wishbone.  No other
603
registers, beyond the wishbone bus, are required.  However, several other
604
may be valuable.  These other registers are listed in Tbl.~\ref{tbl:ioother}.
605
We'll discuss each of these in turn.
606
 
607
First of the other I/O registers is the {\tt o\_sseg} register.  This register
608
encodes which outputs of a seven segment display need to be turned on to
609
represent the value of the clock requested.  This register consists of four
610
eight bit bytes, with the highest order byte referencing the highest order
611
display segment value.  In each byte, the low order bit references a decimal
612
point.  The other bits are ordered around the zero, with the top bit being
613
the top bar of a '0', the next highest order bit and so on following the
614
zero clockwise.  The final bit of each byte, the bit in the two's place,
615
encodes whether or not the middle line is to be displayed.  When either timer
616
or alarm is triggered, this display will blink until the triggering conditions
617
are cleared.
618
 
619
This output is expected to be the input to a seven segment display driver,
620
rather than being the output to the display itself.
621
 
622
The next output lines are the 16~lines of the {\tt o\_led} bus.  When connected
623
with 16~LED's, these lines will create a counting display that will count up
624
to each minute, synchronized to the minute.  When either timer or alarm has
625
triggered, all of the LED's will flash together until the triggered condition
626
is reset.
627
 
628
The third other line is the {\tt o\_interrupt} line.  This line will be
629
strobed by the RTC module any time the alarm is triggered or the timer runs
630
out.  The line will not remain high, but neither will it trigger a second
631
time until the underlying interrupt is cleared.  That is, the timer will only
632
trigger once until cleared as will the alarm, but the alarm may trigger after
633
the timer has triggered and before the timer clears.
634
 
635 5 dgisselq
As a fourth additional line, the clock module produces a one pulse per day
636
signal, {\tt o\_ppd}.  This signal is designed to be the only necessary
637
coordinated input between the clock and date module.  Feeding it straight
638
into the date module will keep the two synchronized.
639
 
640 2 dgisselq
The final other I/O line is a simple input line.  This line is expected to be
641
strobed for one clock cycle any time a time hack is required.  For example,
642
should you wish to read and synchronize to a GPS PPS signal, strobe the device
643
with the PPS (after dealing with any metastability issues), and read the time
644
hacks that are produced.
645
 
646 5 dgisselq
The real--time date module has a similar set of I/O ports to the clock.  These
647
are listed in Tbl.~\ref{tbl:iodate}.
648
\begin{table}[htbp]
649
\begin{center}
650
\begin{portlist}
651
i\_clk & 1 & Input & The system clock.\\\hline
652
i\_ppd & 1 & Input & The one pulse per day strobe from the clock module.\\\hline
653
i\_wb\_cyc & 1 & Input & Wishbone bus cycle.\\\hline
654
i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
655
i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
656
i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
657
        (configuring) the core from the bus.\\\hline
658
o\_wb\_ack & 1 & Output & Equal to the bus cycle line anded with the strobe
659
                line, and delayed by one clock---essentially acknowledging any
660
                wishbone access.\\\hline
661
o\_wb\_stall & 1 & Output & Fixed to zer.\\\hline
662
o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read
663
                from the interface.\\\hline
664
\end{portlist}
665
\caption{Wishbone I/O Ports}\label{tbl:iodate}
666
\end{center}\end{table}
667
There are two big things to notice.  The first is the {\tt i\_ppd} signal.
668
This should be connected straight from the clock module's {\tt o\_ppd} signal
669
into this module.  The second difference is the lack of any address lines.
670
This is appropriate since the date module provides a single register only.
671
 
672 2 dgisselq
% Appendices
673
% Index
674
\end{document}
675
 
676
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.