URL https://opencores.org/ocsvn/rtcclock/rtcclock/trunk

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[/] [rtcclock/] [trunk/] [rtl/] [rtcclock.v] - Blame information for rev 2

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///////////////////////////////////////////////////////////////////////////
//
// Filename:    rtcclock.v
//              
// Project:     A Wishbone Controlled Real--time Clock Core
//
// Purpose:     Implement a real time clock, including alarm, count--down
//              timer, stopwatch, variable time frequency, and more.
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
module  rtcclock(i_clk,
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                //      o_wb_ack, o_wb_stb, o_wb_data, // no reads here
                // // Button inputs
                // i_btn,
                // Output registers
                o_data, // multiplexed based upon i_wb_addr
                // Output controls
                o_sseg, o_led, o_interrupt,
                // Time setting hack(s)
                i_hack);
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   [2:0]    i_wb_addr;
        input   [31:0]   i_wb_data;
        // input                i_btn;
        output  reg     [31:0]   o_data;
        output  reg     [31:0]   o_sseg;
        output  wire    [15:0]   o_led;
        output  wire            o_interrupt;
        input                   i_hack;
 
        reg     [31:0]   clock, stopwatch, ckspeed;
        reg     [17:0]   timer;
 
        wire    ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
        assign  ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
        assign  tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
        assign  sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
        assign  al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
        assign  sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
 
        reg     [39:0]   ck_counter;
        reg             ck_carry;
        always @(posedge i_clk)
                { ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
 
        wire            ck_pps;
        reg             ck_prepps, ck_ppm, ck_pph, ck_ppd;
        reg     [7:0]    ck_sub;
        initial clock = 32'h00000000;
        assign  ck_pps = (ck_carry)&&(ck_prepps);
        always @(posedge i_clk)
        begin
                if (ck_carry)
                        ck_sub <= ck_sub + 1;
                ck_prepps <= (ck_sub == 8'hff);
 
                if (ck_pps)
                begin // advance the seconds
                        if (clock[3:0] >= 4'h9)
                                clock[3:0] <= 4'h0;
                        else
                                clock[3:0] <= clock[3:0] + 4'h1;
                        if (clock[7:0] >= 8'h59)
                                clock[7:4] <= 4'h0;
                        else if (clock[3:0] >= 4'h9)
                                clock[7:4] <= clock[7:4] + 4'h1;
                end
                ck_ppm <= (clock[7:0] == 8'h59);
 
                if ((ck_pps)&&(ck_ppm))
                begin // advance the minutes
                        if (clock[11:8] >= 4'h9)
                                clock[11:8] <= 4'h0;
                        else
                                clock[11:8] <= clock[11:8] + 4'h1;
                        if (clock[15:8] >= 8'h59)
                                clock[15:12] <= 4'h0;
                        else if (clock[11:8] >= 4'h9)
                                clock[15:12] <= clock[15:12] + 4'h1;
                end
                ck_pph <= (clock[15:0] == 16'h5959);
 
                if ((ck_pps)&&(ck_pph))
                begin // advance the hours
                        if (clock[21:16] >= 6'h23)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= 2'h0;
                        end else if (clock[19:16] >= 4'h9)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= clock[21:20] + 2'h1;
                        end else begin
                                clock[19:16] <= clock[19:16] + 4'h1;
                        end
                end
                // ppd <= (clock{15:8] == 8'h59);
 
                if ((ck_sel)&&(i_wb_we))
                begin
                        if (8'hff != i_wb_data[7:0])
                        begin
                                clock[7:0] <= i_wb_data[7:0];
                                ck_ppm <= (i_wb_data[7:0] == 8'h59);
                        end
                        if (8'hff != i_wb_data[15:8])
                        begin
                                clock[15:8] <= i_wb_data[15:8];
                                ck_pph <= (i_wb_data[15:8] == 8'h59);
                        end
                        if (6'h3f != i_wb_data[21:16])
                                clock[21:16] <= i_wb_data[21:16];
                        clock[31:22] <= i_wb_data[31:22];
                        if (8'h00 == i_wb_data[7:0])
                                ck_sub <= 8'h00;
                end
        end
 
        // Clock updates take several clocks, so let's make sure we
        // are only looking at a valid clock value before testing it.
        reg     [21:0]           ck_last_clock;
        always @(posedge i_clk)
                ck_last_clock <= clock[21:0];
 
 
        reg     tm_pps, tm_ppm, tm_int;
        wire    tm_stopped, tm_running, tm_alarm;
        assign  tm_stopped = ~timer[24];
        assign  tm_running =  timer[24];
        assign  tm_alarm   =  timer[25];
        reg     [23:0]           tm_start;
        reg     [7:0]            tm_sub;
        initial tm_start = 16'h00;
        initial timer  = 18'h00;
        initial tm_int   = 1'b0;
        initial tm_pps   = 1'b0;
        always @(posedge i_clk)
        begin
                if (ck_carry)
                begin
                        tm_sub <= tm_sub + 1;
                        tm_pps <= (tm_sub == 8'hff);
                end else
                        tm_pps <= 1'b0;
 
                if ((~tm_alarm)&&(tm_running)&&(tm_pps))
                begin // If we are running ...
                        timer[25] <= 1'b0;
                        if (timer[23:0] == 24'h00)
                                timer[25] <= 1'b1;
                        else if (timer[3:0] != 4'h0)
                                timer[3:0] <= timer[3:0]-4'h1;
                        else begin // last digit is a zero
                                timer[3:0] <= 4'h9;
                                if (timer[7:4] != 4'h0)
                                        timer[7:4] <= timer[7:4]-4'h1;
                                else begin // last two digits are zero
                                        timer[7:4] <= 4'h5;
                                        if (timer[11:8] != 4'h0)
                                                timer[11:8] <= timer[11:8]-4'h1;
                                        else begin // last three digits are zero
                                                timer[11:8] <= 4'h9;
                                                if (timer[15:12] != 4'h0)
                                                        timer[15:12] <= timer[15:12]-4'h1;
                                                else begin
                                                        timer[15:12] <= 4'h5;
                                                        if (timer[19:16] != 4'h0)
                                                                timer[19:16] <= timer[19:16]-4'h1;
                                                        else begin
                                                        //
                                                                timer[19:16] <= 4'h9;
                                                                timer[23:20] <= timer[23:20]-4'h1;
                                                        end
                                                end
                                        end
                                end
                        end
                end
 
                if((~tm_alarm)&&(tm_running))
                begin
                        timer[25] <= (timer[23:0] == 24'h00);
                        tm_int <= (timer[23:0] == 24'h00);
                end else tm_int <= 1'b0;
                if (tm_alarm)
                        timer[24] <= 1'b0;
 
                if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
                        // Only allowed to stop the timer, nothing more
                        timer[24] <= i_wb_data[24];
                else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
                begin
                        timer[24] <= i_wb_data[24];
                        if ((timer[24])||(i_wb_data[24]))
                                timer[25] <= 1'b0;
                        if (i_wb_data[23:0] != 24'h0000)
                        begin
                                timer[23:0] <= i_wb_data[23:0];
                                tm_start <= i_wb_data[23:0];
                                tm_sub <= 8'h00;
                        end else if (timer[23:0] == 24'h00)
                        begin // Resetting timer to last valid timer start val
                                timer[23:0] <= tm_start;
                                tm_sub <= 8'h00;
                        end
                        // Any write clears the alarm
                        timer[25] <= 1'b0;
                end
        end
 
        //
        // Stopwatch functionality
        //
        // Setting bit '0' starts the stop watch, clearing it stops it.
        // Writing to the register with bit '1' high will clear the stopwatch,
        // and return it to zero provided that the stopwatch is stopped either
        // before or after the write.  Hence, writing a '2' to the device
        // will always stop and clear it, whereas writing a '3' to the device
        // will only clear it if it was already stopped.
        reg             sw_pps, sw_ppm, sw_pph;
        reg     [7:0]    sw_sub;
        wire    sw_running;
        assign  sw_running = stopwatch[0];
        initial stopwatch = 32'h00001;
        always @(posedge i_clk)
        begin
                sw_pps <= 1'b0;
                if (sw_running)
                begin
                        if (ck_carry)
                        begin
                                sw_sub <= sw_sub + 1;
                                sw_pps <= (sw_sub == 8'hff);
                        end
                end
 
                stopwatch[7:1] <= sw_sub[7:1];
 
                if (sw_pps)
                begin // Second hand
                        if (stopwatch[11:8] >= 4'h9)
                                stopwatch[11:8] <= 4'h0;
                        else
                                stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
 
                        if (stopwatch[15:8] >= 8'h59)
                                stopwatch[15:12] <= 4'h0;
                        else if (stopwatch[11:8] >= 4'h9)
                                stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
                        sw_ppm <= (stopwatch[15:8] == 8'h59);
                end else sw_ppm <= 1'b0;
 
                if (sw_ppm)
                begin // Minutes
                        if (stopwatch[19:16] >= 4'h9)
                                stopwatch[19:16] <= 4'h0;
                        else
                                stopwatch[19:16] <= stopwatch[19:16]+4'h1;
 
                        if (stopwatch[23:16] >= 8'h59)
                                stopwatch[23:20] <= 4'h0;
                        else if (stopwatch[19:16] >= 4'h9)
                                stopwatch[23:20] <= stopwatch[23:20]+4'h1;
                        sw_pph <= (stopwatch[23:16] == 8'h59);
                end else sw_pph <= 1'b0;
 
                if (sw_pph)
                begin // And hours
                        if (stopwatch[27:24] >= 4'h9)
                                stopwatch[27:24] <= 4'h0;
                        else
                                stopwatch[27:24] <= stopwatch[27:24]+4'h1;
 
                        if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
                                stopwatch[31:28] <= stopwatch[27:24]+4'h1;
                end
 
                if ((sw_sel)&&(i_wb_we))
                begin
                        stopwatch[0] <= i_wb_data[0];
                        if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
                        begin
                                stopwatch[31:1] <= 31'h00;
                                sw_sub <= 8'h00;
                                sw_pps <= 1'b0;
                                sw_ppm <= 1'b0;
                                sw_pph <= 1'b0;
                        end
                end
        end
 
        //
        // The alarm code
        //
        // Set the alarm register to the time you wish the board to "alarm".
        // The "alarm" will take place once per day at that time.  At that
        // time, the RTC code will generate a clock interrupt, and the CPU/host
        // can come and see that the alarm tripped.
        //
        // 
        reg     [21:0]           alarm_time;
        reg                     al_int,         // The alarm interrupt line
                                al_enabled,     // Whether the alarm is enabled
                                al_tripped;     // Whether the alarm has tripped
        initial al_enabled= 1'b0;
        initial al_tripped= 1'b0;
        always @(posedge i_clk)
        begin
                if ((al_sel)&&(i_wb_we))
                begin
                        // Only adjust the alarm hours if the requested hours
                        // are valid.  This allows writes to the register,
                        // without a prior read, to leave these configuration
                        // bits alone.
                        if (i_wb_data[21:16] != 6'h3f)
                                alarm_time[21:16] <= i_wb_data[21:16];
                        // Here's the same thing for the minutes: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[15:8] != 8'hff)
                                alarm_time[15:8] <= i_wb_data[15:8];
                        // Here's the same thing for the seconds: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[7:0] != 8'hff)
                                alarm_time[7:0] <= i_wb_data[7:0];
                        al_enabled <= i_wb_data[24];
                        // Reset the alarm if a '1' is written to the tripped
                        // register, or if the alarm is disabled.
                        if ((i_wb_data[25])||(~i_wb_data[24]))
                                al_tripped <= 1'b0;
                end
 
                al_int <= 1'b0;
                if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
                        &&(al_enabled))
                begin
                        al_tripped <= 1'b1;
                        al_int <= 1'b1;
                end
        end
 
        //
        // The ckspeed register is equal to 2^48 divded by the number of
        // clock ticks you expect per second.  Adjust high for a slower
        // clock, lower for a faster clock.  In this fashion, a single
        // real time clock RTL file can handle tracking the clock in any
        // device.  Further, because this is only the lower 32 bits of a 
        // 48 bit counter per seconds, the clock jitter is kept below
        // 1 part in 65 thousand.
        //
        initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz
        // In the case of verilator, comment the above and uncomment the line
        // below.  The clock constant below is "close" to simulation time,
        // meaning that my verilator simulation is running about 300x slower
        // than board time.
        // initial      ckspeed = 32'd786432000;
        always @(posedge i_clk)
                if ((sp_sel)&&(i_wb_we))
                        ckspeed <= i_wb_data;
 
        // 
        // If you want very fine precision control over your clock, you need
        // to be able to transfer time from one location to another.  This
        // is the beginning of that means: by setting a wire, i_hack, high
        // on a particular input, you can then read (later) what the clock
        // time was on that input.
        //
        // What's missing from this high precision adjustment mechanism is a
        // means of actually adjusting this time based upon the time 
        // difference you measure here between the hack time and some time
        // on another clock, but we'll get there.
        //
        reg             r_hack_carry;
        reg     [29:0]   hack_time;
        reg     [39:0]   hack_counter;
        always @(posedge i_clk)
                if (i_hack)
                begin
                        hack_time <= { clock[21:0], ck_sub };
                        hack_counter <= ck_counter;
                        r_hack_carry <= ck_carry;
                        // if ck_carry is set, the clock register is in the
                        // middle of a two clock update.  In that case ....
                end else if (r_hack_carry)
                begin // update again on the next clock to get the correct
                        // hack time.
                        hack_time <= { clock[21:0], ck_sub };
                        r_hack_carry <= 1'b0;
                end
 
        reg     [15:0]   h_sseg;
        always @(posedge i_clk)
                case(clock[27:24])
                4'h0: h_sseg <= { 2'b00, ck_last_clock[21:8] };
                4'h1: h_sseg <= timer[15:0];
                4'h2: h_sseg <= stopwatch[19:4];
                4'h3: h_sseg <= ck_last_clock[15:0];
                default: h_sseg <= { 2'b00, ck_last_clock[21:8] };
                endcase
 
        wire    [31:0]   w_sseg;
        assign  w_sseg[ 0] = (~ck_sub[7]);
        assign  w_sseg[ 8] = 1'b0;
        assign  w_sseg[16] = 1'b0;
        assign  w_sseg[24] = 1'b0;
        hexmap  ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
        hexmap  hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
        hexmap  hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
        hexmap  hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
 
        always @(posedge i_clk)
                if ((tm_alarm || al_tripped)&&(ck_sub[7]))
                        o_sseg <= 32'h0000;
                else
                        o_sseg <= w_sseg;
 
        reg     [17:0]   ledreg;
        always @(posedge i_clk)
                if ((ck_pps)&&(ck_ppm))
                        ledreg <= 18'h00;
                else if (ck_carry)
                        ledreg <= ledreg + 18'h11;
        assign  o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:ledreg[17:2];
 
        assign  o_interrupt = tm_int || al_int;
 
        always @(posedge i_clk)
                case(i_wb_addr[2:0])
                3'b000: o_data <= { clock[31:22], ck_last_clock };
                3'b001: o_data <= { 14'h00, timer };
                3'b010: o_data <= stopwatch;
                3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
                3'b100: o_data <= ckspeed;
                3'b101: o_data <= { 2'b00, hack_time };
                3'b110: o_data <= hack_counter[39:8];
                3'b111: o_data <= { hack_counter[7:0], 24'h00 };
                endcase
 
endmodule

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Subversion Repositories rtcclock

[/] [rtcclock/] [trunk/] [rtl/] [rtcclock.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: rtcclock.v`
4			`//`
5			`// Project: A Wishbone Controlled Real--time Clock Core`
6			`//`
7			`// Purpose: Implement a real time clock, including alarm, count--down`
8			`// timer, stopwatch, variable time frequency, and more.`
9			`//`
10			`//`
11			`// Creator: Dan Gisselquist, Ph.D.`
12			`// Gisselquist Tecnology, LLC`
13			`//`
14			`///////////////////////////////////////////////////////////////////////////`
15			`//`
16			`// Copyright (C) 2015, Gisselquist Technology, LLC`
17			`//`
18			`// This program is free software (firmware): you can redistribute it and/or`
19			`// modify it under the terms of the GNU General Public License as published`
20			`// by the Free Software Foundation, either version 3 of the License, or (at`
21			`// your option) any later version.`
22			`//`
23			`// This program is distributed in the hope that it will be useful, but WITHOUT`
24			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
25			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
26			`// for more details.`
27			`//`
28			`// You should have received a copy of the GNU General Public License along`
29			`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
30			`// target there if the PDF file isn't present.) If not, see`
31			`// <http://www.gnu.org/licenses/> for a copy.`
32			`//`
33			`// License: GPL, v3, as defined and found on www.gnu.org,`
34			`// http://www.gnu.org/licenses/gpl.html`
35			`//`
36			`//`
37			`///////////////////////////////////////////////////////////////////////////`
38			`module rtcclock(i_clk,`
39			`// Wishbone interface`
40			`i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,`
41			`// o_wb_ack, o_wb_stb, o_wb_data, // no reads here`
42			`// // Button inputs`
43			`// i_btn,`
44			`// Output registers`
45			`o_data, // multiplexed based upon i_wb_addr`
46			`// Output controls`
47			`o_sseg, o_led, o_interrupt,`
48			`// Time setting hack(s)`
49			`i_hack);`
50			`input i_clk;`
51			`input i_wb_cyc, i_wb_stb, i_wb_we;`
52			`input [2:0] i_wb_addr;`
53			`input [31:0] i_wb_data;`
54			`// input i_btn;`
55			`output reg [31:0] o_data;`
56			`output reg [31:0] o_sseg;`
57			`output wire [15:0] o_led;`
58			`output wire o_interrupt;`
59			`input i_hack;`
60
61			`reg [31:0] clock, stopwatch, ckspeed;`
62			`reg [17:0] timer;`
63
64			`wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;`
65			`assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));`
66			`assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));`
67			`assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));`
68			`assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));`
69			`assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));`
70
71			`reg [39:0] ck_counter;`
72			`reg ck_carry;`
73			`always @(posedge i_clk)`
74			`{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };`
75
76			`wire ck_pps;`
77			`reg ck_prepps, ck_ppm, ck_pph, ck_ppd;`
78			`reg [7:0] ck_sub;`
79			`initial clock = 32'h00000000;`
80			`assign ck_pps = (ck_carry)&&(ck_prepps);`
81			`always @(posedge i_clk)`
82			`begin`
83			`if (ck_carry)`
84			`ck_sub <= ck_sub + 1;`
85			`ck_prepps <= (ck_sub == 8'hff);`
86
87			`if (ck_pps)`
88			`begin // advance the seconds`
89			`if (clock[3:0] >= 4'h9)`
90			`clock[3:0] <= 4'h0;`
91			`else`
92			`clock[3:0] <= clock[3:0] + 4'h1;`
93			`if (clock[7:0] >= 8'h59)`
94			`clock[7:4] <= 4'h0;`
95			`else if (clock[3:0] >= 4'h9)`
96			`clock[7:4] <= clock[7:4] + 4'h1;`
97			`end`
98			`ck_ppm <= (clock[7:0] == 8'h59);`
99
100			`if ((ck_pps)&&(ck_ppm))`
101			`begin // advance the minutes`
102			`if (clock[11:8] >= 4'h9)`
103			`clock[11:8] <= 4'h0;`
104			`else`
105			`clock[11:8] <= clock[11:8] + 4'h1;`
106			`if (clock[15:8] >= 8'h59)`
107			`clock[15:12] <= 4'h0;`
108			`else if (clock[11:8] >= 4'h9)`
109			`clock[15:12] <= clock[15:12] + 4'h1;`
110			`end`
111			`ck_pph <= (clock[15:0] == 16'h5959);`
112
113			`if ((ck_pps)&&(ck_pph))`
114			`begin // advance the hours`
115			`if (clock[21:16] >= 6'h23)`
116			`begin`
117			`clock[19:16] <= 4'h0;`
118			`clock[21:20] <= 2'h0;`
119			`end else if (clock[19:16] >= 4'h9)`
120			`begin`
121			`clock[19:16] <= 4'h0;`
122			`clock[21:20] <= clock[21:20] + 2'h1;`
123			`end else begin`
124			`clock[19:16] <= clock[19:16] + 4'h1;`
125			`end`
126			`end`
127			`// ppd <= (clock{15:8] == 8'h59);`
128
129			`if ((ck_sel)&&(i_wb_we))`
130			`begin`
131			`if (8'hff != i_wb_data[7:0])`
132			`begin`
133			`clock[7:0] <= i_wb_data[7:0];`
134			`ck_ppm <= (i_wb_data[7:0] == 8'h59);`
135			`end`
136			`if (8'hff != i_wb_data[15:8])`
137			`begin`
138			`clock[15:8] <= i_wb_data[15:8];`
139			`ck_pph <= (i_wb_data[15:8] == 8'h59);`
140			`end`
141			`if (6'h3f != i_wb_data[21:16])`
142			`clock[21:16] <= i_wb_data[21:16];`
143			`clock[31:22] <= i_wb_data[31:22];`
144			`if (8'h00 == i_wb_data[7:0])`
145			`ck_sub <= 8'h00;`
146			`end`
147			`end`
148
149			`// Clock updates take several clocks, so let's make sure we`
150			`// are only looking at a valid clock value before testing it.`
151			`reg [21:0] ck_last_clock;`
152			`always @(posedge i_clk)`
153			`ck_last_clock <= clock[21:0];`
154
155
156			`reg tm_pps, tm_ppm, tm_int;`
157			`wire tm_stopped, tm_running, tm_alarm;`
158			`assign tm_stopped = ~timer[24];`
159			`assign tm_running = timer[24];`
160			`assign tm_alarm = timer[25];`
161			`reg [23:0] tm_start;`
162			`reg [7:0] tm_sub;`
163			`initial tm_start = 16'h00;`
164			`initial timer = 18'h00;`
165			`initial tm_int = 1'b0;`
166			`initial tm_pps = 1'b0;`
167			`always @(posedge i_clk)`
168			`begin`
169			`if (ck_carry)`
170			`begin`
171			`tm_sub <= tm_sub + 1;`
172			`tm_pps <= (tm_sub == 8'hff);`
173			`end else`
174			`tm_pps <= 1'b0;`
175
176			`if ((~tm_alarm)&&(tm_running)&&(tm_pps))`
177			`begin // If we are running ...`
178			`timer[25] <= 1'b0;`
179			`if (timer[23:0] == 24'h00)`
180			`timer[25] <= 1'b1;`
181			`else if (timer[3:0] != 4'h0)`
182			`timer[3:0] <= timer[3:0]-4'h1;`
183			`else begin // last digit is a zero`
184			`timer[3:0] <= 4'h9;`
185			`if (timer[7:4] != 4'h0)`
186			`timer[7:4] <= timer[7:4]-4'h1;`
187			`else begin // last two digits are zero`
188			`timer[7:4] <= 4'h5;`
189			`if (timer[11:8] != 4'h0)`
190			`timer[11:8] <= timer[11:8]-4'h1;`
191			`else begin // last three digits are zero`
192			`timer[11:8] <= 4'h9;`
193			`if (timer[15:12] != 4'h0)`
194			`timer[15:12] <= timer[15:12]-4'h1;`
195			`else begin`
196			`timer[15:12] <= 4'h5;`
197			`if (timer[19:16] != 4'h0)`
198			`timer[19:16] <= timer[19:16]-4'h1;`
199			`else begin`
200			`//`
201			`timer[19:16] <= 4'h9;`
202			`timer[23:20] <= timer[23:20]-4'h1;`
203			`end`
204			`end`
205			`end`
206			`end`
207			`end`
208			`end`
209
210			`if((~tm_alarm)&&(tm_running))`
211			`begin`
212			`timer[25] <= (timer[23:0] == 24'h00);`
213			`tm_int <= (timer[23:0] == 24'h00);`
214			`end else tm_int <= 1'b0;`
215			`if (tm_alarm)`
216			`timer[24] <= 1'b0;`
217
218			`if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running`
219			`// Only allowed to stop the timer, nothing more`
220			`timer[24] <= i_wb_data[24];`
221			`else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off`
222			`begin`
223			`timer[24] <= i_wb_data[24];`
224			`if ((timer[24])\|\|(i_wb_data[24]))`
225			`timer[25] <= 1'b0;`
226			`if (i_wb_data[23:0] != 24'h0000)`
227			`begin`
228			`timer[23:0] <= i_wb_data[23:0];`
229			`tm_start <= i_wb_data[23:0];`
230			`tm_sub <= 8'h00;`
231			`end else if (timer[23:0] == 24'h00)`
232			`begin // Resetting timer to last valid timer start val`
233			`timer[23:0] <= tm_start;`
234			`tm_sub <= 8'h00;`
235			`end`
236			`// Any write clears the alarm`
237			`timer[25] <= 1'b0;`
238			`end`
239			`end`
240
241			`//`
242			`// Stopwatch functionality`
243			`//`
244			`// Setting bit '0' starts the stop watch, clearing it stops it.`
245			`// Writing to the register with bit '1' high will clear the stopwatch,`
246			`// and return it to zero provided that the stopwatch is stopped either`
247			`// before or after the write. Hence, writing a '2' to the device`
248			`// will always stop and clear it, whereas writing a '3' to the device`
249			`// will only clear it if it was already stopped.`
250			`reg sw_pps, sw_ppm, sw_pph;`
251			`reg [7:0] sw_sub;`
252			`wire sw_running;`
253			`assign sw_running = stopwatch[0];`
254			`initial stopwatch = 32'h00001;`
255			`always @(posedge i_clk)`
256			`begin`
257			`sw_pps <= 1'b0;`
258			`if (sw_running)`
259			`begin`
260			`if (ck_carry)`
261			`begin`
262			`sw_sub <= sw_sub + 1;`
263			`sw_pps <= (sw_sub == 8'hff);`
264			`end`
265			`end`
266
267			`stopwatch[7:1] <= sw_sub[7:1];`
268
269			`if (sw_pps)`
270			`begin // Second hand`
271			`if (stopwatch[11:8] >= 4'h9)`
272			`stopwatch[11:8] <= 4'h0;`
273			`else`
274			`stopwatch[11:8] <= stopwatch[11:8] + 4'h1;`
275
276			`if (stopwatch[15:8] >= 8'h59)`
277			`stopwatch[15:12] <= 4'h0;`
278			`else if (stopwatch[11:8] >= 4'h9)`
279			`stopwatch[15:12] <= stopwatch[15:12] + 4'h1;`
280			`sw_ppm <= (stopwatch[15:8] == 8'h59);`
281			`end else sw_ppm <= 1'b0;`
282
283			`if (sw_ppm)`
284			`begin // Minutes`
285			`if (stopwatch[19:16] >= 4'h9)`
286			`stopwatch[19:16] <= 4'h0;`
287			`else`
288			`stopwatch[19:16] <= stopwatch[19:16]+4'h1;`
289
290			`if (stopwatch[23:16] >= 8'h59)`
291			`stopwatch[23:20] <= 4'h0;`
292			`else if (stopwatch[19:16] >= 4'h9)`
293			`stopwatch[23:20] <= stopwatch[23:20]+4'h1;`
294			`sw_pph <= (stopwatch[23:16] == 8'h59);`
295			`end else sw_pph <= 1'b0;`
296
297			`if (sw_pph)`
298			`begin // And hours`
299			`if (stopwatch[27:24] >= 4'h9)`
300			`stopwatch[27:24] <= 4'h0;`
301			`else`
302			`stopwatch[27:24] <= stopwatch[27:24]+4'h1;`
303
304			`if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))`
305			`stopwatch[31:28] <= stopwatch[27:24]+4'h1;`
306			`end`
307
308			`if ((sw_sel)&&(i_wb_we))`
309			`begin`
310			`stopwatch[0] <= i_wb_data[0];`
311			`if((i_wb_data[1])&&((~stopwatch[0])\|\|(~i_wb_data[0])))`
312			`begin`
313			`stopwatch[31:1] <= 31'h00;`
314			`sw_sub <= 8'h00;`
315			`sw_pps <= 1'b0;`
316			`sw_ppm <= 1'b0;`
317			`sw_pph <= 1'b0;`
318			`end`
319			`end`
320			`end`
321
322			`//`
323			`// The alarm code`
324			`//`
325			`// Set the alarm register to the time you wish the board to "alarm".`
326			`// The "alarm" will take place once per day at that time. At that`
327			`// time, the RTC code will generate a clock interrupt, and the CPU/host`
328			`// can come and see that the alarm tripped.`
329			`//`
330			`//`
331			`reg [21:0] alarm_time;`
332			`reg al_int, // The alarm interrupt line`
333			`al_enabled, // Whether the alarm is enabled`
334			`al_tripped; // Whether the alarm has tripped`
335			`initial al_enabled= 1'b0;`
336			`initial al_tripped= 1'b0;`
337			`always @(posedge i_clk)`
338			`begin`
339			`if ((al_sel)&&(i_wb_we))`
340			`begin`
341			`// Only adjust the alarm hours if the requested hours`
342			`// are valid. This allows writes to the register,`
343			`// without a prior read, to leave these configuration`
344			`// bits alone.`
345			`if (i_wb_data[21:16] != 6'h3f)`
346			`alarm_time[21:16] <= i_wb_data[21:16];`
347			`// Here's the same thing for the minutes: only adjust`
348			`// the alarm minutes if the new bits are not all 1's.`
349			`if (i_wb_data[15:8] != 8'hff)`
350			`alarm_time[15:8] <= i_wb_data[15:8];`
351			`// Here's the same thing for the seconds: only adjust`
352			`// the alarm minutes if the new bits are not all 1's.`
353			`if (i_wb_data[7:0] != 8'hff)`
354			`alarm_time[7:0] <= i_wb_data[7:0];`
355			`al_enabled <= i_wb_data[24];`
356			`// Reset the alarm if a '1' is written to the tripped`
357			`// register, or if the alarm is disabled.`
358			`if ((i_wb_data[25])\|\|(~i_wb_data[24]))`
359			`al_tripped <= 1'b0;`
360			`end`
361
362			`al_int <= 1'b0;`
363			`if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)`
364			`&&(al_enabled))`
365			`begin`
366			`al_tripped <= 1'b1;`
367			`al_int <= 1'b1;`
368			`end`
369			`end`
370
371			`//`
372			`// The ckspeed register is equal to 2^48 divded by the number of`
373			`// clock ticks you expect per second. Adjust high for a slower`
374			`// clock, lower for a faster clock. In this fashion, a single`
375			`// real time clock RTL file can handle tracking the clock in any`
376			`// device. Further, because this is only the lower 32 bits of a`
377			`// 48 bit counter per seconds, the clock jitter is kept below`
378			`// 1 part in 65 thousand.`
379			`//`
380			`initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz`
381			`// In the case of verilator, comment the above and uncomment the line`
382			`// below. The clock constant below is "close" to simulation time,`
383			`// meaning that my verilator simulation is running about 300x slower`
384			`// than board time.`
385			`// initial ckspeed = 32'd786432000;`
386			`always @(posedge i_clk)`
387			`if ((sp_sel)&&(i_wb_we))`
388			`ckspeed <= i_wb_data;`
389
390			`//`
391			`// If you want very fine precision control over your clock, you need`
392			`// to be able to transfer time from one location to another. This`
393			`// is the beginning of that means: by setting a wire, i_hack, high`
394			`// on a particular input, you can then read (later) what the clock`
395			`// time was on that input.`
396			`//`
397			`// What's missing from this high precision adjustment mechanism is a`
398			`// means of actually adjusting this time based upon the time`
399			`// difference you measure here between the hack time and some time`
400			`// on another clock, but we'll get there.`
401			`//`
402			`reg r_hack_carry;`
403			`reg [29:0] hack_time;`
404			`reg [39:0] hack_counter;`
405			`always @(posedge i_clk)`
406			`if (i_hack)`
407			`begin`
408			`hack_time <= { clock[21:0], ck_sub };`
409			`hack_counter <= ck_counter;`
410			`r_hack_carry <= ck_carry;`
411			`// if ck_carry is set, the clock register is in the`
412			`// middle of a two clock update. In that case ....`
413			`end else if (r_hack_carry)`
414			`begin // update again on the next clock to get the correct`
415			`// hack time.`
416			`hack_time <= { clock[21:0], ck_sub };`
417			`r_hack_carry <= 1'b0;`
418			`end`
419
420			`reg [15:0] h_sseg;`
421			`always @(posedge i_clk)`
422			`case(clock[27:24])`
423			`4'h0: h_sseg <= { 2'b00, ck_last_clock[21:8] };`
424			`4'h1: h_sseg <= timer[15:0];`
425			`4'h2: h_sseg <= stopwatch[19:4];`
426			`4'h3: h_sseg <= ck_last_clock[15:0];`
427			`default: h_sseg <= { 2'b00, ck_last_clock[21:8] };`
428			`endcase`
429
430			`wire [31:0] w_sseg;`
431			`assign w_sseg[ 0] = (~ck_sub[7]);`
432			`assign w_sseg[ 8] = 1'b0;`
433			`assign w_sseg[16] = 1'b0;`
434			`assign w_sseg[24] = 1'b0;`
435			`hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);`
436			`hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);`
437			`hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);`
438			`hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);`
439
440			`always @(posedge i_clk)`
441			`if ((tm_alarm \|\| al_tripped)&&(ck_sub[7]))`
442			`o_sseg <= 32'h0000;`
443			`else`
444			`o_sseg <= w_sseg;`
445
446			`reg [17:0] ledreg;`
447			`always @(posedge i_clk)`
448			`if ((ck_pps)&&(ck_ppm))`
449			`ledreg <= 18'h00;`
450			`else if (ck_carry)`
451			`ledreg <= ledreg + 18'h11;`
452			`assign o_led = (tm_alarm\|\|al_tripped)?{ (16){ck_sub[7]}}:ledreg[17:2];`
453
454			`assign o_interrupt = tm_int \|\| al_int;`
455
456			`always @(posedge i_clk)`
457			`case(i_wb_addr[2:0])`
458			`3'b000: o_data <= { clock[31:22], ck_last_clock };`
459			`3'b001: o_data <= { 14'h00, timer };`
460			`3'b010: o_data <= stopwatch;`
461			`3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };`
462			`3'b100: o_data <= ckspeed;`
463			`3'b101: o_data <= { 2'b00, hack_time };`
464			`3'b110: o_data <= hack_counter[39:8];`
465			`3'b111: o_data <= { hack_counter[7:0], 24'h00 };`
466			`endcase`
467
468			`endmodule`