OpenCores
URL https://opencores.org/ocsvn/rtcclock/rtcclock/trunk

Subversion Repositories rtcclock

[/] [rtcclock/] [trunk/] [rtl/] [rtcclock.v] - Blame information for rev 8

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    rtcclock.v
4
//              
5
// Project:     A Wishbone Controlled Real--time Clock Core
6
//
7
// Purpose:     Implement a real time clock, including alarm, count--down
8
//              timer, stopwatch, variable time frequency, and more.
9
//
10
//
11
// Creator:     Dan Gisselquist, Ph.D.
12 8 dgisselq
//              Gisselquist Technology, LLC
13 2 dgisselq
//
14
///////////////////////////////////////////////////////////////////////////
15
//
16
// Copyright (C) 2015, Gisselquist Technology, LLC
17
//
18
// This program is free software (firmware): you can redistribute it and/or
19
// modify it under the terms of  the GNU General Public License as published
20
// by the Free Software Foundation, either version 3 of the License, or (at
21
// your option) any later version.
22
//
23
// This program is distributed in the hope that it will be useful, but WITHOUT
24
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
25
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
26
// for more details.
27
//
28
// You should have received a copy of the GNU General Public License along
29
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
30
// target there if the PDF file isn't present.)  If not, see
31
// <http://www.gnu.org/licenses/> for a copy.
32
//
33
// License:     GPL, v3, as defined and found on www.gnu.org,
34
//              http://www.gnu.org/licenses/gpl.html
35
//
36
//
37
///////////////////////////////////////////////////////////////////////////
38
module  rtcclock(i_clk,
39
                // Wishbone interface
40
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
41
                //      o_wb_ack, o_wb_stb, o_wb_data, // no reads here
42
                // // Button inputs
43
                // i_btn,
44
                // Output registers
45
                o_data, // multiplexed based upon i_wb_addr
46
                // Output controls
47
                o_sseg, o_led, o_interrupt,
48 6 dgisselq
                // A once-per-day strobe on the last clock of the day
49 5 dgisselq
                o_ppd,
50 2 dgisselq
                // Time setting hack(s)
51
                i_hack);
52 7 dgisselq
        parameter       DEFAULT_SPEED = 32'd2814750; //2af31e = 2^48 / 100e6 MHz
53 2 dgisselq
        input   i_clk;
54
        input   i_wb_cyc, i_wb_stb, i_wb_we;
55
        input   [2:0]    i_wb_addr;
56
        input   [31:0]   i_wb_data;
57
        // input                i_btn;
58
        output  reg     [31:0]   o_data;
59
        output  reg     [31:0]   o_sseg;
60
        output  wire    [15:0]   o_led;
61 5 dgisselq
        output  wire            o_interrupt, o_ppd;
62 2 dgisselq
        input                   i_hack;
63
 
64 7 dgisselq
        reg     [31:0]   stopwatch, ckspeed;
65
        reg     [25:0]   clock, timer;
66 2 dgisselq
 
67
        wire    ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
68
        assign  ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
69
        assign  tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
70
        assign  sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
71
        assign  al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
72
        assign  sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
73
 
74
        reg     [39:0]   ck_counter;
75
        reg             ck_carry;
76
        always @(posedge i_clk)
77
                { ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
78
 
79
        wire            ck_pps;
80
        reg             ck_prepps, ck_ppm, ck_pph, ck_ppd;
81
        reg     [7:0]    ck_sub;
82 7 dgisselq
        initial clock = 26'h000000;
83 2 dgisselq
        assign  ck_pps = (ck_carry)&&(ck_prepps);
84
        always @(posedge i_clk)
85
        begin
86
                if (ck_carry)
87 7 dgisselq
                        ck_sub <= ck_sub + 8'h1;
88 2 dgisselq
                ck_prepps <= (ck_sub == 8'hff);
89
 
90
                if (ck_pps)
91
                begin // advance the seconds
92
                        if (clock[3:0] >= 4'h9)
93
                                clock[3:0] <= 4'h0;
94
                        else
95
                                clock[3:0] <= clock[3:0] + 4'h1;
96
                        if (clock[7:0] >= 8'h59)
97
                                clock[7:4] <= 4'h0;
98
                        else if (clock[3:0] >= 4'h9)
99
                                clock[7:4] <= clock[7:4] + 4'h1;
100
                end
101
                ck_ppm <= (clock[7:0] == 8'h59);
102
 
103
                if ((ck_pps)&&(ck_ppm))
104
                begin // advance the minutes
105
                        if (clock[11:8] >= 4'h9)
106
                                clock[11:8] <= 4'h0;
107
                        else
108
                                clock[11:8] <= clock[11:8] + 4'h1;
109
                        if (clock[15:8] >= 8'h59)
110
                                clock[15:12] <= 4'h0;
111
                        else if (clock[11:8] >= 4'h9)
112
                                clock[15:12] <= clock[15:12] + 4'h1;
113
                end
114
                ck_pph <= (clock[15:0] == 16'h5959);
115
 
116
                if ((ck_pps)&&(ck_pph))
117
                begin // advance the hours
118
                        if (clock[21:16] >= 6'h23)
119
                        begin
120
                                clock[19:16] <= 4'h0;
121
                                clock[21:20] <= 2'h0;
122
                        end else if (clock[19:16] >= 4'h9)
123
                        begin
124
                                clock[19:16] <= 4'h0;
125
                                clock[21:20] <= clock[21:20] + 2'h1;
126
                        end else begin
127
                                clock[19:16] <= clock[19:16] + 4'h1;
128
                        end
129
                end
130 5 dgisselq
                ck_ppd <= (clock[21:0] == 22'h235959);
131 2 dgisselq
 
132 5 dgisselq
 
133 2 dgisselq
                if ((ck_sel)&&(i_wb_we))
134
                begin
135
                        if (8'hff != i_wb_data[7:0])
136
                        begin
137
                                clock[7:0] <= i_wb_data[7:0];
138
                                ck_ppm <= (i_wb_data[7:0] == 8'h59);
139
                        end
140
                        if (8'hff != i_wb_data[15:8])
141
                        begin
142
                                clock[15:8] <= i_wb_data[15:8];
143
                                ck_pph <= (i_wb_data[15:8] == 8'h59);
144
                        end
145
                        if (6'h3f != i_wb_data[21:16])
146
                                clock[21:16] <= i_wb_data[21:16];
147 7 dgisselq
                        clock[25:22] <= i_wb_data[25:22];
148 2 dgisselq
                        if (8'h00 == i_wb_data[7:0])
149
                                ck_sub <= 8'h00;
150
                end
151
        end
152
 
153
        // Clock updates take several clocks, so let's make sure we
154
        // are only looking at a valid clock value before testing it.
155
        reg     [21:0]           ck_last_clock;
156
        always @(posedge i_clk)
157
                ck_last_clock <= clock[21:0];
158
 
159
 
160
        reg     tm_pps, tm_ppm, tm_int;
161
        wire    tm_stopped, tm_running, tm_alarm;
162
        assign  tm_stopped = ~timer[24];
163
        assign  tm_running =  timer[24];
164
        assign  tm_alarm   =  timer[25];
165
        reg     [23:0]           tm_start;
166
        reg     [7:0]            tm_sub;
167 4 dgisselq
        initial tm_start = 24'h00;
168
        initial timer    = 26'h00;
169 2 dgisselq
        initial tm_int   = 1'b0;
170
        initial tm_pps   = 1'b0;
171
        always @(posedge i_clk)
172
        begin
173
                if (ck_carry)
174
                begin
175 7 dgisselq
                        tm_sub <= tm_sub + 8'h1;
176 2 dgisselq
                        tm_pps <= (tm_sub == 8'hff);
177
                end else
178
                        tm_pps <= 1'b0;
179
 
180
                if ((~tm_alarm)&&(tm_running)&&(tm_pps))
181
                begin // If we are running ...
182
                        timer[25] <= 1'b0;
183
                        if (timer[23:0] == 24'h00)
184
                                timer[25] <= 1'b1;
185
                        else if (timer[3:0] != 4'h0)
186
                                timer[3:0] <= timer[3:0]-4'h1;
187
                        else begin // last digit is a zero
188
                                timer[3:0] <= 4'h9;
189
                                if (timer[7:4] != 4'h0)
190
                                        timer[7:4] <= timer[7:4]-4'h1;
191
                                else begin // last two digits are zero
192
                                        timer[7:4] <= 4'h5;
193
                                        if (timer[11:8] != 4'h0)
194
                                                timer[11:8] <= timer[11:8]-4'h1;
195
                                        else begin // last three digits are zero
196
                                                timer[11:8] <= 4'h9;
197
                                                if (timer[15:12] != 4'h0)
198
                                                        timer[15:12] <= timer[15:12]-4'h1;
199
                                                else begin
200
                                                        timer[15:12] <= 4'h5;
201
                                                        if (timer[19:16] != 4'h0)
202
                                                                timer[19:16] <= timer[19:16]-4'h1;
203
                                                        else begin
204
                                                        //
205
                                                                timer[19:16] <= 4'h9;
206
                                                                timer[23:20] <= timer[23:20]-4'h1;
207
                                                        end
208
                                                end
209
                                        end
210
                                end
211
                        end
212
                end
213
 
214
                if((~tm_alarm)&&(tm_running))
215
                begin
216
                        timer[25] <= (timer[23:0] == 24'h00);
217
                        tm_int <= (timer[23:0] == 24'h00);
218
                end else tm_int <= 1'b0;
219
                if (tm_alarm)
220
                        timer[24] <= 1'b0;
221
 
222
                if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
223
                        // Only allowed to stop the timer, nothing more
224
                        timer[24] <= i_wb_data[24];
225
                else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
226
                begin
227
                        timer[24] <= i_wb_data[24];
228
                        if ((timer[24])||(i_wb_data[24]))
229
                                timer[25] <= 1'b0;
230
                        if (i_wb_data[23:0] != 24'h0000)
231
                        begin
232
                                timer[23:0] <= i_wb_data[23:0];
233
                                tm_start <= i_wb_data[23:0];
234
                                tm_sub <= 8'h00;
235
                        end else if (timer[23:0] == 24'h00)
236
                        begin // Resetting timer to last valid timer start val
237
                                timer[23:0] <= tm_start;
238
                                tm_sub <= 8'h00;
239
                        end
240
                        // Any write clears the alarm
241
                        timer[25] <= 1'b0;
242
                end
243
        end
244
 
245
        //
246
        // Stopwatch functionality
247
        //
248
        // Setting bit '0' starts the stop watch, clearing it stops it.
249
        // Writing to the register with bit '1' high will clear the stopwatch,
250
        // and return it to zero provided that the stopwatch is stopped either
251
        // before or after the write.  Hence, writing a '2' to the device
252
        // will always stop and clear it, whereas writing a '3' to the device
253
        // will only clear it if it was already stopped.
254
        reg             sw_pps, sw_ppm, sw_pph;
255
        reg     [7:0]    sw_sub;
256
        wire    sw_running;
257
        assign  sw_running = stopwatch[0];
258 4 dgisselq
        initial stopwatch = 32'h00000;
259 2 dgisselq
        always @(posedge i_clk)
260
        begin
261
                sw_pps <= 1'b0;
262
                if (sw_running)
263
                begin
264
                        if (ck_carry)
265
                        begin
266 7 dgisselq
                                sw_sub <= sw_sub + 8'h1;
267 2 dgisselq
                                sw_pps <= (sw_sub == 8'hff);
268
                        end
269
                end
270
 
271
                stopwatch[7:1] <= sw_sub[7:1];
272
 
273
                if (sw_pps)
274
                begin // Second hand
275
                        if (stopwatch[11:8] >= 4'h9)
276
                                stopwatch[11:8] <= 4'h0;
277
                        else
278
                                stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
279
 
280
                        if (stopwatch[15:8] >= 8'h59)
281
                                stopwatch[15:12] <= 4'h0;
282
                        else if (stopwatch[11:8] >= 4'h9)
283
                                stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
284
                        sw_ppm <= (stopwatch[15:8] == 8'h59);
285
                end else sw_ppm <= 1'b0;
286
 
287
                if (sw_ppm)
288
                begin // Minutes
289
                        if (stopwatch[19:16] >= 4'h9)
290
                                stopwatch[19:16] <= 4'h0;
291
                        else
292
                                stopwatch[19:16] <= stopwatch[19:16]+4'h1;
293
 
294
                        if (stopwatch[23:16] >= 8'h59)
295
                                stopwatch[23:20] <= 4'h0;
296
                        else if (stopwatch[19:16] >= 4'h9)
297
                                stopwatch[23:20] <= stopwatch[23:20]+4'h1;
298
                        sw_pph <= (stopwatch[23:16] == 8'h59);
299
                end else sw_pph <= 1'b0;
300
 
301
                if (sw_pph)
302
                begin // And hours
303
                        if (stopwatch[27:24] >= 4'h9)
304
                                stopwatch[27:24] <= 4'h0;
305
                        else
306
                                stopwatch[27:24] <= stopwatch[27:24]+4'h1;
307
 
308
                        if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
309
                                stopwatch[31:28] <= stopwatch[27:24]+4'h1;
310
                end
311
 
312
                if ((sw_sel)&&(i_wb_we))
313
                begin
314
                        stopwatch[0] <= i_wb_data[0];
315
                        if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
316
                        begin
317
                                stopwatch[31:1] <= 31'h00;
318
                                sw_sub <= 8'h00;
319
                                sw_pps <= 1'b0;
320
                                sw_ppm <= 1'b0;
321
                                sw_pph <= 1'b0;
322
                        end
323
                end
324
        end
325
 
326
        //
327
        // The alarm code
328
        //
329
        // Set the alarm register to the time you wish the board to "alarm".
330
        // The "alarm" will take place once per day at that time.  At that
331
        // time, the RTC code will generate a clock interrupt, and the CPU/host
332
        // can come and see that the alarm tripped.
333
        //
334
        // 
335
        reg     [21:0]           alarm_time;
336
        reg                     al_int,         // The alarm interrupt line
337
                                al_enabled,     // Whether the alarm is enabled
338
                                al_tripped;     // Whether the alarm has tripped
339
        initial al_enabled= 1'b0;
340
        initial al_tripped= 1'b0;
341
        always @(posedge i_clk)
342
        begin
343
                if ((al_sel)&&(i_wb_we))
344
                begin
345
                        // Only adjust the alarm hours if the requested hours
346
                        // are valid.  This allows writes to the register,
347
                        // without a prior read, to leave these configuration
348
                        // bits alone.
349
                        if (i_wb_data[21:16] != 6'h3f)
350
                                alarm_time[21:16] <= i_wb_data[21:16];
351
                        // Here's the same thing for the minutes: only adjust
352
                        // the alarm minutes if the new bits are not all 1's. 
353
                        if (i_wb_data[15:8] != 8'hff)
354
                                alarm_time[15:8] <= i_wb_data[15:8];
355
                        // Here's the same thing for the seconds: only adjust
356
                        // the alarm minutes if the new bits are not all 1's. 
357
                        if (i_wb_data[7:0] != 8'hff)
358
                                alarm_time[7:0] <= i_wb_data[7:0];
359
                        al_enabled <= i_wb_data[24];
360
                        // Reset the alarm if a '1' is written to the tripped
361
                        // register, or if the alarm is disabled.
362
                        if ((i_wb_data[25])||(~i_wb_data[24]))
363
                                al_tripped <= 1'b0;
364
                end
365
 
366
                al_int <= 1'b0;
367
                if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
368
                        &&(al_enabled))
369
                begin
370
                        al_tripped <= 1'b1;
371
                        al_int <= 1'b1;
372
                end
373
        end
374
 
375
        //
376
        // The ckspeed register is equal to 2^48 divded by the number of
377
        // clock ticks you expect per second.  Adjust high for a slower
378
        // clock, lower for a faster clock.  In this fashion, a single
379
        // real time clock RTL file can handle tracking the clock in any
380
        // device.  Further, because this is only the lower 32 bits of a 
381
        // 48 bit counter per seconds, the clock jitter is kept below
382
        // 1 part in 65 thousand.
383
        //
384 7 dgisselq
        initial ckspeed = DEFAULT_SPEED;
385 2 dgisselq
        // In the case of verilator, comment the above and uncomment the line
386
        // below.  The clock constant below is "close" to simulation time,
387
        // meaning that my verilator simulation is running about 300x slower
388
        // than board time.
389
        // initial      ckspeed = 32'd786432000;
390
        always @(posedge i_clk)
391
                if ((sp_sel)&&(i_wb_we))
392
                        ckspeed <= i_wb_data;
393
 
394
        // 
395
        // If you want very fine precision control over your clock, you need
396
        // to be able to transfer time from one location to another.  This
397
        // is the beginning of that means: by setting a wire, i_hack, high
398
        // on a particular input, you can then read (later) what the clock
399
        // time was on that input.
400
        //
401
        // What's missing from this high precision adjustment mechanism is a
402
        // means of actually adjusting this time based upon the time 
403
        // difference you measure here between the hack time and some time
404
        // on another clock, but we'll get there.
405
        //
406
        reg             r_hack_carry;
407
        reg     [29:0]   hack_time;
408
        reg     [39:0]   hack_counter;
409 4 dgisselq
        initial hack_time    = 30'h0000;
410
        initial hack_counter = 40'h0000;
411 2 dgisselq
        always @(posedge i_clk)
412
                if (i_hack)
413
                begin
414
                        hack_time <= { clock[21:0], ck_sub };
415
                        hack_counter <= ck_counter;
416
                        r_hack_carry <= ck_carry;
417
                        // if ck_carry is set, the clock register is in the
418
                        // middle of a two clock update.  In that case ....
419
                end else if (r_hack_carry)
420
                begin // update again on the next clock to get the correct
421
                        // hack time.
422
                        hack_time <= { clock[21:0], ck_sub };
423
                        r_hack_carry <= 1'b0;
424
                end
425
 
426
        reg     [15:0]   h_sseg;
427 6 dgisselq
        reg     [3:1]   dmask;
428 2 dgisselq
        always @(posedge i_clk)
429 7 dgisselq
                case(clock[25:24])
430
                2'h1: begin h_sseg <= timer[15:0];
431 6 dgisselq
                        if (tm_alarm) dmask <= 3'h7;
432 4 dgisselq
                        else begin
433
                                dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
434
                                dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
435
                                dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
436 6 dgisselq
                                // dmask[0] <= 1'b1; // Always on
437 4 dgisselq
                        end end
438 7 dgisselq
                2'h2: begin h_sseg <= stopwatch[19:4];
439 4 dgisselq
                                dmask[3] <= (12'h00  != stopwatch[27:16]);
440
                                dmask[2] <= (16'h000 != stopwatch[27:12]);
441
                                dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
442 6 dgisselq
                                // dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
443 4 dgisselq
                        end
444 7 dgisselq
                2'h3: begin h_sseg <= ck_last_clock[15:0];
445 6 dgisselq
                                dmask[3:1] <= 3'h7;
446 4 dgisselq
                        end
447
                default: begin // 4'h0
448
                        h_sseg <= { 2'b00, ck_last_clock[21:8] };
449 6 dgisselq
                        dmask[2:1] <= 2'b11;
450 4 dgisselq
                        dmask[3] <= (2'b00 != ck_last_clock[21:20]);
451
                        end
452 2 dgisselq
                endcase
453
 
454
        wire    [31:0]   w_sseg;
455 4 dgisselq
        assign  w_sseg[ 0] =  (~ck_sub[7]);
456 7 dgisselq
        assign  w_sseg[ 8] =  (clock[25:24] == 2'h2);
457
        assign  w_sseg[16] = ((clock[25:24] == 2'h0)&&(~ck_sub[7]))||(clock[25:24] == 2'h3);
458 2 dgisselq
        assign  w_sseg[24] = 1'b0;
459
        hexmap  ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
460
        hexmap  hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
461
        hexmap  hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
462
        hexmap  hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
463
 
464
        always @(posedge i_clk)
465
                if ((tm_alarm || al_tripped)&&(ck_sub[7]))
466
                        o_sseg <= 32'h0000;
467
                else
468 4 dgisselq
                        o_sseg <= {
469
                                (dmask[3])?w_sseg[31:24]:8'h00,
470
                                (dmask[2])?w_sseg[23:16]:8'h00,
471
                                (dmask[1])?w_sseg[15: 8]:8'h00,
472 6 dgisselq
                                w_sseg[ 7: 0] };
473 2 dgisselq
 
474
        reg     [17:0]   ledreg;
475
        always @(posedge i_clk)
476
                if ((ck_pps)&&(ck_ppm))
477
                        ledreg <= 18'h00;
478
                else if (ck_carry)
479
                        ledreg <= ledreg + 18'h11;
480 4 dgisselq
        assign  o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:
481
                                { ledreg[17:10],
482
                                ledreg[10], ledreg[11], ledreg[12], ledreg[13],
483
                                ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
484 2 dgisselq
 
485
        assign  o_interrupt = tm_int || al_int;
486
 
487 5 dgisselq
        // A once-per day strobe, on the last second of the day so that the
488
        // the next clock is the first clock of the day.  This is useful for
489
        // connecting this module to a year/month/date date/calendar module.
490
        assign  o_ppd = (ck_ppd)&&(ck_pps);
491
 
492 2 dgisselq
        always @(posedge i_clk)
493
                case(i_wb_addr[2:0])
494 7 dgisselq
                3'b000: o_data <= { 6'h00, clock[25:22], ck_last_clock };
495 4 dgisselq
                3'b001: o_data <= { 6'h00, timer };
496 2 dgisselq
                3'b010: o_data <= stopwatch;
497
                3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
498
                3'b100: o_data <= ckspeed;
499
                3'b101: o_data <= { 2'b00, hack_time };
500
                3'b110: o_data <= hack_counter[39:8];
501
                3'b111: o_data <= { hack_counter[7:0], 24'h00 };
502
                endcase
503
 
504
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.