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[/] [rtcclock/] [trunk/] [rtl/] [rtcgps.v] - Blame information for rev 8

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///////////////////////////////////////////////////////////////////////////
//
// Filename:    rtcgps.v
//              
// Project:     A Wishbone Controlled Real--time Clock Core, w/ GPS synch
//
// Purpose:     Implement a real time clock, including alarm, count--down
//              timer, stopwatch, variable time frequency, and more.
//
//      This particular version has hooks for a GPS 1PPS, as well as a 
//      finely tracked clock speed output, to allow for fine clock precision
//      and good freewheeling even if/when GPS is lost.
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
module  rtcgps(i_clk,
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                //      o_wb_ack, o_wb_stb, o_wb_data, // no reads here
                // // Button inputs
                // i_btn,
                // Output registers
                o_data, // multiplexed based upon i_wb_addr
                // Output controls
                o_sseg, o_led, o_interrupt,
                // A once-per-day strobe on the last clock of the day
                o_ppd,
                // GPS interface
                i_gps_valid, i_gps_pps, i_gps_ckspeed,
                // Our personal timing, for debug purposes
                o_rtc_pps);
        parameter       DEFAULT_SPEED = 32'd2814750; //2af31e = 2^48 / 100e6 MHz
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   [1:0]    i_wb_addr;
        input   [31:0]   i_wb_data;
        // input                i_btn;
        output  reg     [31:0]   o_data;
        output  reg     [31:0]   o_sseg;
        output  wire    [15:0]   o_led;
        output  wire            o_interrupt, o_ppd;
        // GPS interface
        input                   i_gps_valid, i_gps_pps;
        input           [31:0]   i_gps_ckspeed;
        // Personal PPS
        output  wire            o_rtc_pps;
 
        reg     [23:0]   clock;
        reg     [31:0]   stopwatch, ckspeed;
        reg     [25:0]   timer;
 
        wire    ck_sel, tm_sel, sw_sel, al_sel;
        assign  ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b00));
        assign  tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b01));
        assign  sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b10));
        assign  al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b11));
 
        reg     [39:0]   ck_counter;
        reg             ck_carry;
        always @(posedge i_clk)
                if ((i_gps_valid)&&(i_gps_pps))
                begin
                        ck_carry   <= 0;
                        // Start our counter 2 clocks into the future.
                        // Why?  Because if we hit the PPS, we'll be delayed
                        // one clock from true time.  This (hopefully) locks
                        // us back onto true time.  Further, if we end up
                        // off (i.e., go off before the GPS tick ...) then
                        // the GPS tick will put us back on track ... likewise
                        // we've got code following that should keep us from
                        // ever producing two PPS's per second.
                        ck_counter <= { 7'h00, ckspeed, 1'b0 };
                end else
                        { ck_carry, ck_counter }<=ck_counter+{ 8'h00, ckspeed };
 
        reg             ck_pps;
        reg             ck_ppm, ck_pph, ck_ppd;
        reg     [7:0]    ck_sub;
        initial clock = 24'h00000000;
        always @(posedge i_clk)
                if ((i_gps_pps)&&(i_gps_valid)&&(ck_sub[7]))
                        ck_pps <= 1'b1;
                else if ((ck_carry)&&(ck_sub == 8'hff))
                        ck_pps <= 1'b1;
                else
                        ck_pps <= 1'b0;
 
        assign  o_rtc_pps = ck_pps;
        always @(posedge i_clk)
        begin
                if ((i_gps_valid)&&(i_gps_pps))
                        ck_sub <= 0;
                else if (ck_carry)
                        ck_sub <= ck_sub + 1;
 
                if (ck_pps)
                begin // advance the seconds
                        if (clock[3:0] >= 4'h9)
                                clock[3:0] <= 4'h0;
                        else
                                clock[3:0] <= clock[3:0] + 4'h1;
                        if (clock[7:0] >= 8'h59)
                                clock[7:4] <= 4'h0;
                        else if (clock[3:0] >= 4'h9)
                                clock[7:4] <= clock[7:4] + 4'h1;
                end
                ck_ppm <= (clock[7:0] == 8'h59);
 
                if ((ck_pps)&&(ck_ppm))
                begin // advance the minutes
                        if (clock[11:8] >= 4'h9)
                                clock[11:8] <= 4'h0;
                        else
                                clock[11:8] <= clock[11:8] + 4'h1;
                        if (clock[15:8] >= 8'h59)
                                clock[15:12] <= 4'h0;
                        else if (clock[11:8] >= 4'h9)
                                clock[15:12] <= clock[15:12] + 4'h1;
                end
                ck_pph <= (clock[15:0] == 16'h5959);
 
                if ((ck_pps)&&(ck_pph))
                begin // advance the hours
                        if (clock[21:16] >= 6'h23)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= 2'h0;
                        end else if (clock[19:16] >= 4'h9)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= clock[21:20] + 2'h1;
                        end else begin
                                clock[19:16] <= clock[19:16] + 4'h1;
                        end
                end
                ck_ppd <= (clock[21:0] == 22'h235959);
 
 
                if ((ck_sel)&&(i_wb_we))
                begin
                        if (8'hff != i_wb_data[7:0])
                        begin
                                clock[7:0] <= i_wb_data[7:0];
                                ck_ppm <= (i_wb_data[7:0] == 8'h59);
                        end
                        if (8'hff != i_wb_data[15:8])
                        begin
                                clock[15:8] <= i_wb_data[15:8];
                                ck_pph <= (i_wb_data[15:8] == 8'h59);
                        end
                        if (6'h3f != i_wb_data[21:16])
                                clock[21:16] <= i_wb_data[21:16];
                        clock[23:22] <= i_wb_data[25:24];
                        if ((~i_gps_valid)&&(8'h00 == i_wb_data[7:0]))
                                ck_sub <= 8'h00;
                end
        end
 
        reg     [21:0]   ck_last_clock;
        always @(posedge i_clk)
                ck_last_clock <= clock[21:0];
 
        reg     tm_pps, tm_ppm, tm_int;
        wire    tm_stopped, tm_running, tm_alarm;
        assign  tm_stopped = ~timer[24];
        assign  tm_running =  timer[24];
        assign  tm_alarm   =  timer[25];
        reg     [23:0]           tm_start;
        reg     [7:0]            tm_sub;
        initial tm_start = 24'h00;
        initial timer    = 26'h00;
        initial tm_int   = 1'b0;
        initial tm_pps   = 1'b0;
        always @(posedge i_clk)
        begin
                if (ck_carry)
                begin
                        tm_sub <= tm_sub + 1;
                        tm_pps <= (tm_sub == 8'hff);
                end else
                        tm_pps <= 1'b0;
 
                if ((~tm_alarm)&&(tm_running)&&(tm_pps))
                begin // If we are running ...
                        timer[25] <= 1'b0;
                        if (timer[23:0] == 24'h00)
                                timer[25] <= 1'b1;
                        else if (timer[3:0] != 4'h0)
                                timer[3:0] <= timer[3:0]-4'h1;
                        else begin // last digit is a zero
                                timer[3:0] <= 4'h9;
                                if (timer[7:4] != 4'h0)
                                        timer[7:4] <= timer[7:4]-4'h1;
                                else begin // last two digits are zero
                                        timer[7:4] <= 4'h5;
                                        if (timer[11:8] != 4'h0)
                                                timer[11:8] <= timer[11:8]-4'h1;
                                        else begin // last three digits are zero
                                                timer[11:8] <= 4'h9;
                                                if (timer[15:12] != 4'h0)
                                                        timer[15:12] <= timer[15:12]-4'h1;
                                                else begin
                                                        timer[15:12] <= 4'h5;
                                                        if (timer[19:16] != 4'h0)
                                                                timer[19:16] <= timer[19:16]-4'h1;
                                                        else begin
                                                        //
                                                                timer[19:16] <= 4'h9;
                                                                timer[23:20] <= timer[23:20]-4'h1;
                                                        end
                                                end
                                        end
                                end
                        end
                end
 
                if((~tm_alarm)&&(tm_running))
                begin
                        timer[25] <= (timer[23:0] == 24'h00);
                        tm_int <= (timer[23:0] == 24'h00);
                end else tm_int <= 1'b0;
                if (tm_alarm)
                        timer[24] <= 1'b0;
 
                if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
                        // Only allowed to stop the timer, nothing more
                        timer[24] <= i_wb_data[24];
                else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
                begin
                        timer[24] <= i_wb_data[24];
                        if ((timer[24])||(i_wb_data[24]))
                                timer[25] <= 1'b0;
                        if (i_wb_data[23:0] != 24'h0000)
                        begin
                                timer[23:0] <= i_wb_data[23:0];
                                tm_start <= i_wb_data[23:0];
                                tm_sub <= 8'h00;
                        end else if (timer[23:0] == 24'h00)
                        begin // Resetting timer to last valid timer start val
                                timer[23:0] <= tm_start;
                                tm_sub <= 8'h00;
                        end
                        // Any write clears the alarm
                        timer[25] <= 1'b0;
                end
        end
 
        //
        // Stopwatch functionality
        //
        // Setting bit '0' starts the stop watch, clearing it stops it.
        // Writing to the register with bit '1' high will clear the stopwatch,
        // and return it to zero provided that the stopwatch is stopped either
        // before or after the write.  Hence, writing a '2' to the device
        // will always stop and clear it, whereas writing a '3' to the device
        // will only clear it if it was already stopped.
        reg             sw_pps, sw_ppm, sw_pph;
        reg     [7:0]    sw_sub;
        wire    sw_running;
        assign  sw_running = stopwatch[0];
        initial stopwatch = 32'h00000;
        always @(posedge i_clk)
        begin
                sw_pps <= 1'b0;
                if (sw_running)
                begin
                        if (ck_carry)
                        begin
                                sw_sub <= sw_sub + 1;
                                sw_pps <= (sw_sub == 8'hff);
                        end
                end
 
                stopwatch[7:1] <= sw_sub[7:1];
 
                if (sw_pps)
                begin // Second hand
                        if (stopwatch[11:8] >= 4'h9)
                                stopwatch[11:8] <= 4'h0;
                        else
                                stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
 
                        if (stopwatch[15:8] >= 8'h59)
                                stopwatch[15:12] <= 4'h0;
                        else if (stopwatch[11:8] >= 4'h9)
                                stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
                        sw_ppm <= (stopwatch[15:8] == 8'h59);
                end else sw_ppm <= 1'b0;
 
                if (sw_ppm)
                begin // Minutes
                        if (stopwatch[19:16] >= 4'h9)
                                stopwatch[19:16] <= 4'h0;
                        else
                                stopwatch[19:16] <= stopwatch[19:16]+4'h1;
 
                        if (stopwatch[23:16] >= 8'h59)
                                stopwatch[23:20] <= 4'h0;
                        else if (stopwatch[19:16] >= 4'h9)
                                stopwatch[23:20] <= stopwatch[23:20]+4'h1;
                        sw_pph <= (stopwatch[23:16] == 8'h59);
                end else sw_pph <= 1'b0;
 
                if (sw_pph)
                begin // And hours
                        if (stopwatch[27:24] >= 4'h9)
                                stopwatch[27:24] <= 4'h0;
                        else
                                stopwatch[27:24] <= stopwatch[27:24]+4'h1;
 
                        if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
                                stopwatch[31:28] <= stopwatch[27:24]+4'h1;
                end
 
                if ((sw_sel)&&(i_wb_we))
                begin
                        stopwatch[0] <= i_wb_data[0];
                        if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
                        begin
                                stopwatch[31:1] <= 31'h00;
                                sw_sub <= 8'h00;
                                sw_pps <= 1'b0;
                                sw_ppm <= 1'b0;
                                sw_pph <= 1'b0;
                        end
                end
        end
 
        //
        // The alarm code
        //
        // Set the alarm register to the time you wish the board to "alarm".
        // The "alarm" will take place once per day at that time.  At that
        // time, the RTC code will generate a clock interrupt, and the CPU/host
        // can come and see that the alarm tripped.
        //
        // 
        reg     [21:0]           alarm_time;
        reg                     al_int,         // The alarm interrupt line
                                al_enabled,     // Whether the alarm is enabled
                                al_tripped;     // Whether the alarm has tripped
        initial al_enabled= 1'b0;
        initial al_tripped= 1'b0;
        always @(posedge i_clk)
        begin
                if ((al_sel)&&(i_wb_we))
                begin
                        // Only adjust the alarm hours if the requested hours
                        // are valid.  This allows writes to the register,
                        // without a prior read, to leave these configuration
                        // bits alone.
                        if (i_wb_data[21:16] != 6'h3f)
                                alarm_time[21:16] <= i_wb_data[21:16];
                        // Here's the same thing for the minutes: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[15:8] != 8'hff)
                                alarm_time[15:8] <= i_wb_data[15:8];
                        // Here's the same thing for the seconds: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[7:0] != 8'hff)
                                alarm_time[7:0] <= i_wb_data[7:0];
                        al_enabled <= i_wb_data[24];
                        // Reset the alarm if a '1' is written to the tripped
                        // register, or if the alarm is disabled.
                        if ((i_wb_data[25])||(~i_wb_data[24]))
                                al_tripped <= 1'b0;
                end
 
                al_int <= 1'b0;
                if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)&&(al_enabled))
                begin
                        al_tripped <= 1'b1;
                        al_int <= 1'b1;
                end
        end
 
        //
        // The ckspeed register is equal to 2^48 divded by the number of
        // clock ticks you expect per second.  Adjust high for a slower
        // clock, lower for a faster clock.  In this fashion, a single
        // real time clock RTL file can handle tracking the clock in any
        // device.  Further, because this is only the lower 32 bits of a 
        // 48 bit counter per seconds, the clock jitter is kept below
        // 1 part in 65 thousand.
        //
        initial ckspeed = DEFAULT_SPEED;
        // In the case of verilator, comment the above and uncomment the line
        // below.  The clock constant below is "close" to simulation time,
        // meaning that my verilator simulation is running about 300x slower
        // than board time.
        // initial      ckspeed = 32'd786432000;
        always @(posedge i_clk)
                if (i_gps_valid)
                        ckspeed <= i_gps_ckspeed;
 
        reg     [15:0]   h_sseg;
        reg     [3:1]   dmask;
        always @(posedge i_clk)
                case(clock[23:22])
                2'h1: begin h_sseg <= timer[15:0];
                        if (tm_alarm) dmask <= 3'h7;
                        else begin
                                dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
                                dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
                                dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
                                // dmask[0] <= 1'b1; // Always on
                        end end
                2'h2: begin h_sseg <= stopwatch[19:4];
                                dmask[3] <= (12'h00  != stopwatch[27:16]);
                                dmask[2] <= (16'h000 != stopwatch[27:12]);
                                dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
                                // dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
                        end
                2'h3: begin h_sseg <= clock[15:0];
                                dmask[3:1] <= 3'h7;
                        end
                default: begin // 4'h0
                        h_sseg <= { 2'b00, clock[21:8] };
                        dmask[2:1] <= 2'b11;
                        dmask[3] <= (2'b00 != clock[21:20]);
                        end
                endcase
 
        wire    [31:0]   w_sseg;
        assign  w_sseg[ 0] =  (i_gps_valid)?(ck_sub[7:5]==3'h0):(~ck_sub[0]);
        assign  w_sseg[ 8] =  (i_gps_valid)?(ck_sub[7:5]==3'h0):(~ck_sub[0]);
        assign  w_sseg[16] =  (i_gps_valid)?(ck_sub[7:5]==3'h0):(~ck_sub[0]);
        // assign       w_sseg[ 8] =  w_sseg[0];
        // assign       w_sseg[16] =  w_sseg[0];
        assign  w_sseg[24] = 1'b0;
        hexmap  ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
        hexmap  hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
        hexmap  hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
        hexmap  hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
 
        always @(posedge i_clk)
                if ((tm_alarm || al_tripped)&&(ck_sub[7]))
                        o_sseg <= 32'h0000;
                else
                        o_sseg <= {
                                (dmask[3])?w_sseg[31:24]:8'h00,
                                (dmask[2])?w_sseg[23:16]:8'h00,
                                (dmask[1])?w_sseg[15: 8]:8'h00,
                                w_sseg[ 7: 0] };
 
        reg     [17:0]   ledreg;
        always @(posedge i_clk)
                if ((ck_pps)&&(ck_ppm))
                        ledreg <= 18'h00;
                else if (ck_carry)
                        ledreg <= ledreg + 18'h11;
        assign  o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:
                                { ledreg[17:10],
                                ledreg[10], ledreg[11], ledreg[12], ledreg[13],
                                ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
 
        assign  o_interrupt = tm_int || al_int;
 
        // A once-per day strobe, on the last second of the day so that the
        // the next clock is the first clock of the day.  This is useful for
        // connecting this module to a year/month/date date/calendar module.
        assign  o_ppd = (ck_ppd)&&(ck_pps);
 
        always @(posedge i_clk)
                case(i_wb_addr)
                2'b00: o_data <= { ~i_gps_valid, 5'h0, clock[23:22], 2'b00, clock[21:0] };
                2'b01: o_data <= { 6'h00, timer };
                2'b10: o_data <= stopwatch;
                2'b11: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
                endcase
 
endmodule

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[/] [rtcclock/] [trunk/] [rtl/] [rtcgps.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	7	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: rtcgps.v`
4			`//`
5			`// Project: A Wishbone Controlled Real--time Clock Core, w/ GPS synch`
6			`//`
7			`// Purpose: Implement a real time clock, including alarm, count--down`
8			`// timer, stopwatch, variable time frequency, and more.`
9			`//`
10			`// This particular version has hooks for a GPS 1PPS, as well as a`
11			`// finely tracked clock speed output, to allow for fine clock precision`
12			`// and good freewheeling even if/when GPS is lost.`
13			`//`
14			`//`
15			`// Creator: Dan Gisselquist, Ph.D.`
16	8	dgisselq	`// Gisselquist Technology, LLC`
17	7	dgisselq	`//`
18			`///////////////////////////////////////////////////////////////////////////`
19			`//`
20			`// Copyright (C) 2015, Gisselquist Technology, LLC`
21			`//`
22			`// This program is free software (firmware): you can redistribute it and/or`
23			`// modify it under the terms of the GNU General Public License as published`
24			`// by the Free Software Foundation, either version 3 of the License, or (at`
25			`// your option) any later version.`
26			`//`
27			`// This program is distributed in the hope that it will be useful, but WITHOUT`
28			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
29			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
30			`// for more details.`
31			`//`
32			`// You should have received a copy of the GNU General Public License along`
33			`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
34			`// target there if the PDF file isn't present.) If not, see`
35			`// <http://www.gnu.org/licenses/> for a copy.`
36			`//`
37			`// License: GPL, v3, as defined and found on www.gnu.org,`
38			`// http://www.gnu.org/licenses/gpl.html`
39			`//`
40			`//`
41			`///////////////////////////////////////////////////////////////////////////`
42			`module rtcgps(i_clk,`
43			`// Wishbone interface`
44			`i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,`
45			`// o_wb_ack, o_wb_stb, o_wb_data, // no reads here`
46			`// // Button inputs`
47			`// i_btn,`
48			`// Output registers`
49			`o_data, // multiplexed based upon i_wb_addr`
50			`// Output controls`
51			`o_sseg, o_led, o_interrupt,`
52			`// A once-per-day strobe on the last clock of the day`
53			`o_ppd,`
54			`// GPS interface`
55	8	dgisselq	`i_gps_valid, i_gps_pps, i_gps_ckspeed,`
56			`// Our personal timing, for debug purposes`
57			`o_rtc_pps);`
58	7	dgisselq	`parameter DEFAULT_SPEED = 32'd2814750; //2af31e = 2^48 / 100e6 MHz`
59			`input i_clk;`
60			`input i_wb_cyc, i_wb_stb, i_wb_we;`
61			`input [1:0] i_wb_addr;`
62			`input [31:0] i_wb_data;`
63			`// input i_btn;`
64			`output reg [31:0] o_data;`
65			`output reg [31:0] o_sseg;`
66			`output wire [15:0] o_led;`
67			`output wire o_interrupt, o_ppd;`
68			`// GPS interface`
69			`input i_gps_valid, i_gps_pps;`
70			`input [31:0] i_gps_ckspeed;`
71	8	dgisselq	`// Personal PPS`
72			`output wire o_rtc_pps;`
73	7	dgisselq
74			`reg [23:0] clock;`
75			`reg [31:0] stopwatch, ckspeed;`
76			`reg [25:0] timer;`
77
78			`wire ck_sel, tm_sel, sw_sel, al_sel;`
79			`assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b00));`
80			`assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b01));`
81			`assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b10));`
82			`assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr==2'b11));`
83
84			`reg [39:0] ck_counter;`
85			`reg ck_carry;`
86			`always @(posedge i_clk)`
87	8	dgisselq	`if ((i_gps_valid)&&(i_gps_pps))`
88			`begin`
89			`ck_carry <= 0;`
90			`// Start our counter 2 clocks into the future.`
91			`// Why? Because if we hit the PPS, we'll be delayed`
92			`// one clock from true time. This (hopefully) locks`
93			`// us back onto true time. Further, if we end up`
94			`// off (i.e., go off before the GPS tick ...) then`
95			`// the GPS tick will put us back on track ... likewise`
96			`// we've got code following that should keep us from`
97			`// ever producing two PPS's per second.`
98			`ck_counter <= { 7'h00, ckspeed, 1'b0 };`
99			`end else`
100			`{ ck_carry, ck_counter }<=ck_counter+{ 8'h00, ckspeed };`
101	7	dgisselq
102	8	dgisselq	`reg ck_pps;`
103			`reg ck_ppm, ck_pph, ck_ppd;`
104	7	dgisselq	`reg [7:0] ck_sub;`
105			`initial clock = 24'h00000000;`
106			`always @(posedge i_clk)`
107	8	dgisselq	`if ((i_gps_pps)&&(i_gps_valid)&&(ck_sub[7]))`
108			`ck_pps <= 1'b1;`
109			`else if ((ck_carry)&&(ck_sub == 8'hff))`
110			`ck_pps <= 1'b1;`
111			`else`
112			`ck_pps <= 1'b0;`
113
114			`assign o_rtc_pps = ck_pps;`
115			`always @(posedge i_clk)`
116	7	dgisselq	`begin`
117			`if ((i_gps_valid)&&(i_gps_pps))`
118			`ck_sub <= 0;`
119			`else if (ck_carry)`
120			`ck_sub <= ck_sub + 1;`
121
122			`if (ck_pps)`
123			`begin // advance the seconds`
124			`if (clock[3:0] >= 4'h9)`
125			`clock[3:0] <= 4'h0;`
126			`else`
127			`clock[3:0] <= clock[3:0] + 4'h1;`
128			`if (clock[7:0] >= 8'h59)`
129			`clock[7:4] <= 4'h0;`
130			`else if (clock[3:0] >= 4'h9)`
131			`clock[7:4] <= clock[7:4] + 4'h1;`
132			`end`
133			`ck_ppm <= (clock[7:0] == 8'h59);`
134
135			`if ((ck_pps)&&(ck_ppm))`
136			`begin // advance the minutes`
137			`if (clock[11:8] >= 4'h9)`
138			`clock[11:8] <= 4'h0;`
139			`else`
140			`clock[11:8] <= clock[11:8] + 4'h1;`
141			`if (clock[15:8] >= 8'h59)`
142			`clock[15:12] <= 4'h0;`
143			`else if (clock[11:8] >= 4'h9)`
144			`clock[15:12] <= clock[15:12] + 4'h1;`
145			`end`
146			`ck_pph <= (clock[15:0] == 16'h5959);`
147
148			`if ((ck_pps)&&(ck_pph))`
149			`begin // advance the hours`
150			`if (clock[21:16] >= 6'h23)`
151			`begin`
152			`clock[19:16] <= 4'h0;`
153			`clock[21:20] <= 2'h0;`
154			`end else if (clock[19:16] >= 4'h9)`
155			`begin`
156			`clock[19:16] <= 4'h0;`
157			`clock[21:20] <= clock[21:20] + 2'h1;`
158			`end else begin`
159			`clock[19:16] <= clock[19:16] + 4'h1;`
160			`end`
161			`end`
162			`ck_ppd <= (clock[21:0] == 22'h235959);`
163
164
165			`if ((ck_sel)&&(i_wb_we))`
166			`begin`
167			`if (8'hff != i_wb_data[7:0])`
168			`begin`
169			`clock[7:0] <= i_wb_data[7:0];`
170			`ck_ppm <= (i_wb_data[7:0] == 8'h59);`
171			`end`
172			`if (8'hff != i_wb_data[15:8])`
173			`begin`
174			`clock[15:8] <= i_wb_data[15:8];`
175			`ck_pph <= (i_wb_data[15:8] == 8'h59);`
176			`end`
177			`if (6'h3f != i_wb_data[21:16])`
178			`clock[21:16] <= i_wb_data[21:16];`
179			`clock[23:22] <= i_wb_data[25:24];`
180			`if ((~i_gps_valid)&&(8'h00 == i_wb_data[7:0]))`
181			`ck_sub <= 8'h00;`
182			`end`
183			`end`
184
185			`reg [21:0] ck_last_clock;`
186			`always @(posedge i_clk)`
187			`ck_last_clock <= clock[21:0];`
188
189			`reg tm_pps, tm_ppm, tm_int;`
190			`wire tm_stopped, tm_running, tm_alarm;`
191			`assign tm_stopped = ~timer[24];`
192			`assign tm_running = timer[24];`
193			`assign tm_alarm = timer[25];`
194			`reg [23:0] tm_start;`
195			`reg [7:0] tm_sub;`
196			`initial tm_start = 24'h00;`
197			`initial timer = 26'h00;`
198			`initial tm_int = 1'b0;`
199			`initial tm_pps = 1'b0;`
200			`always @(posedge i_clk)`
201			`begin`
202			`if (ck_carry)`
203			`begin`
204			`tm_sub <= tm_sub + 1;`
205			`tm_pps <= (tm_sub == 8'hff);`
206			`end else`
207			`tm_pps <= 1'b0;`
208
209			`if ((~tm_alarm)&&(tm_running)&&(tm_pps))`
210			`begin // If we are running ...`
211			`timer[25] <= 1'b0;`
212			`if (timer[23:0] == 24'h00)`
213			`timer[25] <= 1'b1;`
214			`else if (timer[3:0] != 4'h0)`
215			`timer[3:0] <= timer[3:0]-4'h1;`
216			`else begin // last digit is a zero`
217			`timer[3:0] <= 4'h9;`
218			`if (timer[7:4] != 4'h0)`
219			`timer[7:4] <= timer[7:4]-4'h1;`
220			`else begin // last two digits are zero`
221			`timer[7:4] <= 4'h5;`
222			`if (timer[11:8] != 4'h0)`
223			`timer[11:8] <= timer[11:8]-4'h1;`
224			`else begin // last three digits are zero`
225			`timer[11:8] <= 4'h9;`
226			`if (timer[15:12] != 4'h0)`
227			`timer[15:12] <= timer[15:12]-4'h1;`
228			`else begin`
229			`timer[15:12] <= 4'h5;`
230			`if (timer[19:16] != 4'h0)`
231			`timer[19:16] <= timer[19:16]-4'h1;`
232			`else begin`
233			`//`
234			`timer[19:16] <= 4'h9;`
235			`timer[23:20] <= timer[23:20]-4'h1;`
236			`end`
237			`end`
238			`end`
239			`end`
240			`end`
241			`end`
242
243			`if((~tm_alarm)&&(tm_running))`
244			`begin`
245			`timer[25] <= (timer[23:0] == 24'h00);`
246			`tm_int <= (timer[23:0] == 24'h00);`
247			`end else tm_int <= 1'b0;`
248			`if (tm_alarm)`
249			`timer[24] <= 1'b0;`
250
251			`if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running`
252			`// Only allowed to stop the timer, nothing more`
253			`timer[24] <= i_wb_data[24];`
254			`else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off`
255			`begin`
256			`timer[24] <= i_wb_data[24];`
257			`if ((timer[24])\|\|(i_wb_data[24]))`
258			`timer[25] <= 1'b0;`
259			`if (i_wb_data[23:0] != 24'h0000)`
260			`begin`
261			`timer[23:0] <= i_wb_data[23:0];`
262			`tm_start <= i_wb_data[23:0];`
263			`tm_sub <= 8'h00;`
264			`end else if (timer[23:0] == 24'h00)`
265			`begin // Resetting timer to last valid timer start val`
266			`timer[23:0] <= tm_start;`
267			`tm_sub <= 8'h00;`
268			`end`
269			`// Any write clears the alarm`
270			`timer[25] <= 1'b0;`
271			`end`
272			`end`
273
274			`//`
275			`// Stopwatch functionality`
276			`//`
277			`// Setting bit '0' starts the stop watch, clearing it stops it.`
278			`// Writing to the register with bit '1' high will clear the stopwatch,`
279			`// and return it to zero provided that the stopwatch is stopped either`
280			`// before or after the write. Hence, writing a '2' to the device`
281			`// will always stop and clear it, whereas writing a '3' to the device`
282			`// will only clear it if it was already stopped.`
283			`reg sw_pps, sw_ppm, sw_pph;`
284			`reg [7:0] sw_sub;`
285			`wire sw_running;`
286			`assign sw_running = stopwatch[0];`
287			`initial stopwatch = 32'h00000;`
288			`always @(posedge i_clk)`
289			`begin`
290			`sw_pps <= 1'b0;`
291			`if (sw_running)`
292			`begin`
293			`if (ck_carry)`
294			`begin`
295			`sw_sub <= sw_sub + 1;`
296			`sw_pps <= (sw_sub == 8'hff);`
297			`end`
298			`end`
299
300			`stopwatch[7:1] <= sw_sub[7:1];`
301
302			`if (sw_pps)`
303			`begin // Second hand`
304			`if (stopwatch[11:8] >= 4'h9)`
305			`stopwatch[11:8] <= 4'h0;`
306			`else`
307			`stopwatch[11:8] <= stopwatch[11:8] + 4'h1;`
308
309			`if (stopwatch[15:8] >= 8'h59)`
310			`stopwatch[15:12] <= 4'h0;`
311			`else if (stopwatch[11:8] >= 4'h9)`
312			`stopwatch[15:12] <= stopwatch[15:12] + 4'h1;`
313			`sw_ppm <= (stopwatch[15:8] == 8'h59);`
314			`end else sw_ppm <= 1'b0;`
315
316			`if (sw_ppm)`
317			`begin // Minutes`
318			`if (stopwatch[19:16] >= 4'h9)`
319			`stopwatch[19:16] <= 4'h0;`
320			`else`
321			`stopwatch[19:16] <= stopwatch[19:16]+4'h1;`
322
323			`if (stopwatch[23:16] >= 8'h59)`
324			`stopwatch[23:20] <= 4'h0;`
325			`else if (stopwatch[19:16] >= 4'h9)`
326			`stopwatch[23:20] <= stopwatch[23:20]+4'h1;`
327			`sw_pph <= (stopwatch[23:16] == 8'h59);`
328			`end else sw_pph <= 1'b0;`
329
330			`if (sw_pph)`
331			`begin // And hours`
332			`if (stopwatch[27:24] >= 4'h9)`
333			`stopwatch[27:24] <= 4'h0;`
334			`else`
335			`stopwatch[27:24] <= stopwatch[27:24]+4'h1;`
336
337			`if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))`
338			`stopwatch[31:28] <= stopwatch[27:24]+4'h1;`
339			`end`
340
341			`if ((sw_sel)&&(i_wb_we))`
342			`begin`
343			`stopwatch[0] <= i_wb_data[0];`
344			`if((i_wb_data[1])&&((~stopwatch[0])\|\|(~i_wb_data[0])))`
345			`begin`
346			`stopwatch[31:1] <= 31'h00;`
347			`sw_sub <= 8'h00;`
348			`sw_pps <= 1'b0;`
349			`sw_ppm <= 1'b0;`
350			`sw_pph <= 1'b0;`
351			`end`
352			`end`
353			`end`
354
355			`//`
356			`// The alarm code`
357			`//`
358			`// Set the alarm register to the time you wish the board to "alarm".`
359			`// The "alarm" will take place once per day at that time. At that`
360			`// time, the RTC code will generate a clock interrupt, and the CPU/host`
361			`// can come and see that the alarm tripped.`
362			`//`
363			`//`
364			`reg [21:0] alarm_time;`
365			`reg al_int, // The alarm interrupt line`
366			`al_enabled, // Whether the alarm is enabled`
367			`al_tripped; // Whether the alarm has tripped`
368			`initial al_enabled= 1'b0;`
369			`initial al_tripped= 1'b0;`
370			`always @(posedge i_clk)`
371			`begin`
372			`if ((al_sel)&&(i_wb_we))`
373			`begin`
374			`// Only adjust the alarm hours if the requested hours`
375			`// are valid. This allows writes to the register,`
376			`// without a prior read, to leave these configuration`
377			`// bits alone.`
378			`if (i_wb_data[21:16] != 6'h3f)`
379			`alarm_time[21:16] <= i_wb_data[21:16];`
380			`// Here's the same thing for the minutes: only adjust`
381			`// the alarm minutes if the new bits are not all 1's.`
382			`if (i_wb_data[15:8] != 8'hff)`
383			`alarm_time[15:8] <= i_wb_data[15:8];`
384			`// Here's the same thing for the seconds: only adjust`
385			`// the alarm minutes if the new bits are not all 1's.`
386			`if (i_wb_data[7:0] != 8'hff)`
387			`alarm_time[7:0] <= i_wb_data[7:0];`
388			`al_enabled <= i_wb_data[24];`
389			`// Reset the alarm if a '1' is written to the tripped`
390			`// register, or if the alarm is disabled.`
391			`if ((i_wb_data[25])\|\|(~i_wb_data[24]))`
392			`al_tripped <= 1'b0;`
393			`end`
394
395			`al_int <= 1'b0;`
396			`if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)&&(al_enabled))`
397			`begin`
398			`al_tripped <= 1'b1;`
399			`al_int <= 1'b1;`
400			`end`
401			`end`
402
403			`//`
404			`// The ckspeed register is equal to 2^48 divded by the number of`
405			`// clock ticks you expect per second. Adjust high for a slower`
406			`// clock, lower for a faster clock. In this fashion, a single`
407			`// real time clock RTL file can handle tracking the clock in any`
408			`// device. Further, because this is only the lower 32 bits of a`
409			`// 48 bit counter per seconds, the clock jitter is kept below`
410			`// 1 part in 65 thousand.`
411			`//`
412			`initial ckspeed = DEFAULT_SPEED;`
413			`// In the case of verilator, comment the above and uncomment the line`
414			`// below. The clock constant below is "close" to simulation time,`
415			`// meaning that my verilator simulation is running about 300x slower`
416			`// than board time.`
417			`// initial ckspeed = 32'd786432000;`
418			`always @(posedge i_clk)`
419			`if (i_gps_valid)`
420			`ckspeed <= i_gps_ckspeed;`
421
422			`reg [15:0] h_sseg;`
423			`reg [3:1] dmask;`
424			`always @(posedge i_clk)`
425			`case(clock[23:22])`
426			`2'h1: begin h_sseg <= timer[15:0];`
427			`if (tm_alarm) dmask <= 3'h7;`
428			`else begin`
429			`dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]`
430			`dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]`
431			`dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]`
432			`// dmask[0] <= 1'b1; // Always on`
433			`end end`
434			`2'h2: begin h_sseg <= stopwatch[19:4];`
435			`dmask[3] <= (12'h00 != stopwatch[27:16]);`
436			`dmask[2] <= (16'h000 != stopwatch[27:12]);`
437			`dmask[1] <= 1'b1; // Always on, stopwatch[11:8]`
438			`// dmask[0] <= 1'b1; // Always on, stopwatch[7:4]`
439			`end`
440			`2'h3: begin h_sseg <= clock[15:0];`
441			`dmask[3:1] <= 3'h7;`
442			`end`
443			`default: begin // 4'h0`
444			`h_sseg <= { 2'b00, clock[21:8] };`
445			`dmask[2:1] <= 2'b11;`
446			`dmask[3] <= (2'b00 != clock[21:20]);`
447			`end`
448			`endcase`
449
450			`wire [31:0] w_sseg;`
451	8	dgisselq	`assign w_sseg[ 0] = (i_gps_valid)?(ck_sub[7:5]==3'h0):(~ck_sub[0]);`
452			`assign w_sseg[ 8] = (i_gps_valid)?(ck_sub[7:5]==3'h0):(~ck_sub[0]);`
453			`assign w_sseg[16] = (i_gps_valid)?(ck_sub[7:5]==3'h0):(~ck_sub[0]);`
454			`// assign w_sseg[ 8] = w_sseg[0];`
455			`// assign w_sseg[16] = w_sseg[0];`
456	7	dgisselq	`assign w_sseg[24] = 1'b0;`
457			`hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);`
458			`hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);`
459			`hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);`
460			`hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);`
461
462			`always @(posedge i_clk)`
463			`if ((tm_alarm \|\| al_tripped)&&(ck_sub[7]))`
464			`o_sseg <= 32'h0000;`
465			`else`
466			`o_sseg <= {`
467			`(dmask[3])?w_sseg[31:24]:8'h00,`
468			`(dmask[2])?w_sseg[23:16]:8'h00,`
469			`(dmask[1])?w_sseg[15: 8]:8'h00,`
470			`w_sseg[ 7: 0] };`
471
472			`reg [17:0] ledreg;`
473			`always @(posedge i_clk)`
474			`if ((ck_pps)&&(ck_ppm))`
475			`ledreg <= 18'h00;`
476			`else if (ck_carry)`
477			`ledreg <= ledreg + 18'h11;`
478			`assign o_led = (tm_alarm\|\|al_tripped)?{ (16){ck_sub[7]}}:`
479			`{ ledreg[17:10],`
480			`ledreg[10], ledreg[11], ledreg[12], ledreg[13],`
481			`ledreg[14], ledreg[15], ledreg[16], ledreg[17] };`
482
483			`assign o_interrupt = tm_int \|\| al_int;`
484
485			`// A once-per day strobe, on the last second of the day so that the`
486			`// the next clock is the first clock of the day. This is useful for`
487			`// connecting this module to a year/month/date date/calendar module.`
488			`assign o_ppd = (ck_ppd)&&(ck_pps);`
489
490			`always @(posedge i_clk)`
491			`case(i_wb_addr)`
492			`2'b00: o_data <= { ~i_gps_valid, 5'h0, clock[23:22], 2'b00, clock[21:0] };`
493			`2'b01: o_data <= { 6'h00, timer };`
494			`2'b10: o_data <= stopwatch;`
495			`2'b11: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };`
496			`endcase`
497
498			`endmodule`