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///////////////////////////////////////////////////////////////////////////
//
// Filename:    rtclight.v
//              
// Project:     A Wishbone Controlled Real--time Clock Core
//
// Purpose:     Implement a real time clock, including alarm, count--down
//              timer, stopwatch, variable time frequency, and more.
//
//      This is a light-weight version of the RTC found in this directory.
//      Unlike the full RTC, this version does not support time hacks, seven
//      segment display outputs, or LED's.  It is an RTC for an internal core
//      only.  (That's how I was using it on one of my projects anyway ...)
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
module  rtclight(i_clk,
                // Wishbone interface
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                //      o_wb_ack, o_wb_stb, o_wb_data, // no reads here
                // // Button inputs
                // i_btn,
                // Output registers
                o_data, // multiplexed based upon i_wb_addr
                // Output controls
                o_interrupt,
                // A once-per-day strobe on the last clock of the day
                o_ppd);
        parameter       DEFAULT_SPEED = 32'd2814750;    // 100 Mhz
        input   i_clk;
        input   i_wb_cyc, i_wb_stb, i_wb_we;
        input   [2:0]    i_wb_addr;
        input   [31:0]   i_wb_data;
        // input                i_btn;
        output  reg     [31:0]   o_data;
        output  wire            o_interrupt, o_ppd;
 
        reg     [21:0]   clock;
        reg     [31:0]   stopwatch, ckspeed;
        reg     [25:0]   timer;
 
        wire    ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
        assign  ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
        assign  tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
        assign  sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
        assign  al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
        assign  sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
 
        reg             ck_carry;
        reg     [39:0]   ck_counter;
        initial         ck_carry = 1'b0;
        initial         ck_counter = 40'h00;
        always @(posedge i_clk)
                { ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
 
        wire            ck_pps;
        reg             ck_prepps, ck_ppm, ck_pph, ck_ppd;
        reg     [7:0]    ck_sub;
        initial clock = 22'h00000;
        assign  ck_pps = (ck_carry)&&(ck_prepps);
        always @(posedge i_clk)
        begin
                if (ck_carry)
                        ck_sub <= ck_sub + 8'h1;
                ck_prepps <= (ck_sub == 8'hff);
 
                if (ck_pps)
                begin // advance the seconds
                        if (clock[3:0] >= 4'h9)
                                clock[3:0] <= 4'h0;
                        else
                                clock[3:0] <= clock[3:0] + 4'h1;
                        if (clock[7:0] >= 8'h59)
                                clock[7:4] <= 4'h0;
                        else if (clock[3:0] >= 4'h9)
                                clock[7:4] <= clock[7:4] + 4'h1;
                end
                ck_ppm <= (clock[7:0] == 8'h59);
 
                if ((ck_pps)&&(ck_ppm))
                begin // advance the minutes
                        if (clock[11:8] >= 4'h9)
                                clock[11:8] <= 4'h0;
                        else
                                clock[11:8] <= clock[11:8] + 4'h1;
                        if (clock[15:8] >= 8'h59)
                                clock[15:12] <= 4'h0;
                        else if (clock[11:8] >= 4'h9)
                                clock[15:12] <= clock[15:12] + 4'h1;
                end
                ck_pph <= (clock[15:0] == 16'h5959);
 
                if ((ck_pps)&&(ck_pph))
                begin // advance the hours
                        if (clock[21:16] >= 6'h23)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= 2'h0;
                        end else if (clock[19:16] >= 4'h9)
                        begin
                                clock[19:16] <= 4'h0;
                                clock[21:20] <= clock[21:20] + 2'h1;
                        end else begin
                                clock[19:16] <= clock[19:16] + 4'h1;
                        end
                end
                ck_ppd <= (clock[21:0] == 22'h235959);
 
 
                if ((ck_sel)&&(i_wb_we))
                begin
                        if (8'hff != i_wb_data[7:0])
                        begin
                                clock[7:0] <= i_wb_data[7:0];
                                ck_ppm <= (i_wb_data[7:0] == 8'h59);
                        end
                        if (8'hff != i_wb_data[15:8])
                        begin
                                clock[15:8] <= i_wb_data[15:8];
                                ck_pph <= (i_wb_data[15:8] == 8'h59);
                        end
                        if (6'h3f != i_wb_data[21:16])
                                clock[21:16] <= i_wb_data[21:16];
                        if (8'h00 == i_wb_data[7:0])
                                ck_sub <= 8'h00;
                end
        end
 
        // Clock updates take several clocks, so let's make sure we
        // are only looking at a valid clock value before testing it.
        reg     [21:0]           ck_last_clock;
        always @(posedge i_clk)
                ck_last_clock <= clock[21:0];
 
 
        reg     tm_pps, tm_ppm, tm_int;
        wire    tm_stopped, tm_running, tm_alarm;
        assign  tm_stopped = ~timer[24];
        assign  tm_running =  timer[24];
        assign  tm_alarm   =  timer[25];
        reg     [23:0]           tm_start;
        reg     [7:0]            tm_sub;
        initial tm_start = 24'h00;
        initial timer    = 26'h00;
        initial tm_int   = 1'b0;
        initial tm_pps   = 1'b0;
        always @(posedge i_clk)
        begin
                if (ck_carry)
                begin
                        tm_sub <= tm_sub + 8'h1;
                        tm_pps <= (tm_sub == 8'hff);
                end else
                        tm_pps <= 1'b0;
 
                if ((~tm_alarm)&&(tm_running)&&(tm_pps))
                begin // If we are running ...
                        timer[25] <= 1'b0;
                        if (timer[23:0] == 24'h00)
                                timer[25] <= 1'b1;
                        else if (timer[3:0] != 4'h0)
                                timer[3:0] <= timer[3:0]-4'h1;
                        else begin // last digit is a zero
                                timer[3:0] <= 4'h9;
                                if (timer[7:4] != 4'h0)
                                        timer[7:4] <= timer[7:4]-4'h1;
                                else begin // last two digits are zero
                                        timer[7:4] <= 4'h5;
                                        if (timer[11:8] != 4'h0)
                                                timer[11:8] <= timer[11:8]-4'h1;
                                        else begin // last three digits are zero
                                                timer[11:8] <= 4'h9;
                                                if (timer[15:12] != 4'h0)
                                                        timer[15:12] <= timer[15:12]-4'h1;
                                                else begin
                                                        timer[15:12] <= 4'h5;
                                                        if (timer[19:16] != 4'h0)
                                                                timer[19:16] <= timer[19:16]-4'h1;
                                                        else begin
                                                        //
                                                                timer[19:16] <= 4'h9;
                                                                timer[23:20] <= timer[23:20]-4'h1;
                                                        end
                                                end
                                        end
                                end
                        end
                end
 
                if((~tm_alarm)&&(tm_running))
                begin
                        timer[25] <= (timer[23:0] == 24'h00);
                        tm_int <= (timer[23:0] == 24'h00);
                end else tm_int <= 1'b0;
                if (tm_alarm)
                        timer[24] <= 1'b0;
 
                if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running
                        // Only allowed to stop the timer, nothing more
                        timer[24] <= i_wb_data[24];
                else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off
                begin
                        timer[24] <= i_wb_data[24];
                        if ((timer[24])||(i_wb_data[24]))
                                timer[25] <= 1'b0;
                        if (i_wb_data[23:0] != 24'h0000)
                        begin
                                timer[23:0] <= i_wb_data[23:0];
                                tm_start <= i_wb_data[23:0];
                                tm_sub <= 8'h00;
                        end else if (timer[23:0] == 24'h00)
                        begin // Resetting timer to last valid timer start val
                                timer[23:0] <= tm_start;
                                tm_sub <= 8'h00;
                        end
                        // Any write clears the alarm
                        timer[25] <= 1'b0;
                end
        end
 
        //
        // Stopwatch functionality
        //
        // Setting bit '0' starts the stop watch, clearing it stops it.
        // Writing to the register with bit '1' high will clear the stopwatch,
        // and return it to zero provided that the stopwatch is stopped either
        // before or after the write.  Hence, writing a '2' to the device
        // will always stop and clear it, whereas writing a '3' to the device
        // will only clear it if it was already stopped.
        reg             sw_pps, sw_ppm, sw_pph;
        reg     [7:0]    sw_sub;
        wire    sw_running;
        assign  sw_running = stopwatch[0];
        initial stopwatch = 32'h00000;
        always @(posedge i_clk)
        begin
                sw_pps <= 1'b0;
                if (sw_running)
                begin
                        if (ck_carry)
                        begin
                                sw_sub <= sw_sub + 8'h1;
                                sw_pps <= (sw_sub == 8'hff);
                        end
                end
 
                stopwatch[7:1] <= sw_sub[7:1];
 
                if (sw_pps)
                begin // Second hand
                        if (stopwatch[11:8] >= 4'h9)
                                stopwatch[11:8] <= 4'h0;
                        else
                                stopwatch[11:8] <= stopwatch[11:8] + 4'h1;
 
                        if (stopwatch[15:8] >= 8'h59)
                                stopwatch[15:12] <= 4'h0;
                        else if (stopwatch[11:8] >= 4'h9)
                                stopwatch[15:12] <= stopwatch[15:12] + 4'h1;
                        sw_ppm <= (stopwatch[15:8] == 8'h59);
                end else sw_ppm <= 1'b0;
 
                if (sw_ppm)
                begin // Minutes
                        if (stopwatch[19:16] >= 4'h9)
                                stopwatch[19:16] <= 4'h0;
                        else
                                stopwatch[19:16] <= stopwatch[19:16]+4'h1;
 
                        if (stopwatch[23:16] >= 8'h59)
                                stopwatch[23:20] <= 4'h0;
                        else if (stopwatch[19:16] >= 4'h9)
                                stopwatch[23:20] <= stopwatch[23:20]+4'h1;
                        sw_pph <= (stopwatch[23:16] == 8'h59);
                end else sw_pph <= 1'b0;
 
                if (sw_pph)
                begin // And hours
                        if (stopwatch[27:24] >= 4'h9)
                                stopwatch[27:24] <= 4'h0;
                        else
                                stopwatch[27:24] <= stopwatch[27:24]+4'h1;
 
                        if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))
                                stopwatch[31:28] <= stopwatch[27:24]+4'h1;
                end
 
                if ((sw_sel)&&(i_wb_we))
                begin
                        stopwatch[0] <= i_wb_data[0];
                        if((i_wb_data[1])&&((~stopwatch[0])||(~i_wb_data[0])))
                        begin
                                stopwatch[31:1] <= 31'h00;
                                sw_sub <= 8'h00;
                                sw_pps <= 1'b0;
                                sw_ppm <= 1'b0;
                                sw_pph <= 1'b0;
                        end
                end
        end
 
        //
        // The alarm code
        //
        // Set the alarm register to the time you wish the board to "alarm".
        // The "alarm" will take place once per day at that time.  At that
        // time, the RTC code will generate a clock interrupt, and the CPU/host
        // can come and see that the alarm tripped.
        //
        // 
        reg     [21:0]           alarm_time;
        reg                     al_int,         // The alarm interrupt line
                                al_enabled,     // Whether the alarm is enabled
                                al_tripped;     // Whether the alarm has tripped
        initial al_enabled= 1'b0;
        initial al_tripped= 1'b0;
        always @(posedge i_clk)
        begin
                if ((al_sel)&&(i_wb_we))
                begin
                        // Only adjust the alarm hours if the requested hours
                        // are valid.  This allows writes to the register,
                        // without a prior read, to leave these configuration
                        // bits alone.
                        if (i_wb_data[21:16] != 6'h3f)
                                alarm_time[21:16] <= i_wb_data[21:16];
                        // Here's the same thing for the minutes: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[15:8] != 8'hff)
                                alarm_time[15:8] <= i_wb_data[15:8];
                        // Here's the same thing for the seconds: only adjust
                        // the alarm minutes if the new bits are not all 1's. 
                        if (i_wb_data[7:0] != 8'hff)
                                alarm_time[7:0] <= i_wb_data[7:0];
                        al_enabled <= i_wb_data[24];
                        // Reset the alarm if a '1' is written to the tripped
                        // register, or if the alarm is disabled.
                        if ((i_wb_data[25])||(~i_wb_data[24]))
                                al_tripped <= 1'b0;
                end
 
                al_int <= 1'b0;
                if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)
                        &&(al_enabled))
                begin
                        al_tripped <= 1'b1;
                        al_int <= 1'b1;
                end
        end
 
        //
        // The ckspeed register is equal to 2^48 divded by the number of
        // clock ticks you expect per second.  Adjust high for a slower
        // clock, lower for a faster clock.  In this fashion, a single
        // real time clock RTL file can handle tracking the clock in any
        // device.  Further, because this is only the lower 32 bits of a 
        // 48 bit counter per seconds, the clock jitter is kept below
        // 1 part in 65 thousand.
        //
        initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz
        // In the case of verilator, comment the above and uncomment the line
        // below.  The clock constant below is "close" to simulation time,
        // meaning that my verilator simulation is running about 300x slower
        // than board time.
        // initial      ckspeed = 32'd786432000;
        always @(posedge i_clk)
                if ((sp_sel)&&(i_wb_we))
                        ckspeed <= i_wb_data;
 
        assign  o_interrupt = tm_int || al_int;
 
        // A once-per day strobe, on the last second of the day so that the
        // the next clock is the first clock of the day.  This is useful for
        // connecting this module to a year/month/date date/calendar module.
        assign  o_ppd = (ck_ppd)&&(ck_pps);
 
        always @(posedge i_clk)
                case(i_wb_addr[2:0])
                3'b000: o_data <= { 10'h0, ck_last_clock };
                3'b001: o_data <= { 6'h00, timer };
                3'b010: o_data <= stopwatch;
                3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
                3'b100: o_data <= ckspeed;
                default: o_data <= 32'h000;
                endcase
 
endmodule

Line No.	Rev	Author	Line
1	6	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: rtclight.v`
4			`//`
5			`// Project: A Wishbone Controlled Real--time Clock Core`
6			`//`
7			`// Purpose: Implement a real time clock, including alarm, count--down`
8			`// timer, stopwatch, variable time frequency, and more.`
9			`//`
10			`// This is a light-weight version of the RTC found in this directory.`
11			`// Unlike the full RTC, this version does not support time hacks, seven`
12			`// segment display outputs, or LED's. It is an RTC for an internal core`
13			`// only. (That's how I was using it on one of my projects anyway ...)`
14			`//`
15			`//`
16			`// Creator: Dan Gisselquist, Ph.D.`
17	8	dgisselq	`// Gisselquist Technology, LLC`
18	6	dgisselq	`//`
19			`///////////////////////////////////////////////////////////////////////////`
20			`//`
21			`// Copyright (C) 2015, Gisselquist Technology, LLC`
22			`//`
23			`// This program is free software (firmware): you can redistribute it and/or`
24			`// modify it under the terms of the GNU General Public License as published`
25			`// by the Free Software Foundation, either version 3 of the License, or (at`
26			`// your option) any later version.`
27			`//`
28			`// This program is distributed in the hope that it will be useful, but WITHOUT`
29			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
30			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
31			`// for more details.`
32			`//`
33			`// You should have received a copy of the GNU General Public License along`
34			`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
35			`// target there if the PDF file isn't present.) If not, see`
36			`// <http://www.gnu.org/licenses/> for a copy.`
37			`//`
38			`// License: GPL, v3, as defined and found on www.gnu.org,`
39			`// http://www.gnu.org/licenses/gpl.html`
40			`//`
41			`//`
42			`///////////////////////////////////////////////////////////////////////////`
43	7	dgisselq	`module rtclight(i_clk,`
44	6	dgisselq	`// Wishbone interface`
45			`i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,`
46			`// o_wb_ack, o_wb_stb, o_wb_data, // no reads here`
47			`// // Button inputs`
48			`// i_btn,`
49			`// Output registers`
50			`o_data, // multiplexed based upon i_wb_addr`
51			`// Output controls`
52			`o_interrupt,`
53			`// A once-per-day strobe on the last clock of the day`
54			`o_ppd);`
55	8	dgisselq	`parameter DEFAULT_SPEED = 32'd2814750; // 100 Mhz`
56	6	dgisselq	`input i_clk;`
57			`input i_wb_cyc, i_wb_stb, i_wb_we;`
58			`input [2:0] i_wb_addr;`
59			`input [31:0] i_wb_data;`
60			`// input i_btn;`
61			`output reg [31:0] o_data;`
62			`output wire o_interrupt, o_ppd;`
63
64	7	dgisselq	`reg [21:0] clock;`
65			`reg [31:0] stopwatch, ckspeed;`
66	6	dgisselq	`reg [25:0] timer;`
67
68			`wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;`
69			`assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));`
70			`assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));`
71			`assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));`
72			`assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));`
73			`assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));`
74
75	10	dgisselq	`reg ck_carry;`
76	6	dgisselq	`reg [39:0] ck_counter;`
77	10	dgisselq	`initial ck_carry = 1'b0;`
78			`initial ck_counter = 40'h00;`
79	6	dgisselq	`always @(posedge i_clk)`
80			`{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };`
81
82			`wire ck_pps;`
83			`reg ck_prepps, ck_ppm, ck_pph, ck_ppd;`
84			`reg [7:0] ck_sub;`
85	7	dgisselq	`initial clock = 22'h00000;`
86	6	dgisselq	`assign ck_pps = (ck_carry)&&(ck_prepps);`
87			`always @(posedge i_clk)`
88			`begin`
89			`if (ck_carry)`
90			`ck_sub <= ck_sub + 8'h1;`
91			`ck_prepps <= (ck_sub == 8'hff);`
92
93			`if (ck_pps)`
94			`begin // advance the seconds`
95			`if (clock[3:0] >= 4'h9)`
96			`clock[3:0] <= 4'h0;`
97			`else`
98			`clock[3:0] <= clock[3:0] + 4'h1;`
99			`if (clock[7:0] >= 8'h59)`
100			`clock[7:4] <= 4'h0;`
101			`else if (clock[3:0] >= 4'h9)`
102			`clock[7:4] <= clock[7:4] + 4'h1;`
103			`end`
104			`ck_ppm <= (clock[7:0] == 8'h59);`
105
106			`if ((ck_pps)&&(ck_ppm))`
107			`begin // advance the minutes`
108			`if (clock[11:8] >= 4'h9)`
109			`clock[11:8] <= 4'h0;`
110			`else`
111			`clock[11:8] <= clock[11:8] + 4'h1;`
112			`if (clock[15:8] >= 8'h59)`
113			`clock[15:12] <= 4'h0;`
114			`else if (clock[11:8] >= 4'h9)`
115			`clock[15:12] <= clock[15:12] + 4'h1;`
116			`end`
117			`ck_pph <= (clock[15:0] == 16'h5959);`
118
119			`if ((ck_pps)&&(ck_pph))`
120			`begin // advance the hours`
121			`if (clock[21:16] >= 6'h23)`
122			`begin`
123			`clock[19:16] <= 4'h0;`
124			`clock[21:20] <= 2'h0;`
125			`end else if (clock[19:16] >= 4'h9)`
126			`begin`
127			`clock[19:16] <= 4'h0;`
128			`clock[21:20] <= clock[21:20] + 2'h1;`
129			`end else begin`
130			`clock[19:16] <= clock[19:16] + 4'h1;`
131			`end`
132			`end`
133			`ck_ppd <= (clock[21:0] == 22'h235959);`
134
135
136			`if ((ck_sel)&&(i_wb_we))`
137			`begin`
138			`if (8'hff != i_wb_data[7:0])`
139			`begin`
140			`clock[7:0] <= i_wb_data[7:0];`
141			`ck_ppm <= (i_wb_data[7:0] == 8'h59);`
142			`end`
143			`if (8'hff != i_wb_data[15:8])`
144			`begin`
145			`clock[15:8] <= i_wb_data[15:8];`
146			`ck_pph <= (i_wb_data[15:8] == 8'h59);`
147			`end`
148			`if (6'h3f != i_wb_data[21:16])`
149			`clock[21:16] <= i_wb_data[21:16];`
150			`if (8'h00 == i_wb_data[7:0])`
151			`ck_sub <= 8'h00;`
152			`end`
153			`end`
154
155			`// Clock updates take several clocks, so let's make sure we`
156			`// are only looking at a valid clock value before testing it.`
157			`reg [21:0] ck_last_clock;`
158			`always @(posedge i_clk)`
159			`ck_last_clock <= clock[21:0];`
160
161
162			`reg tm_pps, tm_ppm, tm_int;`
163			`wire tm_stopped, tm_running, tm_alarm;`
164			`assign tm_stopped = ~timer[24];`
165			`assign tm_running = timer[24];`
166			`assign tm_alarm = timer[25];`
167			`reg [23:0] tm_start;`
168			`reg [7:0] tm_sub;`
169			`initial tm_start = 24'h00;`
170			`initial timer = 26'h00;`
171			`initial tm_int = 1'b0;`
172			`initial tm_pps = 1'b0;`
173			`always @(posedge i_clk)`
174			`begin`
175			`if (ck_carry)`
176			`begin`
177			`tm_sub <= tm_sub + 8'h1;`
178			`tm_pps <= (tm_sub == 8'hff);`
179			`end else`
180			`tm_pps <= 1'b0;`
181
182			`if ((~tm_alarm)&&(tm_running)&&(tm_pps))`
183			`begin // If we are running ...`
184			`timer[25] <= 1'b0;`
185			`if (timer[23:0] == 24'h00)`
186			`timer[25] <= 1'b1;`
187			`else if (timer[3:0] != 4'h0)`
188			`timer[3:0] <= timer[3:0]-4'h1;`
189			`else begin // last digit is a zero`
190			`timer[3:0] <= 4'h9;`
191			`if (timer[7:4] != 4'h0)`
192			`timer[7:4] <= timer[7:4]-4'h1;`
193			`else begin // last two digits are zero`
194			`timer[7:4] <= 4'h5;`
195			`if (timer[11:8] != 4'h0)`
196			`timer[11:8] <= timer[11:8]-4'h1;`
197			`else begin // last three digits are zero`
198			`timer[11:8] <= 4'h9;`
199			`if (timer[15:12] != 4'h0)`
200			`timer[15:12] <= timer[15:12]-4'h1;`
201			`else begin`
202			`timer[15:12] <= 4'h5;`
203			`if (timer[19:16] != 4'h0)`
204			`timer[19:16] <= timer[19:16]-4'h1;`
205			`else begin`
206			`//`
207			`timer[19:16] <= 4'h9;`
208			`timer[23:20] <= timer[23:20]-4'h1;`
209			`end`
210			`end`
211			`end`
212			`end`
213			`end`
214			`end`
215
216			`if((~tm_alarm)&&(tm_running))`
217			`begin`
218			`timer[25] <= (timer[23:0] == 24'h00);`
219			`tm_int <= (timer[23:0] == 24'h00);`
220			`end else tm_int <= 1'b0;`
221			`if (tm_alarm)`
222			`timer[24] <= 1'b0;`
223
224			`if ((tm_sel)&&(i_wb_we)&&(tm_running)) // Writes while running`
225			`// Only allowed to stop the timer, nothing more`
226			`timer[24] <= i_wb_data[24];`
227			`else if ((tm_sel)&&(i_wb_we)&&(tm_stopped)) // Writes while off`
228			`begin`
229			`timer[24] <= i_wb_data[24];`
230			`if ((timer[24])\|\|(i_wb_data[24]))`
231			`timer[25] <= 1'b0;`
232			`if (i_wb_data[23:0] != 24'h0000)`
233			`begin`
234			`timer[23:0] <= i_wb_data[23:0];`
235			`tm_start <= i_wb_data[23:0];`
236			`tm_sub <= 8'h00;`
237			`end else if (timer[23:0] == 24'h00)`
238			`begin // Resetting timer to last valid timer start val`
239			`timer[23:0] <= tm_start;`
240			`tm_sub <= 8'h00;`
241			`end`
242			`// Any write clears the alarm`
243			`timer[25] <= 1'b0;`
244			`end`
245			`end`
246
247			`//`
248			`// Stopwatch functionality`
249			`//`
250			`// Setting bit '0' starts the stop watch, clearing it stops it.`
251			`// Writing to the register with bit '1' high will clear the stopwatch,`
252			`// and return it to zero provided that the stopwatch is stopped either`
253			`// before or after the write. Hence, writing a '2' to the device`
254			`// will always stop and clear it, whereas writing a '3' to the device`
255			`// will only clear it if it was already stopped.`
256			`reg sw_pps, sw_ppm, sw_pph;`
257			`reg [7:0] sw_sub;`
258			`wire sw_running;`
259			`assign sw_running = stopwatch[0];`
260			`initial stopwatch = 32'h00000;`
261			`always @(posedge i_clk)`
262			`begin`
263			`sw_pps <= 1'b0;`
264			`if (sw_running)`
265			`begin`
266			`if (ck_carry)`
267			`begin`
268			`sw_sub <= sw_sub + 8'h1;`
269			`sw_pps <= (sw_sub == 8'hff);`
270			`end`
271			`end`
272
273			`stopwatch[7:1] <= sw_sub[7:1];`
274
275			`if (sw_pps)`
276			`begin // Second hand`
277			`if (stopwatch[11:8] >= 4'h9)`
278			`stopwatch[11:8] <= 4'h0;`
279			`else`
280			`stopwatch[11:8] <= stopwatch[11:8] + 4'h1;`
281
282			`if (stopwatch[15:8] >= 8'h59)`
283			`stopwatch[15:12] <= 4'h0;`
284			`else if (stopwatch[11:8] >= 4'h9)`
285			`stopwatch[15:12] <= stopwatch[15:12] + 4'h1;`
286			`sw_ppm <= (stopwatch[15:8] == 8'h59);`
287			`end else sw_ppm <= 1'b0;`
288
289			`if (sw_ppm)`
290			`begin // Minutes`
291			`if (stopwatch[19:16] >= 4'h9)`
292			`stopwatch[19:16] <= 4'h0;`
293			`else`
294			`stopwatch[19:16] <= stopwatch[19:16]+4'h1;`
295
296			`if (stopwatch[23:16] >= 8'h59)`
297			`stopwatch[23:20] <= 4'h0;`
298			`else if (stopwatch[19:16] >= 4'h9)`
299			`stopwatch[23:20] <= stopwatch[23:20]+4'h1;`
300			`sw_pph <= (stopwatch[23:16] == 8'h59);`
301			`end else sw_pph <= 1'b0;`
302
303			`if (sw_pph)`
304			`begin // And hours`
305			`if (stopwatch[27:24] >= 4'h9)`
306			`stopwatch[27:24] <= 4'h0;`
307			`else`
308			`stopwatch[27:24] <= stopwatch[27:24]+4'h1;`
309
310			`if((stopwatch[27:24] >= 4'h9)&&(stopwatch[31:28] < 4'hf))`
311			`stopwatch[31:28] <= stopwatch[27:24]+4'h1;`
312			`end`
313
314			`if ((sw_sel)&&(i_wb_we))`
315			`begin`
316			`stopwatch[0] <= i_wb_data[0];`
317			`if((i_wb_data[1])&&((~stopwatch[0])\|\|(~i_wb_data[0])))`
318			`begin`
319			`stopwatch[31:1] <= 31'h00;`
320			`sw_sub <= 8'h00;`
321			`sw_pps <= 1'b0;`
322			`sw_ppm <= 1'b0;`
323			`sw_pph <= 1'b0;`
324			`end`
325			`end`
326			`end`
327
328			`//`
329			`// The alarm code`
330			`//`
331			`// Set the alarm register to the time you wish the board to "alarm".`
332			`// The "alarm" will take place once per day at that time. At that`
333			`// time, the RTC code will generate a clock interrupt, and the CPU/host`
334			`// can come and see that the alarm tripped.`
335			`//`
336			`//`
337			`reg [21:0] alarm_time;`
338			`reg al_int, // The alarm interrupt line`
339			`al_enabled, // Whether the alarm is enabled`
340			`al_tripped; // Whether the alarm has tripped`
341			`initial al_enabled= 1'b0;`
342			`initial al_tripped= 1'b0;`
343			`always @(posedge i_clk)`
344			`begin`
345			`if ((al_sel)&&(i_wb_we))`
346			`begin`
347			`// Only adjust the alarm hours if the requested hours`
348			`// are valid. This allows writes to the register,`
349			`// without a prior read, to leave these configuration`
350			`// bits alone.`
351			`if (i_wb_data[21:16] != 6'h3f)`
352			`alarm_time[21:16] <= i_wb_data[21:16];`
353			`// Here's the same thing for the minutes: only adjust`
354			`// the alarm minutes if the new bits are not all 1's.`
355			`if (i_wb_data[15:8] != 8'hff)`
356			`alarm_time[15:8] <= i_wb_data[15:8];`
357			`// Here's the same thing for the seconds: only adjust`
358			`// the alarm minutes if the new bits are not all 1's.`
359			`if (i_wb_data[7:0] != 8'hff)`
360			`alarm_time[7:0] <= i_wb_data[7:0];`
361			`al_enabled <= i_wb_data[24];`
362			`// Reset the alarm if a '1' is written to the tripped`
363			`// register, or if the alarm is disabled.`
364			`if ((i_wb_data[25])\|\|(~i_wb_data[24]))`
365			`al_tripped <= 1'b0;`
366			`end`
367
368			`al_int <= 1'b0;`
369			`if ((ck_last_clock != alarm_time)&&(clock[21:0] == alarm_time)`
370			`&&(al_enabled))`
371			`begin`
372			`al_tripped <= 1'b1;`
373			`al_int <= 1'b1;`
374			`end`
375			`end`
376
377			`//`
378			`// The ckspeed register is equal to 2^48 divded by the number of`
379			`// clock ticks you expect per second. Adjust high for a slower`
380			`// clock, lower for a faster clock. In this fashion, a single`
381			`// real time clock RTL file can handle tracking the clock in any`
382			`// device. Further, because this is only the lower 32 bits of a`
383			`// 48 bit counter per seconds, the clock jitter is kept below`
384			`// 1 part in 65 thousand.`
385			`//`
386	7	dgisselq	`initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz`
387	6	dgisselq	`// In the case of verilator, comment the above and uncomment the line`
388			`// below. The clock constant below is "close" to simulation time,`
389			`// meaning that my verilator simulation is running about 300x slower`
390			`// than board time.`
391			`// initial ckspeed = 32'd786432000;`
392			`always @(posedge i_clk)`
393			`if ((sp_sel)&&(i_wb_we))`
394			`ckspeed <= i_wb_data;`
395
396			`assign o_interrupt = tm_int \|\| al_int;`
397
398			`// A once-per day strobe, on the last second of the day so that the`
399			`// the next clock is the first clock of the day. This is useful for`
400			`// connecting this module to a year/month/date date/calendar module.`
401			`assign o_ppd = (ck_ppd)&&(ck_pps);`
402
403			`always @(posedge i_clk)`
404			`case(i_wb_addr[2:0])`
405	7	dgisselq	`3'b000: o_data <= { 10'h0, ck_last_clock };`
406	6	dgisselq	`3'b001: o_data <= { 6'h00, timer };`
407			`3'b010: o_data <= stopwatch;`
408			`3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };`
409			`3'b100: o_data <= ckspeed;`
410			`default: o_data <= 32'h000;`
411			`endcase`
412
413			`endmodule`

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