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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Byte mode decode/execute state
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// ============================================================================
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//
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BYTE_DECODE:
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begin
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first_ifetch <= `TRUE;
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state <= IFETCH;
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case(ir[7:0])
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`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
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`NAT: begin em <= 1'b0; pc <= pc + 32'd1; end
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`NOP: pc <= pc + 32'd1;
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`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
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`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
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`CLV: begin vf <= 1'b0; pc <= pc + 32'd1; end
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`CLI: begin im <= 1'b0; pc <= pc + 32'd1; end
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`SEI: begin im <= 1'b1; pc <= pc + 32'd1; end
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`CLD: begin df <= 1'b0; pc <= pc + 32'd1; end
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`SED: begin df <= 1'b1; pc <= pc + 32'd1; end
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`WAI: begin wai <= 1'b1; pc <= pc + 32'd1; end
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`DEX: begin res8 <= x[7:0] - 8'd1; pc <= pc + 32'd1; end
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`INX: begin res8 <= x[7:0] + 8'd1; pc <= pc + 32'd1; end
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`DEY: begin res8 <= y[7:0] - 8'd1; pc <= pc + 32'd1; end
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`INY: begin res8 <= y[7:0] + 8'd1; pc <= pc + 32'd1; end
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`DEA: begin res8 <= acc[7:0] - 8'd1; pc <= pc + 32'd1; end
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`INA: begin res8 <= acc[7:0] + 8'd1; pc <= pc + 32'd1; end
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`TSX,`TSA: begin res8 <= sp[7:0]; pc <= pc + 32'd1; end
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`TXS,`TXA,`TXY: begin res8 <= x[7:0]; pc <= pc + 32'd1; end
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`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; pc <= pc + 32'd1; end
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`TYA,`TYX: begin res8 <= y[7:0]; pc <= pc + 32'd1; end
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`ASL_ACC: begin res8 <= {acc8,1'b0}; pc <= pc + 32'd1; end
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`ROL_ACC: begin res8 <= {acc8,cf}; pc <= pc + 32'd1; end
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`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; pc <= pc + 32'd1; end
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`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; pc <= pc + 32'd1; end
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// Handle # mode
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`LDA_IMM,`LDX_IMM,`LDY_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= ir[15:8];
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end
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`ADC_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= acc8 + ir[15:8] + {7'b0,cf};
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b8 <= ir[15:8]; // for overflow calc
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end
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`SBC_IMM:
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begin
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pc <= pc + 32'd2;
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// res8 <= acc8 - ir[15:8] - ~cf;
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res8 <= acc8 - ir[15:8] - {7'b0,~cf};
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$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
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b8 <= ir[15:8]; // for overflow calc
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end
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`AND_IMM,`BIT_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= acc8 & ir[15:8];
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b8 <= ir[15:8]; // for bit flags
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end
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`ORA_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= acc8 | ir[15:8];
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end
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`EOR_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= acc8 ^ ir[15:8];
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end
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`CMP_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= acc8 - ir[15:8];
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end
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`CPX_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= x8 - ir[15:8];
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end
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`CPY_IMM:
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begin
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pc <= pc + 32'd2;
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res8 <= y8 - ir[15:8];
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end
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// Handle zp mode
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`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,`LDA_ZP,
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`LDX_ZP,`LDY_ZP,`BIT_ZP,`CPX_ZP,`CPY_ZP,
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`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
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begin
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pc <= pc + 32'd2;
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radr <= zp_address[31:2];
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radr2LSB <= zp_address[1:0];
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state <= LOAD1;
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end
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`STA_ZP:
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begin
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pc <= pc + 32'd2;
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wdat <= {4{acc8}};
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state <= STORE1;
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end
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`STX_ZP:
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begin
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pc <= pc + 32'd2;
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wdat <= {4{x8}};
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state <= STORE1;
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end
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`STY_ZP:
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begin
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pc <= pc + 32'd2;
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wdat <= {4{y8}};
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state <= STORE1;
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end
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`STZ_ZP:
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begin
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pc <= pc + 32'd2;
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wdat <= {4{8'h00}};
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state <= STORE1;
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end
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// Handle zp,x mode
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`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,`LDA_ZPX,
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`LDY_ZPX,`BIT_ZPX,
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`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
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begin
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pc <= pc + 32'd2;
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radr <= zpx_address[31:2];
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radr2LSB <= zpx_address[1:0];
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state <= LOAD1;
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end
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`STA_ZPX:
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begin
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pc <= pc + 32'd2;
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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wdat <= {4{acc8}};
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state <= STORE1;
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end
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`STY_ZPX:
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begin
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pc <= pc + 32'd2;
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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wdat <= {4{y8}};
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state <= STORE1;
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end
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`STZ_ZPX:
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begin
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pc <= pc + 32'd2;
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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wdat <= {4{8'h00}};
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state <= STORE1;
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end
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// Handle zp,y
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`LDX_ZPY:
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begin
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pc <= pc + 32'd2;
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radr <= zpy_address[31:2];
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radr2LSB <= zpy_address[1:0];
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state <= LOAD1;
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end
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`STX_ZPY:
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begin
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pc <= pc + 32'd2;
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wadr <= zpy_address[31:2];
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wadr2LSB <= zpy_address[1:0];
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wdat <= {4{x8}};
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state <= STORE1;
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end
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// Handle (zp,x)
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`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
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begin
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pc <= pc + 32'd2;
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radr <= zpx_address[31:2];
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radr2LSB <= zpx_address[1:0];
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state <= BYTE_IX1;
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end
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// Handle (zp),y
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`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
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begin
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pc <= pc + 32'd2;
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radr <= zp_address[31:2];
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radr2LSB <= zp_address[1:0];
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state <= BYTE_IY1;
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end
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// Handle abs
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`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,`LDA_ABS,
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`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
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`LDX_ABS,`LDY_ABS,
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`CPX_ABS,`CPY_ABS,
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`BIT_ABS:
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begin
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pc <= pc + 32'd3;
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radr <= abs_address[31:2];
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radr2LSB <= abs_address[1:0];
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state <= LOAD1;
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end
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`STA_ABS:
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begin
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pc <= pc + 32'd3;
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wadr <= abs_address[31:2];
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wadr2LSB <= abs_address[1:0];
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wdat <= {4{acc8}};
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state <= STORE1;
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end
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`STX_ABS:
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begin
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pc <= pc + 32'd3;
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wadr <= abs_address[31:2];
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wadr2LSB <= abs_address[1:0];
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| 238 |
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wdat <= {4{x8}};
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state <= STORE1;
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| 240 |
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end
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| 241 |
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`STY_ABS:
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| 242 |
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begin
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| 243 |
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pc <= pc + 32'd3;
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| 244 |
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wadr <= abs_address[31:2];
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| 245 |
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wadr2LSB <= abs_address[1:0];
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| 246 |
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wdat <= {4{y8}};
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| 247 |
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state <= STORE1;
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| 248 |
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end
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| 249 |
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`STZ_ABS:
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| 250 |
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begin
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| 251 |
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pc <= pc + 32'd3;
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| 252 |
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wadr <= abs_address[31:2];
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| 253 |
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wadr2LSB <= abs_address[1:0];
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| 254 |
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wdat <= {4{8'h00}};
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| 255 |
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state <= STORE1;
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| 256 |
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end
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| 257 |
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// Handle abs,x
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| 258 |
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`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
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| 259 |
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`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
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| 260 |
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`LDY_ABSX:
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| 261 |
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begin
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| 262 |
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pc <= pc + 32'd3;
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| 263 |
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radr <= absx_address[31:2];
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| 264 |
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radr2LSB <= absx_address[1:0];
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| 265 |
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state <= LOAD1;
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| 266 |
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end
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| 267 |
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`STA_ABSX:
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| 268 |
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begin
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| 269 |
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pc <= pc + 32'd3;
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| 270 |
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wadr <= absx_address[31:2];
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| 271 |
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wadr2LSB <= absx_address[1:0];
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| 272 |
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wdat <= {4{acc8}};
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| 273 |
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state <= STORE1;
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| 274 |
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end
|
| 275 |
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`STZ_ABSX:
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| 276 |
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begin
|
| 277 |
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pc <= pc + 32'd3;
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| 278 |
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wadr <= absx_address[31:2];
|
| 279 |
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wadr2LSB <= absx_address[1:0];
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| 280 |
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wdat <= {4{8'h00}};
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| 281 |
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state <= STORE1;
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| 282 |
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end
|
| 283 |
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|
// Handle abs,y
|
| 284 |
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`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
|
| 285 |
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`LDX_ABSY:
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| 286 |
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begin
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| 287 |
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pc <= pc + 32'd3;
|
| 288 |
|
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radr <= absy_address[31:2];
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| 289 |
|
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radr2LSB <= absy_address[1:0];
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| 290 |
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state <= LOAD1;
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| 291 |
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end
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| 292 |
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|
`STA_ABSY:
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| 293 |
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begin
|
| 294 |
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pc <= pc + 32'd3;
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| 295 |
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wadr <= absy_address[31:2];
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| 296 |
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wadr2LSB <= absy_address[1:0];
|
| 297 |
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wdat <= {4{acc8}};
|
| 298 |
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state <= STORE1;
|
| 299 |
|
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end
|
| 300 |
|
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// Handle (zp)
|
| 301 |
|
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`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
| 302 |
|
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begin
|
| 303 |
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pc <= pc + 32'd2;
|
| 304 |
|
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radr <= zp_address[31:2];
|
| 305 |
|
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radr2LSB <= zp_address[1:0];
|
| 306 |
|
|
state <= BYTE_IX1;
|
| 307 |
|
|
end
|
| 308 |
|
|
`BRK:
|
| 309 |
|
|
begin
|
| 310 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 311 |
|
|
radr2LSB <= sp[1:0];
|
| 312 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 313 |
|
|
wadr2LSB <= sp[1:0];
|
| 314 |
|
|
wdat <= {4{pcp1[31:24]}};
|
| 315 |
|
|
cyc_o <= 1'b1;
|
| 316 |
|
|
stb_o <= 1'b1;
|
| 317 |
|
|
we_o <= 1'b1;
|
| 318 |
|
|
case(sp[1:0])
|
| 319 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 320 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 321 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 322 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 323 |
|
|
endcase
|
| 324 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 325 |
|
|
dat_o <= {4{pcp1[31:24]}};
|
| 326 |
|
|
sp <= sp_dec;
|
| 327 |
|
|
vect <= `BYTE_IRQ_VECT;
|
| 328 |
|
|
state <= BYTE_IRQ1;
|
| 329 |
|
|
bf <= 1'b1;
|
| 330 |
|
|
end
|
| 331 |
|
|
`JMP:
|
| 332 |
|
|
begin
|
| 333 |
|
|
pc[15:0] <= abs_address[15:0];
|
| 334 |
|
|
end
|
| 335 |
|
|
`JML:
|
| 336 |
|
|
begin
|
| 337 |
|
|
pc <= ir[39:8];
|
| 338 |
|
|
end
|
| 339 |
|
|
`JMP_IND:
|
| 340 |
|
|
begin
|
| 341 |
|
|
radr <= abs_address[31:2];
|
| 342 |
|
|
radr2LSB <= abs_address[1:0];
|
| 343 |
|
|
state <= BYTE_JMP_IND1;
|
| 344 |
|
|
end
|
| 345 |
|
|
`JMP_INDX:
|
| 346 |
|
|
begin
|
| 347 |
|
|
radr <= absx_address[31:2];
|
| 348 |
|
|
radr2LSB <= absx_address[1:0];
|
| 349 |
|
|
state <= BYTE_JMP_IND1;
|
| 350 |
|
|
end
|
| 351 |
|
|
`JSR:
|
| 352 |
|
|
begin
|
| 353 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 354 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 355 |
|
|
radr2LSB <= sp[1:0];
|
| 356 |
|
|
wadr2LSB <= sp[1:0];
|
| 357 |
|
|
wdat <= {4{pcp2[15:8]}};
|
| 358 |
|
|
cyc_o <= 1'b1;
|
| 359 |
|
|
stb_o <= 1'b1;
|
| 360 |
|
|
we_o <= 1'b1;
|
| 361 |
|
|
case(sp[1:0])
|
| 362 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 363 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 364 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 365 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 366 |
|
|
endcase
|
| 367 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 368 |
|
|
dat_o <= {4{pcp2[15:8]}};
|
| 369 |
|
|
sp <= sp_dec;
|
| 370 |
|
|
state <= BYTE_JSR1;
|
| 371 |
|
|
end
|
| 372 |
|
|
`JSL:
|
| 373 |
|
|
begin
|
| 374 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 375 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 376 |
|
|
radr2LSB <= sp[1:0];
|
| 377 |
|
|
wadr2LSB <= sp[1:0];
|
| 378 |
|
|
wdat <= {4{pcp4[31:24]}};
|
| 379 |
|
|
cyc_o <= 1'b1;
|
| 380 |
|
|
stb_o <= 1'b1;
|
| 381 |
|
|
we_o <= 1'b1;
|
| 382 |
|
|
case(sp[1:0])
|
| 383 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 384 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 385 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 386 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 387 |
|
|
endcase
|
| 388 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 389 |
|
|
dat_o <= {4{pcp4[31:24]}};
|
| 390 |
|
|
sp <= sp_dec;
|
| 391 |
|
|
state <= BYTE_JSL1;
|
| 392 |
|
|
end
|
| 393 |
|
|
`JSR_INDX:
|
| 394 |
|
|
begin
|
| 395 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 396 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 397 |
|
|
radr2LSB <= sp[1:0];
|
| 398 |
|
|
wadr2LSB <= sp[1:0];
|
| 399 |
|
|
wdat <= {4{pcp2[15:8]}};
|
| 400 |
|
|
cyc_o <= 1'b1;
|
| 401 |
|
|
stb_o <= 1'b1;
|
| 402 |
|
|
we_o <= 1'b1;
|
| 403 |
|
|
case(sp_dec[1:0])
|
| 404 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 405 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 406 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 407 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 408 |
|
|
endcase
|
| 409 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 410 |
|
|
dat_o <= {4{pcp2[15:8]}};
|
| 411 |
|
|
sp <= sp_dec;
|
| 412 |
|
|
state <= BYTE_JSR_INDX1;
|
| 413 |
|
|
end
|
| 414 |
|
|
`RTS,`RTL:
|
| 415 |
|
|
begin
|
| 416 |
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
| 417 |
|
|
radr2LSB <= sp_inc[1:0];
|
| 418 |
|
|
sp <= sp_inc;
|
| 419 |
|
|
state <= BYTE_RTS1;
|
| 420 |
|
|
end
|
| 421 |
|
|
`RTI: begin
|
| 422 |
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
| 423 |
|
|
radr2LSB <= sp_inc[1:0];
|
| 424 |
|
|
sp <= sp_inc;
|
| 425 |
|
|
state <= BYTE_RTI9;
|
| 426 |
|
|
end
|
| 427 |
|
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
| 428 |
|
|
begin
|
| 429 |
|
|
// if (ir[15:8]==8'hFE) begin
|
| 430 |
|
|
// radr <= {24'h1,sp[7:2]};
|
| 431 |
|
|
// radr2LSB <= sp[1:0];
|
| 432 |
|
|
// wadr <= {24'h1,sp[7:2]};
|
| 433 |
|
|
// wadr2LSB <= sp[1:0];
|
| 434 |
|
|
// case(sp[1:0])
|
| 435 |
|
|
// 2'd0: sel_o <= 4'b0001;
|
| 436 |
|
|
// 2'd1: sel_o <= 4'b0010;
|
| 437 |
|
|
// 2'd2: sel_o <= 4'b0100;
|
| 438 |
|
|
// 2'd3: sel_o <= 4'b1000;
|
| 439 |
|
|
// endcase
|
| 440 |
|
|
// wdat <= {4{pcp2[31:24]}};
|
| 441 |
|
|
// cyc_o <= 1'b1;
|
| 442 |
|
|
// stb_o <= 1'b1;
|
| 443 |
|
|
// we_o <= 1'b1;
|
| 444 |
|
|
// adr_o <= {24'h1,sp[7:2],2'b00};
|
| 445 |
|
|
// dat_o <= {4{pcp2[31:24]}};
|
| 446 |
|
|
// vect <= `SLP_VECT;
|
| 447 |
|
|
// state <= BYTE_IRQ1;
|
| 448 |
|
|
// end
|
| 449 |
|
|
// else
|
| 450 |
|
|
if (ir[15:8]==8'hFF) begin
|
| 451 |
|
|
if (takb)
|
| 452 |
|
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
| 453 |
|
|
else
|
| 454 |
|
|
pc <= pc + 32'd4;
|
| 455 |
|
|
end
|
| 456 |
|
|
else begin
|
| 457 |
|
|
if (takb)
|
| 458 |
|
|
pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
|
| 459 |
|
|
else
|
| 460 |
|
|
pc <= pc + 32'd2;
|
| 461 |
|
|
end
|
| 462 |
|
|
end
|
| 463 |
|
|
`PHP:
|
| 464 |
|
|
begin
|
| 465 |
|
|
cyc_o <= 1'b1;
|
| 466 |
|
|
stb_o <= 1'b1;
|
| 467 |
|
|
we_o <= 1'b1;
|
| 468 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 469 |
|
|
radr2LSB <= sp[1:0];
|
| 470 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 471 |
|
|
wadr2LSB <= sp[1:0];
|
| 472 |
|
|
case(sp[1:0])
|
| 473 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 474 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 475 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 476 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 477 |
|
|
endcase
|
| 478 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 479 |
|
|
dat_o <= {4{sr8}};
|
| 480 |
|
|
wdat <= {4{sr8}};
|
| 481 |
|
|
sp <= sp_dec;
|
| 482 |
|
|
state <= PHP1;
|
| 483 |
|
|
end
|
| 484 |
|
|
`PHA:
|
| 485 |
|
|
begin
|
| 486 |
|
|
cyc_o <= 1'b1;
|
| 487 |
|
|
stb_o <= 1'b1;
|
| 488 |
|
|
we_o <= 1'b1;
|
| 489 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 490 |
|
|
radr2LSB <= sp[1:0];
|
| 491 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 492 |
|
|
wadr2LSB <= sp[1:0];
|
| 493 |
|
|
case(sp[1:0])
|
| 494 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 495 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 496 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 497 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 498 |
|
|
endcase
|
| 499 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 500 |
|
|
dat_o <= {4{acc8}};
|
| 501 |
|
|
wdat <= {4{acc8}};
|
| 502 |
|
|
sp <= sp_dec;
|
| 503 |
|
|
state <= PHP1;
|
| 504 |
|
|
end
|
| 505 |
|
|
`PHX:
|
| 506 |
|
|
begin
|
| 507 |
|
|
cyc_o <= 1'b1;
|
| 508 |
|
|
stb_o <= 1'b1;
|
| 509 |
|
|
we_o <= 1'b1;
|
| 510 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 511 |
|
|
radr2LSB <= sp[1:0];
|
| 512 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 513 |
|
|
wadr2LSB <= sp[1:0];
|
| 514 |
|
|
case(sp[1:0])
|
| 515 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 516 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 517 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 518 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 519 |
|
|
endcase
|
| 520 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 521 |
|
|
dat_o <= {4{x8}};
|
| 522 |
|
|
wdat <= {4{x8}};
|
| 523 |
|
|
sp <= sp_dec;
|
| 524 |
|
|
state <= PHP1;
|
| 525 |
|
|
end
|
| 526 |
|
|
`PHY:
|
| 527 |
|
|
begin
|
| 528 |
|
|
cyc_o <= 1'b1;
|
| 529 |
|
|
stb_o <= 1'b1;
|
| 530 |
|
|
we_o <= 1'b1;
|
| 531 |
|
|
radr <= {spage[31:8],sp[7:2]};
|
| 532 |
|
|
radr2LSB <= sp[1:0];
|
| 533 |
|
|
wadr <= {spage[31:8],sp[7:2]};
|
| 534 |
|
|
wadr2LSB <= sp[1:0];
|
| 535 |
|
|
case(sp[1:0])
|
| 536 |
|
|
2'd0: sel_o <= 4'b0001;
|
| 537 |
|
|
2'd1: sel_o <= 4'b0010;
|
| 538 |
|
|
2'd2: sel_o <= 4'b0100;
|
| 539 |
|
|
2'd3: sel_o <= 4'b1000;
|
| 540 |
|
|
endcase
|
| 541 |
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
| 542 |
|
|
dat_o <= {4{y8}};
|
| 543 |
|
|
wdat <= {4{y8}};
|
| 544 |
|
|
sp <= sp_dec;
|
| 545 |
|
|
state <= PHP1;
|
| 546 |
|
|
end
|
| 547 |
|
|
`PLP:
|
| 548 |
|
|
begin
|
| 549 |
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
| 550 |
|
|
radr2LSB <= sp_inc[1:0];
|
| 551 |
|
|
sp <= sp_inc;
|
| 552 |
|
|
state <= BYTE_PLP1;
|
| 553 |
|
|
pc <= pc + 32'd1;
|
| 554 |
|
|
end
|
| 555 |
|
|
`PLA,`PLX,`PLY:
|
| 556 |
|
|
begin
|
| 557 |
|
|
radr <= {spage[31:8],sp_inc[7:2]};
|
| 558 |
|
|
radr2LSB <= sp_inc[1:0];
|
| 559 |
|
|
sp <= sp_inc;
|
| 560 |
|
|
state <= PLA1;
|
| 561 |
|
|
pc <= pc + 32'd1;
|
| 562 |
|
|
end
|
| 563 |
|
|
default: // unimplemented opcode
|
| 564 |
|
|
pc <= pc + 32'd1;
|
| 565 |
|
|
endcase
|
| 566 |
|
|
end
|
| 567 |
|
|
|
