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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_decode.v] - Blame information for rev 25

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// Byte mode decode/execute state
// ============================================================================
//
BYTE_DECODE:
        begin
                first_ifetch <= `TRUE;
                state <= IFETCH;
                case(ir[7:0])
                `STP:   begin clk_en <= 1'b0; pc <= pc + 32'd1; end
                `NAT:   begin em <= 1'b0; pc <= pc + 32'd1; end
                `NOP:   pc <= pc + 32'd1;
                `CLC:   begin cf <= 1'b0; pc <= pc + 32'd1; end
                `SEC:   begin cf <= 1'b1; pc <= pc + 32'd1; end
                `CLV:   begin vf <= 1'b0; pc <= pc + 32'd1; end
                `CLI:   begin im <= 1'b0; pc <= pc + 32'd1; end
                `SEI:   begin im <= 1'b1; pc <= pc + 32'd1; end
                `CLD:   begin df <= 1'b0; pc <= pc + 32'd1; end
                `SED:   begin df <= 1'b1; pc <= pc + 32'd1; end
                `WAI:   begin wai <= 1'b1; pc <= pc + 32'd1; end
                `DEX:   begin res8 <= x[7:0] - 8'd1; pc <= pc + 32'd1; end
                `INX:   begin res8 <= x[7:0] + 8'd1; pc <= pc + 32'd1; end
                `DEY:   begin res8 <= y[7:0] - 8'd1; pc <= pc + 32'd1; end
                `INY:   begin res8 <= y[7:0] + 8'd1; pc <= pc + 32'd1; end
                `DEA:   begin res8 <= acc[7:0] - 8'd1; pc <= pc + 32'd1; end
                `INA:   begin res8 <= acc[7:0] + 8'd1; pc <= pc + 32'd1; end
                `TSX,`TSA:      begin res8 <= sp[7:0]; pc <= pc + 32'd1; end
                `TXS,`TXA,`TXY: begin res8 <= x[7:0]; pc <= pc + 32'd1; end
                `TAX,`TAY,`TAS: begin res8 <= acc[7:0]; pc <= pc + 32'd1; end
                `TYA,`TYX:      begin res8 <= y[7:0]; pc <= pc + 32'd1; end
                `ASL_ACC:       begin res8 <= {acc8,1'b0}; pc <= pc + 32'd1; end
                `ROL_ACC:       begin res8 <= {acc8,cf}; pc <= pc + 32'd1; end
                `LSR_ACC:       begin res8 <= {acc8[0],1'b0,acc8[7:1]}; pc <= pc + 32'd1; end
                `ROR_ACC:       begin res8 <= {acc8[0],cf,acc8[7:1]}; pc <= pc + 32'd1; end
                // Handle # mode
                `LDA_IMM,`LDX_IMM,`LDY_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= ir[15:8];
                        end
                `ADC_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= acc8 + ir[15:8] + {7'b0,cf};
                                b8 <= ir[15:8];         // for overflow calc
                        end
                `SBC_IMM:
                        begin
                                pc <= pc + 32'd2;
//                              res8 <= acc8 - ir[15:8] - ~cf;
                                res8 <= acc8 - ir[15:8] - {7'b0,~cf};
                                $display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
                                b8 <= ir[15:8];         // for overflow calc
                        end
                `AND_IMM,`BIT_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= acc8 & ir[15:8];
                                b8 <= ir[15:8]; // for bit flags
                        end
                `ORA_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= acc8 | ir[15:8];
                        end
                `EOR_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= acc8 ^ ir[15:8];
                        end
                `CMP_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= acc8 - ir[15:8];
                        end
                `CPX_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= x8 - ir[15:8];
                        end
                `CPY_IMM:
                        begin
                                pc <= pc + 32'd2;
                                res8 <= y8 - ir[15:8];
                        end
                // Handle zp mode
                `LDX_ZP,`LDY_ZP,`LDA_ZP:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
                `BIT_ZP,`CPX_ZP,`CPY_ZP,
                `ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ZP:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                wdat <= {4{acc8}};
                                state <= STORE1;
                        end
                `STX_ZP:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                wdat <= {4{x8}};
                                state <= STORE1;
                        end
                `STY_ZP:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                wdat <= {4{y8}};
                                state <= STORE1;
                        end
                `STZ_ZP:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                wdat <= {4{8'h00}};
                                state <= STORE1;
                        end
                // Handle zp,x mode
                `LDY_ZPX,`LDA_ZPX:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
                `BIT_ZPX,
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ZPX:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                wdat <= {4{acc8}};
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                wdat <= {4{y8}};
                                state <= STORE1;
                        end
                `STZ_ZPX:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                wdat <= {4{8'h00}};
                                state <= STORE1;
                        end
                // Handle zp,y
                `LDX_ZPY:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zpy_address[31:2];
                                radr2LSB <= zpy_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `STX_ZPY:
                        begin
                                pc <= pc + 32'd2;
                                wadr <= zpy_address[31:2];
                                wadr2LSB <= zpy_address[1:0];
                                wdat <= {4{x8}};
                                state <= STORE1;
                        end
                // Handle (zp,x)
                `ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                // Handle (zp),y
                `ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                isIY <= `TRUE;
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                // Handle abs
                `LDA_ABS,`LDX_ABS,`LDY_ABS:
                        begin
                                pc <= pc + 32'd3;
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
                `CPX_ABS,`CPY_ABS,
                `BIT_ABS:
                        begin
                                pc <= pc + 32'd3;
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABS:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                wdat <= {4{acc8}};
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                wdat <= {4{x8}};
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                wdat <= {4{y8}};
                                state <= STORE1;
                        end
                `STZ_ABS:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                wdat <= {4{8'h00}};
                                state <= STORE1;
                        end
                // Handle abs,x
                `ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
                `LDY_ABSX:
                        begin
                                pc <= pc + 32'd3;
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABSX:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                wdat <= {4{acc8}};
                                state <= STORE1;
                        end
                `STZ_ABSX:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                wdat <= {4{8'h00}};
                                state <= STORE1;
                        end
                // Handle abs,y
                `ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
                `LDX_ABSY:
                        begin
                                pc <= pc + 32'd3;
                                radr <= absy_address[31:2];
                                radr2LSB <= absy_address[1:0];
                                load_what <= `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABSY:
                        begin
                                pc <= pc + 32'd3;
                                wadr <= absy_address[31:2];
                                wadr2LSB <= absy_address[1:0];
                                wdat <= {4{acc8}};
                                state <= STORE1;
                        end
                // Handle (zp)
                `ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
                        begin
                                pc <= pc + 32'd2;
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                wdat <= {4{pcp2[31:24]}};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{pcp2[31:24]}};
                                sp <= sp_dec;
                                vect <= `BYTE_IRQ_VECT;
                                state <= BYTE_IRQ1;
                                bf <= 1'b1;
                        end
                `JMP:
                        begin
                                pc[15:0] <= abs_address[15:0];
                        end
                `JML:
                        begin
                                pc <= ir[39:8];
                        end
                `JMP_IND:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `JSR:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                wdat <= {4{pcp2[15:8]}};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{pcp2[15:8]}};
                                sp <= sp_dec;
                                state <= BYTE_JSR1;
                        end
                `JSL:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                wdat <= {4{pcp4[31:24]}};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{pcp4[31:24]}};
                                sp <= sp_dec;
                                state <= BYTE_JSL1;
                        end
                `JSR_INDX:
                        begin
                                radr <= {spage[31:8],sp[7:2]};
                                wadr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr2LSB <= sp[1:0];
                                wdat <= {4{pcp2[15:8]}};
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                case(sp_dec[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{pcp2[15:8]}};
                                sp <= sp_dec;
                                state <= BYTE_JSR_INDX1;
                        end
                `RTS,`RTL:
                        begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `RTI:   begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `SR_70;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
                        begin
//                              if (ir[15:8]==8'hFE) begin
//                                      radr <= {24'h1,sp[7:2]};
//                                      radr2LSB <= sp[1:0];
//                                      wadr <= {24'h1,sp[7:2]};
//                                      wadr2LSB <= sp[1:0];
//                                      case(sp[1:0])
//                                      2'd0:   sel_o <= 4'b0001;
//                                      2'd1:   sel_o <= 4'b0010;
//                                      2'd2:   sel_o <= 4'b0100;
//                                      2'd3:   sel_o <= 4'b1000;
//                                      endcase
//                                      wdat <= {4{pcp2[31:24]}};
//                                      cyc_o <= 1'b1;
//                                      stb_o <= 1'b1;
//                                      we_o <= 1'b1;
//                                      adr_o <= {24'h1,sp[7:2],2'b00};
//                                      dat_o <= {4{pcp2[31:24]}};
//                                      vect <= `SLP_VECT;
//                                      state <= BYTE_IRQ1;
//                              end
//                              else
                                if (ir[15:8]==8'hFF) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pc + 32'd4;
                                end
                                else begin
                                        if (takb)
                                                pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
                                        else
                                                pc <= pc + 32'd2;
                                end
                        end
                `PHP:
                        begin
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{sr8}};
                                wdat <= {4{sr8}};
                                sp <= sp_dec;
                                state <= STORE2;
                                pc <= pc + 32'd1;
                        end
                `PHA:
                        begin
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{acc8}};
                                wdat <= {4{acc8}};
                                sp <= sp_dec;
                                state <= STORE2;
                                pc <= pc + 32'd1;
                        end
                `PHX:
                        begin
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{x8}};
                                wdat <= {4{x8}};
                                sp <= sp_dec;
                                state <= STORE2;
                                pc <= pc + 32'd1;
                        end
                `PHY:
                        begin
                                cyc_o <= 1'b1;
                                stb_o <= 1'b1;
                                we_o <= 1'b1;
                                radr <= {spage[31:8],sp[7:2]};
                                radr2LSB <= sp[1:0];
                                wadr <= {spage[31:8],sp[7:2]};
                                wadr2LSB <= sp[1:0];
                                case(sp[1:0])
                                2'd0:   sel_o <= 4'b0001;
                                2'd1:   sel_o <= 4'b0010;
                                2'd2:   sel_o <= 4'b0100;
                                2'd3:   sel_o <= 4'b1000;
                                endcase
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
                                dat_o <= {4{y8}};
                                wdat <= {4{y8}};
                                sp <= sp_dec;
                                pc <= pc + 32'd1;
                                state <= STORE2;
                        end
                `PLP:
                        begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `SR_70;
                                state <= LOAD_MAC1;
                                pc <= pc + 32'd1;
                        end
                `PLA,`PLX,`PLY:
                        begin
                                radr <= {spage[31:8],sp_inc[7:2]};
                                radr2LSB <= sp_inc[1:0];
                                sp <= sp_inc;
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                                pc <= pc + 32'd1;
                        end
                default:        // unimplemented opcode
                        pc <= pc + 32'd1;
                endcase
        end
 

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Byte mode decode/execute state`
22			`// ============================================================================`
23			`//`
24			`BYTE_DECODE:`
25			`begin`
26			first_ifetch <= `TRUE;
27			`state <= IFETCH;`
28			`case(ir[7:0])`
29			`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
30			`NAT: begin em <= 1'b0; pc <= pc + 32'd1; end
31			`NOP: pc <= pc + 32'd1;
32			`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
33			`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
34			`CLV: begin vf <= 1'b0; pc <= pc + 32'd1; end
35			`CLI: begin im <= 1'b0; pc <= pc + 32'd1; end
36			`SEI: begin im <= 1'b1; pc <= pc + 32'd1; end
37			`CLD: begin df <= 1'b0; pc <= pc + 32'd1; end
38			`SED: begin df <= 1'b1; pc <= pc + 32'd1; end
39			`WAI: begin wai <= 1'b1; pc <= pc + 32'd1; end
40			`DEX: begin res8 <= x[7:0] - 8'd1; pc <= pc + 32'd1; end
41			`INX: begin res8 <= x[7:0] + 8'd1; pc <= pc + 32'd1; end
42			`DEY: begin res8 <= y[7:0] - 8'd1; pc <= pc + 32'd1; end
43			`INY: begin res8 <= y[7:0] + 8'd1; pc <= pc + 32'd1; end
44			`DEA: begin res8 <= acc[7:0] - 8'd1; pc <= pc + 32'd1; end
45			`INA: begin res8 <= acc[7:0] + 8'd1; pc <= pc + 32'd1; end
46			`TSX,`TSA: begin res8 <= sp[7:0]; pc <= pc + 32'd1; end
47			`TXS,`TXA,`TXY: begin res8 <= x[7:0]; pc <= pc + 32'd1; end
48			`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; pc <= pc + 32'd1; end
49			`TYA,`TYX: begin res8 <= y[7:0]; pc <= pc + 32'd1; end
50			`ASL_ACC: begin res8 <= {acc8,1'b0}; pc <= pc + 32'd1; end
51			`ROL_ACC: begin res8 <= {acc8,cf}; pc <= pc + 32'd1; end
52			`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; pc <= pc + 32'd1; end
53			`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; pc <= pc + 32'd1; end
54			`// Handle # mode`
55			`LDA_IMM,`LDX_IMM,`LDY_IMM:
56			`begin`
57			`pc <= pc + 32'd2;`
58			`res8 <= ir[15:8];`
59			`end`
60			`ADC_IMM:
61			`begin`
62			`pc <= pc + 32'd2;`
63			`res8 <= acc8 + ir[15:8] + {7'b0,cf};`
64			`b8 <= ir[15:8]; // for overflow calc`
65			`end`
66			`SBC_IMM:
67			`begin`
68			`pc <= pc + 32'd2;`
69			`// res8 <= acc8 - ir[15:8] - ~cf;`
70			`res8 <= acc8 - ir[15:8] - {7'b0,~cf};`
71			`$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);`
72			`b8 <= ir[15:8]; // for overflow calc`
73			`end`
74			`AND_IMM,`BIT_IMM:
75			`begin`
76			`pc <= pc + 32'd2;`
77			`res8 <= acc8 & ir[15:8];`
78			`b8 <= ir[15:8]; // for bit flags`
79			`end`
80			`ORA_IMM:
81			`begin`
82			`pc <= pc + 32'd2;`
83			`res8 <= acc8 \| ir[15:8];`
84			`end`
85			`EOR_IMM:
86			`begin`
87			`pc <= pc + 32'd2;`
88			`res8 <= acc8 ^ ir[15:8];`
89			`end`
90			`CMP_IMM:
91			`begin`
92			`pc <= pc + 32'd2;`
93			`res8 <= acc8 - ir[15:8];`
94			`end`
95			`CPX_IMM:
96			`begin`
97			`pc <= pc + 32'd2;`
98			`res8 <= x8 - ir[15:8];`
99			`end`
100			`CPY_IMM:
101			`begin`
102			`pc <= pc + 32'd2;`
103			`res8 <= y8 - ir[15:8];`
104			`end`
105			`// Handle zp mode`
106	21	robfinch	`LDX_ZP,`LDY_ZP,`LDA_ZP:
107			`begin`
108			`pc <= pc + 32'd2;`
109			`radr <= zp_address[31:2];`
110			`radr2LSB <= zp_address[1:0];`
111			load_what <= `BYTE_71;
112			`state <= LOAD_MAC1;`
113			`end`
114			`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
115			`BIT_ZP,`CPX_ZP,`CPY_ZP,
116	20	robfinch	`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
117			`begin`
118			`pc <= pc + 32'd2;`
119			`radr <= zp_address[31:2];`
120			`radr2LSB <= zp_address[1:0];`
121	21	robfinch	load_what <= `BYTE_70;
122			`state <= LOAD_MAC1;`
123	20	robfinch	`end`
124			`STA_ZP:
125			`begin`
126			`pc <= pc + 32'd2;`
127			`wadr <= zp_address[31:2];`
128			`wadr2LSB <= zp_address[1:0];`
129			`wdat <= {4{acc8}};`
130			`state <= STORE1;`
131			`end`
132			`STX_ZP:
133			`begin`
134			`pc <= pc + 32'd2;`
135			`wadr <= zp_address[31:2];`
136			`wadr2LSB <= zp_address[1:0];`
137			`wdat <= {4{x8}};`
138			`state <= STORE1;`
139			`end`
140			`STY_ZP:
141			`begin`
142			`pc <= pc + 32'd2;`
143			`wadr <= zp_address[31:2];`
144			`wadr2LSB <= zp_address[1:0];`
145			`wdat <= {4{y8}};`
146			`state <= STORE1;`
147			`end`
148			`STZ_ZP:
149			`begin`
150			`pc <= pc + 32'd2;`
151			`wadr <= zp_address[31:2];`
152			`wadr2LSB <= zp_address[1:0];`
153			`wdat <= {4{8'h00}};`
154			`state <= STORE1;`
155			`end`
156			`// Handle zp,x mode`
157	21	robfinch	`LDY_ZPX,`LDA_ZPX:
158			`begin`
159			`pc <= pc + 32'd2;`
160			`radr <= zpx_address[31:2];`
161			`radr2LSB <= zpx_address[1:0];`
162			load_what <= `BYTE_71;
163			`state <= LOAD_MAC1;`
164			`end`
165			`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
166			`BIT_ZPX,
167	20	robfinch	`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
168			`begin`
169			`pc <= pc + 32'd2;`
170			`radr <= zpx_address[31:2];`
171			`radr2LSB <= zpx_address[1:0];`
172	21	robfinch	load_what <= `BYTE_70;
173			`state <= LOAD_MAC1;`
174	20	robfinch	`end`
175			`STA_ZPX:
176			`begin`
177			`pc <= pc + 32'd2;`
178			`wadr <= zpx_address[31:2];`
179			`wadr2LSB <= zpx_address[1:0];`
180			`wdat <= {4{acc8}};`
181			`state <= STORE1;`
182			`end`
183			`STY_ZPX:
184			`begin`
185			`pc <= pc + 32'd2;`
186			`wadr <= zpx_address[31:2];`
187			`wadr2LSB <= zpx_address[1:0];`
188			`wdat <= {4{y8}};`
189			`state <= STORE1;`
190			`end`
191			`STZ_ZPX:
192			`begin`
193			`pc <= pc + 32'd2;`
194			`wadr <= zpx_address[31:2];`
195			`wadr2LSB <= zpx_address[1:0];`
196			`wdat <= {4{8'h00}};`
197			`state <= STORE1;`
198			`end`
199			`// Handle zp,y`
200			`LDX_ZPY:
201			`begin`
202			`pc <= pc + 32'd2;`
203			`radr <= zpy_address[31:2];`
204			`radr2LSB <= zpy_address[1:0];`
205	21	robfinch	load_what <= `BYTE_71;
206			`state <= LOAD_MAC1;`
207	20	robfinch	`end`
208			`STX_ZPY:
209			`begin`
210			`pc <= pc + 32'd2;`
211			`wadr <= zpy_address[31:2];`
212			`wadr2LSB <= zpy_address[1:0];`
213			`wdat <= {4{x8}};`
214			`state <= STORE1;`
215			`end`
216			`// Handle (zp,x)`
217			`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
218			`begin`
219			`pc <= pc + 32'd2;`
220			`radr <= zpx_address[31:2];`
221			`radr2LSB <= zpx_address[1:0];`
222	21	robfinch	load_what <= `IA_70;
223			`state <= LOAD_MAC1;`
224	20	robfinch	`end`
225			`// Handle (zp),y`
226			`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
227			`begin`
228			`pc <= pc + 32'd2;`
229			`radr <= zp_address[31:2];`
230			`radr2LSB <= zp_address[1:0];`
231	21	robfinch	isIY <= `TRUE;
232			load_what <= `IA_70;
233			`state <= LOAD_MAC1;`
234	20	robfinch	`end`
235			`// Handle abs`
236	21	robfinch	`LDA_ABS,`LDX_ABS,`LDY_ABS:
237			`begin`
238			`pc <= pc + 32'd3;`
239			`radr <= abs_address[31:2];`
240			`radr2LSB <= abs_address[1:0];`
241			load_what <= `BYTE_71;
242			`state <= LOAD_MAC1;`
243			`end`
244			`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
245	20	robfinch	`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
246			`CPX_ABS,`CPY_ABS,
247			`BIT_ABS:
248			`begin`
249			`pc <= pc + 32'd3;`
250			`radr <= abs_address[31:2];`
251			`radr2LSB <= abs_address[1:0];`
252	21	robfinch	load_what <= `BYTE_70;
253			`state <= LOAD_MAC1;`
254	20	robfinch	`end`
255			`STA_ABS:
256			`begin`
257			`pc <= pc + 32'd3;`
258			`wadr <= abs_address[31:2];`
259			`wadr2LSB <= abs_address[1:0];`
260			`wdat <= {4{acc8}};`
261			`state <= STORE1;`
262			`end`
263			`STX_ABS:
264			`begin`
265			`pc <= pc + 32'd3;`
266			`wadr <= abs_address[31:2];`
267			`wadr2LSB <= abs_address[1:0];`
268			`wdat <= {4{x8}};`
269			`state <= STORE1;`
270			`end`
271			`STY_ABS:
272			`begin`
273			`pc <= pc + 32'd3;`
274			`wadr <= abs_address[31:2];`
275			`wadr2LSB <= abs_address[1:0];`
276			`wdat <= {4{y8}};`
277			`state <= STORE1;`
278			`end`
279			`STZ_ABS:
280			`begin`
281			`pc <= pc + 32'd3;`
282			`wadr <= abs_address[31:2];`
283			`wadr2LSB <= abs_address[1:0];`
284			`wdat <= {4{8'h00}};`
285			`state <= STORE1;`
286			`end`
287			`// Handle abs,x`
288			`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
289			`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
290			`LDY_ABSX:
291			`begin`
292			`pc <= pc + 32'd3;`
293			`radr <= absx_address[31:2];`
294			`radr2LSB <= absx_address[1:0];`
295	21	robfinch	load_what <= `BYTE_70;
296			`state <= LOAD_MAC1;`
297	20	robfinch	`end`
298			`STA_ABSX:
299			`begin`
300			`pc <= pc + 32'd3;`
301			`wadr <= absx_address[31:2];`
302			`wadr2LSB <= absx_address[1:0];`
303			`wdat <= {4{acc8}};`
304			`state <= STORE1;`
305			`end`
306			`STZ_ABSX:
307			`begin`
308			`pc <= pc + 32'd3;`
309			`wadr <= absx_address[31:2];`
310			`wadr2LSB <= absx_address[1:0];`
311			`wdat <= {4{8'h00}};`
312			`state <= STORE1;`
313			`end`
314			`// Handle abs,y`
315			`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
316			`LDX_ABSY:
317			`begin`
318			`pc <= pc + 32'd3;`
319			`radr <= absy_address[31:2];`
320			`radr2LSB <= absy_address[1:0];`
321	21	robfinch	load_what <= `BYTE_70;
322			`state <= LOAD_MAC1;`
323	20	robfinch	`end`
324			`STA_ABSY:
325			`begin`
326			`pc <= pc + 32'd3;`
327			`wadr <= absy_address[31:2];`
328			`wadr2LSB <= absy_address[1:0];`
329			`wdat <= {4{acc8}};`
330			`state <= STORE1;`
331			`end`
332			`// Handle (zp)`
333			`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
334			`begin`
335			`pc <= pc + 32'd2;`
336			`radr <= zp_address[31:2];`
337			`radr2LSB <= zp_address[1:0];`
338	21	robfinch	load_what <= `IA_70;
339			`state <= LOAD_MAC1;`
340	20	robfinch	`end`
341			`BRK:
342			`begin`
343			`radr <= {spage[31:8],sp[7:2]};`
344			`radr2LSB <= sp[1:0];`
345			`wadr <= {spage[31:8],sp[7:2]};`
346			`wadr2LSB <= sp[1:0];`
347	25	robfinch	`wdat <= {4{pcp2[31:24]}};`
348	20	robfinch	`cyc_o <= 1'b1;`
349			`stb_o <= 1'b1;`
350			`we_o <= 1'b1;`
351			`case(sp[1:0])`
352			`2'd0: sel_o <= 4'b0001;`
353			`2'd1: sel_o <= 4'b0010;`
354			`2'd2: sel_o <= 4'b0100;`
355			`2'd3: sel_o <= 4'b1000;`
356			`endcase`
357			`adr_o <= {spage[31:8],sp[7:2],2'b00};`
358	25	robfinch	`dat_o <= {4{pcp2[31:24]}};`
359	20	robfinch	`sp <= sp_dec;`
360			vect <= `BYTE_IRQ_VECT;
361			`state <= BYTE_IRQ1;`
362			`bf <= 1'b1;`
363			`end`
364			`JMP:
365			`begin`
366			`pc[15:0] <= abs_address[15:0];`
367			`end`
368			`JML:
369			`begin`
370			`pc <= ir[39:8];`
371			`end`
372			`JMP_IND:
373			`begin`
374			`radr <= abs_address[31:2];`
375			`radr2LSB <= abs_address[1:0];`
376	21	robfinch	load_what <= `PC_70;
377			`state <= LOAD_MAC1;`
378	20	robfinch	`end`
379			`JMP_INDX:
380			`begin`
381			`radr <= absx_address[31:2];`
382			`radr2LSB <= absx_address[1:0];`
383	21	robfinch	load_what <= `PC_70;
384			`state <= LOAD_MAC1;`
385	20	robfinch	`end`
386			`JSR:
387			`begin`
388			`radr <= {spage[31:8],sp[7:2]};`
389			`wadr <= {spage[31:8],sp[7:2]};`
390			`radr2LSB <= sp[1:0];`
391			`wadr2LSB <= sp[1:0];`
392			`wdat <= {4{pcp2[15:8]}};`
393			`cyc_o <= 1'b1;`
394			`stb_o <= 1'b1;`
395			`we_o <= 1'b1;`
396			`case(sp[1:0])`
397			`2'd0: sel_o <= 4'b0001;`
398			`2'd1: sel_o <= 4'b0010;`
399			`2'd2: sel_o <= 4'b0100;`
400			`2'd3: sel_o <= 4'b1000;`
401			`endcase`
402			`adr_o <= {spage[31:8],sp[7:2],2'b00};`
403			`dat_o <= {4{pcp2[15:8]}};`
404			`sp <= sp_dec;`
405			`state <= BYTE_JSR1;`
406			`end`
407			`JSL:
408			`begin`
409			`radr <= {spage[31:8],sp[7:2]};`
410			`wadr <= {spage[31:8],sp[7:2]};`
411			`radr2LSB <= sp[1:0];`
412			`wadr2LSB <= sp[1:0];`
413			`wdat <= {4{pcp4[31:24]}};`
414			`cyc_o <= 1'b1;`
415			`stb_o <= 1'b1;`
416			`we_o <= 1'b1;`
417			`case(sp[1:0])`
418			`2'd0: sel_o <= 4'b0001;`
419			`2'd1: sel_o <= 4'b0010;`
420			`2'd2: sel_o <= 4'b0100;`
421			`2'd3: sel_o <= 4'b1000;`
422			`endcase`
423			`adr_o <= {spage[31:8],sp[7:2],2'b00};`
424			`dat_o <= {4{pcp4[31:24]}};`
425			`sp <= sp_dec;`
426			`state <= BYTE_JSL1;`
427			`end`
428			`JSR_INDX:
429			`begin`
430			`radr <= {spage[31:8],sp[7:2]};`
431			`wadr <= {spage[31:8],sp[7:2]};`
432			`radr2LSB <= sp[1:0];`
433			`wadr2LSB <= sp[1:0];`
434			`wdat <= {4{pcp2[15:8]}};`
435			`cyc_o <= 1'b1;`
436			`stb_o <= 1'b1;`
437			`we_o <= 1'b1;`
438			`case(sp_dec[1:0])`
439			`2'd0: sel_o <= 4'b0001;`
440			`2'd1: sel_o <= 4'b0010;`
441			`2'd2: sel_o <= 4'b0100;`
442			`2'd3: sel_o <= 4'b1000;`
443			`endcase`
444			`adr_o <= {spage[31:8],sp[7:2],2'b00};`
445			`dat_o <= {4{pcp2[15:8]}};`
446			`sp <= sp_dec;`
447			`state <= BYTE_JSR_INDX1;`
448			`end`
449			`RTS,`RTL:
450			`begin`
451			`radr <= {spage[31:8],sp_inc[7:2]};`
452			`radr2LSB <= sp_inc[1:0];`
453			`sp <= sp_inc;`
454	21	robfinch	load_what <= `PC_70;
455			`state <= LOAD_MAC1;`
456	20	robfinch	`end`
457			`RTI: begin
458			`radr <= {spage[31:8],sp_inc[7:2]};`
459			`radr2LSB <= sp_inc[1:0];`
460			`sp <= sp_inc;`
461	21	robfinch	load_what <= `SR_70;
462			`state <= LOAD_MAC1;`
463	20	robfinch	`end`
464			`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
465			`begin`
466			`// if (ir[15:8]==8'hFE) begin`
467			`// radr <= {24'h1,sp[7:2]};`
468			`// radr2LSB <= sp[1:0];`
469			`// wadr <= {24'h1,sp[7:2]};`
470			`// wadr2LSB <= sp[1:0];`
471			`// case(sp[1:0])`
472			`// 2'd0: sel_o <= 4'b0001;`
473			`// 2'd1: sel_o <= 4'b0010;`
474			`// 2'd2: sel_o <= 4'b0100;`
475			`// 2'd3: sel_o <= 4'b1000;`
476			`// endcase`
477			`// wdat <= {4{pcp2[31:24]}};`
478			`// cyc_o <= 1'b1;`
479			`// stb_o <= 1'b1;`
480			`// we_o <= 1'b1;`
481			`// adr_o <= {24'h1,sp[7:2],2'b00};`
482			`// dat_o <= {4{pcp2[31:24]}};`
483			// vect <= `SLP_VECT;
484			`// state <= BYTE_IRQ1;`
485			`// end`
486			`// else`
487			`if (ir[15:8]==8'hFF) begin`
488			`if (takb)`
489			`pc <= pc + {{16{ir[31]}},ir[31:16]};`
490			`else`
491			`pc <= pc + 32'd4;`
492			`end`
493			`else begin`
494			`if (takb)`
495			`pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;`
496			`else`
497			`pc <= pc + 32'd2;`
498			`end`
499			`end`
500			`PHP:

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