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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_decode.v] - Blame information for rev 38

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013,2014  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// Byte mode decode/execute state
// ============================================================================
//
BYTE_DECODE:
        begin
                first_ifetch <= `TRUE;
                next_state(BYTE_IFETCH);
                pc <= pc + pc_inc8;
                case(ir[7:0])
                `SEP:   ;       // see byte_ifetch
                `REP:   ;
                // XBA cannot be done in the ifetch stage because it'd repeat when there
                // was a cache miss, causing the instruction to be done twice.
                `XBA:
                        begin
                                res16 <= {acc[7:0],acc[15:8]};
                                res8 <= acc[15:8];      // for flag settings
                        end
                `STP:   begin clk_en <= 1'b0; end
//              `NAT:   begin em <= 1'b0; state <= IFETCH; end
                `WDM:   if (ir[15:8]==`XCE) begin
                                        em <= 1'b0;
                                        next_state(IFETCH);
                                        pc <= pc + 32'd2;
                                end
                // Switching the processor mode always zeros out the upper part of the index registers.
                // switching to 816 mode sets 8 bit memory/indexes
                `XCE:   begin
                                        m816 <= ~cf;
                                        cf <= ~m816;
                                        if (~cf) begin
                                                m_bit <= 1'b1;
                                                x_bit <= 1'b1;
                                        end
                                        x[31:8] <= 24'd0;
                                        y[31:8] <= 24'd0;
                                end
//              `NOP:   ;       // may help routing
                `CLC:   begin cf <= 1'b0; end
                `SEC:   begin cf <= 1'b1; end
                `CLV:   begin vf <= 1'b0; end
                `CLI:   begin im <= 1'b0; end
                `SEI:   begin im <= 1'b1; end
                `CLD:   begin df <= 1'b0; end
                `SED:   begin df <= 1'b1; end
                `WAI:   begin wai <= 1'b1; end
                `DEX:   begin res8 <= x_dec[7:0]; res16 <= x_dec[15:0]; end
                `INX:   begin res8 <= x_inc[7:0]; res16 <= x_inc[15:0]; end
                `DEY:   begin res8 <= y_dec[7:0]; res16 <= y_dec[15:0]; end
                `INY:   begin res8 <= y_inc[7:0]; res16 <= y_inc[15:0]; end
                `DEA:   begin res8 <= acc_dec[7:0]; res16 <= acc_dec[15:0]; end
                `INA:   begin res8 <= acc_inc[7:0]; res16 <= acc_inc[15:0]; end
                `TSX,`TSA:      begin res8 <= sp[7:0]; res16 <= sp[15:0]; end
                `TXS,`TXA,`TXY: begin res8 <= x[7:0]; res16 <= xb16 ? x[15:0] : {8'h00,x8}; end
                `TAX,`TAY:      begin res8 <= acc[7:0]; res16 <= m16 ? acc[15:0] : {8'h00,acc8}; end
                `TAS:   begin res8 <= acc[7:0]; res16 <= acc[15:0]; end
                `TYA,`TYX:      begin res8 <= y[7:0]; res16 <= xb16 ? y[15:0] : {8'h00,y8}; end
                `TDC:           begin res16 <= dpr; end
                `TCD:           begin res16 <= acc[15:0]; end
                `ASL_ACC:       begin res8 <= {acc8,1'b0}; res16 <= {acc16,1'b0}; end
                `ROL_ACC:       begin res8 <= {acc8,cf}; res16 <= {acc16,cf}; end
                `LSR_ACC:       begin res8 <= {acc8[0],1'b0,acc8[7:1]}; res16 <= {acc16[0],1'b0,acc16[15:1]}; end
                `ROR_ACC:       begin res8 <= {acc8[0],cf,acc8[7:1]}; res16 <= {acc16[0],cf,acc16[15:1]}; end
                // Handle # mode
                `LDA_IMM:
                        begin
                                res8 <= ir[15:8];
                                res16 <= ir[23:8];
                        end
                `LDX_IMM,`LDY_IMM:
                        begin
                                res8 <= ir[15:8];
                                res16 <= ir[23:8];
                        end
                `ADC_IMM:
                        begin
                                res8 <= acc8 + ir[15:8] + {7'b0,cf};
                                res16 <= acc16 + ir[23:8] + {15'b0,cf};
                                b8 <= ir[15:8];         // for overflow calc
                                b16 <= ir[23:8];
                        end
                `SBC_IMM:
                        begin
//                              res8 <= acc8 - ir[15:8] - ~cf;
                                res8 <= acc8 - ir[15:8] - {7'b0,~cf};
                                res16 <= acc16 - ir[23:8] - {15'b0,~cf};
                                $display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
                                b8 <= ir[15:8];         // for overflow calc
                                b16 <= ir[23:8];
                        end
                `AND_IMM,`BIT_IMM:
                        begin
                                res8 <= acc8 & ir[15:8];
                                res16 <= acc16 & ir[23:8];
                                b8 <= ir[15:8]; // for bit flags
                                b16 <= ir[23:8];
                        end
                `ORA_IMM:       begin res8 <= acc8 | ir[15:8]; res16 <= acc16 | ir[23:8]; end
                `EOR_IMM:       begin res8 <= acc8 ^ ir[15:8]; res16 <= acc16 ^ ir[23:8]; end
                `CMP_IMM:       begin res8 <= acc8 - ir[15:8]; res16 <= acc16 - ir[23:8]; end
                `CPX_IMM:       begin res8 <= x8 - ir[15:8]; res16 <= x16 - ir[23:8]; end
                `CPY_IMM:       begin res8 <= y8 - ir[15:8]; res16 <= y16 - ir[23:8]; end
                // Handle zp mode
                `LDA_ZP:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `LDX_ZP,`LDY_ZP:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= xb16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
                `BIT_ZP,
                `ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `CPX_ZP,`CPY_ZP:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= xb16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                `STX_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= xb16 ? `STW_X70 : `STW_X8;
                                state <= STORE1;
                        end
                `STY_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= xb16 ? `STW_Y70 : `STW_Y8;
                                state <= STORE1;
                        end
                `STZ_ZP:
                        begin
                                wadr <= zp_address[31:2];
                                wadr2LSB <= zp_address[1:0];
                                store_what <= m16 ? `STW_Z70 : `STW_Z8;
                                state <= STORE1;
                        end
                // Handle zp,x mode
                `LDA_ZPX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `LDY_ZPX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= xb16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
                `BIT_ZPX,
                `ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ZPX:
                        begin
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                `STY_ZPX:
                        begin
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                store_what <= xb16 ? `STW_Y70 : `STW_Y8;
                                state <= STORE1;
                        end
                `STZ_ZPX:
                        begin
                                wadr <= zpx_address[31:2];
                                wadr2LSB <= zpx_address[1:0];
                                store_what <= m16 ? `STW_Z70 : `STW_Z8;
                                state <= STORE1;
                        end
                // Handle zp,y
                `LDX_ZPY:
                        begin
                                radr <= zpy_address[31:2];
                                radr2LSB <= zpy_address[1:0];
                                load_what <= xb16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `STX_ZPY:
                        begin
                                wadr <= zpy_address[31:2];
                                wadr2LSB <= zpy_address[1:0];
                                store_what <= xb16 ? `STW_X70 : `STW_X8;
                                state <= STORE1;
                        end
                // Handle (zp,x)
                `ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
                        begin
                                radr <= zpx_address[31:2];
                                radr2LSB <= zpx_address[1:0];
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                // Handle (zp),y
                `ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                isIY <= `TRUE;
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                // Handle abs
                `LDA_ABS:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABS,`LDY_ABS:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= xb16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
                `ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
                `BIT_ABS:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `CPX_ABS,`CPY_ABS:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= xb16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                `STX_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= xb16 ? `STW_X70 : `STW_X8;
                                state <= STORE1;
                        end
                `STY_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= xb16 ? `STW_Y70 : `STW_Y8;
                                state <= STORE1;
                        end
                `STZ_ABS:
                        begin
                                wadr <= abs_address[31:2];
                                wadr2LSB <= abs_address[1:0];
                                store_what <= m16 ? `STW_Z70 : `STW_Z8;
                                state <= STORE1;
                        end
                // Handle abs,x
                `LDA_ABSX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,
                `ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `LDY_ABSX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= xb16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `STA_ABSX:
                        begin
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                `STZ_ABSX:
                        begin
                                wadr <= absx_address[31:2];
                                wadr2LSB <= absx_address[1:0];
                                store_what <= m16 ? `STW_Z70 : `STW_Z8;
                                state <= STORE1;
                        end
                // Handle abs,y
                `LDA_ABSY:
                        begin
                                radr <= absy_address[31:2];
                                radr2LSB <= absy_address[1:0];
                                load_what <= m16 ? `HALF_71     : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY:
                        begin
                                radr <= absy_address[31:2];
                                radr2LSB <= absy_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `LDX_ABSY:
                        begin
                                radr <= absy_address[31:2];
                                radr2LSB <= absy_address[1:0];
                                load_what <= xb16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `STA_ABSY:
                        begin
                                wadr <= absy_address[31:2];
                                wadr2LSB <= absy_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
`ifdef SUPPORT_816
                // Handle d,sp
                `LDA_DSP:
                        begin
                                radr <= dsp_address[31:2];
                                radr2LSB <= dsp_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_DSP,`SBC_DSP,`CMP_DSP,`ORA_DSP,`AND_DSP,`EOR_DSP:
                        begin
                                radr <= dsp_address[31:2];
                                radr2LSB <= dsp_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_DSP:
                        begin
                                wadr <= dsp_address[31:2];
                                wadr2LSB <= dsp_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                // Handle (d,sp),y
                `ADC_DSPIY,`SBC_DSPIY,`CMP_DSPIY,`ORA_DSPIY,`AND_DSPIY,`EOR_DSPIY,`LDA_DSPIY,`STA_DSPIY:
                        begin
                                radr <= dsp_address[31:2];
                                radr2LSB <= dsp_address[1:0];
                                isIY <= `TRUE;
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                // Handle [zp],y
                `ADC_IYL,`SBC_IYL,`AND_IYL,`ORA_IYL,`EOR_IYL,`CMP_IYL,`LDA_IYL,`STA_IYL:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                isIY24 <= `TRUE;
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                // Handle al
                `LDA_AL:
                        begin
                                radr <= al_address[31:2];
                                radr2LSB <= al_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_AL,`SBC_AL,`AND_AL,`ORA_AL,`EOR_AL,`CMP_AL:
                        begin
                                radr <= al_address[31:2];
                                radr2LSB <= al_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_AL:
                        begin
                                wadr <= al_address[31:2];
                                wadr2LSB <= al_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                // Handle alx
                `LDA_ALX:
                        begin
                                radr <= alx_address[31:2];
                                radr2LSB <= alx_address[1:0];
                                load_what <= m16 ? `HALF_71 : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `ADC_ALX,`SBC_ALX,`AND_ALX,`ORA_ALX,`EOR_ALX,`CMP_ALX:
                        begin
                                radr <= alx_address[31:2];
                                radr2LSB <= alx_address[1:0];
                                load_what <= m16 ? `HALF_70 : `BYTE_70;
                                state <= LOAD_MAC1;
                        end
                `STA_ALX:
                        begin
                                wadr <= alx_address[31:2];
                                wadr2LSB <= alx_address[1:0];
                                store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
                                state <= STORE1;
                        end
                // Handle [zp]
                `ADC_IL,`SBC_IL,`AND_IL,`ORA_IL,`EOR_IL,`CMP_IL,`LDA_IL,`STA_IL:
                        begin
                                isI24 <= `TRUE;
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
`endif
                // Handle (zp)
                `ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I,`PEI:
                        begin
                                radr <= zp_address[31:2];
                                radr2LSB <= zp_address[1:0];
                                load_what <= `IA_70;
                                state <= LOAD_MAC1;
                        end
                `BRK:
                        begin
                                set_sp();
                                store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
                                state <= STORE1;
                                bf <= !hwi;
                        end
`ifdef SUPPORT_816
                `COP:
                        begin
                                set_sp();
                                store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
                                state <= STORE1;
                                vect <= `COP_VECT_816;
                        end
`endif
                `JMP:
                        begin
                                pc[15:0] <= ir[23:8];
                        end
                `JML:
                        begin
                                pc[23:0] <= ir[31:8];
                        end
                `JMP_IND:
                        begin
                                radr <= abs_address[31:2];
                                radr2LSB <= abs_address[1:0];
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `JMP_INDX:
                        begin
                                radr <= absx_address[31:2];
                                radr2LSB <= absx_address[1:0];
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `JSR,`JSR_INDX:
                        begin
                                set_sp();
                                store_what <= `STW_PC158;
                                state <= STORE1;
                        end
                `JSL:
                        begin
                                set_sp();
                                store_what <= `STW_PC2316;
                                state <= STORE1;
                        end
                `RTS,`RTL:
                        begin
                                inc_sp();
                                load_what <= `PC_70;
                                state <= LOAD_MAC1;
                        end
                `RTI:   begin
                                inc_sp();
                                load_what <= `SR_70;
                                state <= LOAD_MAC1;
                                end
                `BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
/*
                        begin
                                if (ir[15:8]==8'hFF) begin
                                        if (takb)
                                                pc <= pc + {{16{ir[31]}},ir[31:16]};
                                        else
                                                pc <= pc + 32'd4;
                                end
                                else */
                                begin
                                        if (takb)
                                                pc <= pc + pc_inc8 + {{24{ir[15]}},ir[15:8]};
                                        else
                                                pc <= pc + pc_inc8;
                                end
                        //end
                `BRL:   pc <= pc + pc_inc8 + {{16{ir[23]}},ir[23:8]};
                `PHP:
                        begin
                                set_sp();
                                store_what <= `STW_SR70;
                                state <= STORE1;
                        end
                `PHA:   tsk_push(`STW_ACC8,`STW_ACC70,m16);
                `PHX:   tsk_push(`STW_X8,`STW_X70,xb16);
                `PHY:   tsk_push(`STW_Y8,`STW_Y70,xb16);
                `PLP:
                        begin
                                inc_sp();
                                load_what <= `SR_70;
                                state <= LOAD_MAC1;
                        end
                `PLA:
                        begin
                                inc_sp();
                                load_what <= m16 ? `HALF_71S : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `PLX,`PLY:
                        begin
                                inc_sp();
                                load_what <= xb16 ? `HALF_71S : `BYTE_71;
                                state <= LOAD_MAC1;
                        end
`ifdef SUPPORT_816
                `PHB:
                        begin
                                set_sp();
                                store_what <= `STW_DBR;
                                state <= STORE1;
                        end
                `PHD:
                        begin
                                set_sp();
                                store_what <= `STW_DPR158;
                                state <= STORE1;
                        end
                `PHK:
                        begin
                                set_sp();
                                store_what <= `STW_PC2316;
                                state <= STORE1;
                        end
                `PEA:
                        begin
                                tmp16 <= ir[23:8];
                                set_sp();
                                store_what <= `STW_TMP158;
                                state <= STORE1;
                        end
                `PER:
                        begin
                                tmp16 <= pc[15:0] + ir[23:8] + 16'd3;
                                set_sp();
                                store_what <= `STW_TMP158;
                                state <= STORE1;
                        end
                `PLB:
                        begin
                                inc_sp();
                                load_what <= `BYTE_71;
                                state <= LOAD_MAC1;
                        end
                `PLD:
                        begin
                                inc_sp();
                                load_what <= `HALF_71S;
                                state <= LOAD_MAC1;
                        end
                `MVN,`MVP:
                        begin
                                radr <= mvnsrc_address[31:2];
                                radr2LSB <= mvnsrc_address[1:0];
                                load_what <= `BYTE_72;
                                pc <= pc;       // override increment above
                                state <= LOAD_MAC1;
                        end
`endif
                default:        // unimplemented opcode
                        pc <= pc + 32'd1;
                endcase
        end
 

Line No.	Rev	Author	Line
1	20	robfinch	`// ============================================================================`
2			`// __`
3	38	robfinch	`// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford`
4	20	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// Byte mode decode/execute state`
22			`// ============================================================================`
23			`//`
24			`BYTE_DECODE:`
25			`begin`
26			first_ifetch <= `TRUE;
27	38	robfinch	`next_state(BYTE_IFETCH);`
28	32	robfinch	`pc <= pc + pc_inc8;`
29	20	robfinch	`case(ir[7:0])`
30	38	robfinch	`SEP: ; // see byte_ifetch
31			`REP: ;
32			`// XBA cannot be done in the ifetch stage because it'd repeat when there`
33			`// was a cache miss, causing the instruction to be done twice.`
34			`XBA:
35			`begin`
36			`res16 <= {acc[7:0],acc[15:8]};`
37			`res8 <= acc[15:8]; // for flag settings`
38			`end`
39	32	robfinch	`STP: begin clk_en <= 1'b0; end
40	38	robfinch	// `NAT: begin em <= 1'b0; state <= IFETCH; end
41			`WDM: if (ir[15:8]==`XCE) begin
42			`em <= 1'b0;`
43			`next_state(IFETCH);`
44			`pc <= pc + 32'd2;`
45			`end`
46			`// Switching the processor mode always zeros out the upper part of the index registers.`
47			`// switching to 816 mode sets 8 bit memory/indexes`
48			`XCE: begin
49			`m816 <= ~cf;`
50			`cf <= ~m816;`
51			`if (~cf) begin`
52			`m_bit <= 1'b1;`
53			`x_bit <= 1'b1;`
54			`end`
55			`x[31:8] <= 24'd0;`
56			`y[31:8] <= 24'd0;`
57			`end`
58			// `NOP: ; // may help routing
59	32	robfinch	`CLC: begin cf <= 1'b0; end
60			`SEC: begin cf <= 1'b1; end
61			`CLV: begin vf <= 1'b0; end
62			`CLI: begin im <= 1'b0; end
63			`SEI: begin im <= 1'b1; end
64			`CLD: begin df <= 1'b0; end
65			`SED: begin df <= 1'b1; end
66			`WAI: begin wai <= 1'b1; end
67	38	robfinch	`DEX: begin res8 <= x_dec[7:0]; res16 <= x_dec[15:0]; end
68			`INX: begin res8 <= x_inc[7:0]; res16 <= x_inc[15:0]; end
69			`DEY: begin res8 <= y_dec[7:0]; res16 <= y_dec[15:0]; end
70			`INY: begin res8 <= y_inc[7:0]; res16 <= y_inc[15:0]; end
71			`DEA: begin res8 <= acc_dec[7:0]; res16 <= acc_dec[15:0]; end
72			`INA: begin res8 <= acc_inc[7:0]; res16 <= acc_inc[15:0]; end
73			`TSX,`TSA: begin res8 <= sp[7:0]; res16 <= sp[15:0]; end
74			`TXS,`TXA,`TXY: begin res8 <= x[7:0]; res16 <= xb16 ? x[15:0] : {8'h00,x8}; end
75			`TAX,`TAY: begin res8 <= acc[7:0]; res16 <= m16 ? acc[15:0] : {8'h00,acc8}; end
76			`TAS: begin res8 <= acc[7:0]; res16 <= acc[15:0]; end
77			`TYA,`TYX: begin res8 <= y[7:0]; res16 <= xb16 ? y[15:0] : {8'h00,y8}; end
78			`TDC: begin res16 <= dpr; end
79			`TCD: begin res16 <= acc[15:0]; end
80			`ASL_ACC: begin res8 <= {acc8,1'b0}; res16 <= {acc16,1'b0}; end
81			`ROL_ACC: begin res8 <= {acc8,cf}; res16 <= {acc16,cf}; end
82			`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; res16 <= {acc16[0],1'b0,acc16[15:1]}; end
83			`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; res16 <= {acc16[0],cf,acc16[15:1]}; end
84	20	robfinch	`// Handle # mode`
85	38	robfinch	`LDA_IMM:
86	20	robfinch	`begin`
87			`res8 <= ir[15:8];`
88	38	robfinch	`res16 <= ir[23:8];`
89	20	robfinch	`end`
90	38	robfinch	`LDX_IMM,`LDY_IMM:
91			`begin`
92			`res8 <= ir[15:8];`
93			`res16 <= ir[23:8];`
94			`end`
95	20	robfinch	`ADC_IMM:
96			`begin`
97			`res8 <= acc8 + ir[15:8] + {7'b0,cf};`
98	38	robfinch	`res16 <= acc16 + ir[23:8] + {15'b0,cf};`
99	20	robfinch	`b8 <= ir[15:8]; // for overflow calc`
100	38	robfinch	`b16 <= ir[23:8];`
101	20	robfinch	`end`
102			`SBC_IMM:
103			`begin`
104			`// res8 <= acc8 - ir[15:8] - ~cf;`
105			`res8 <= acc8 - ir[15:8] - {7'b0,~cf};`
106	38	robfinch	`res16 <= acc16 - ir[23:8] - {15'b0,~cf};`
107	20	robfinch	`$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);`
108			`b8 <= ir[15:8]; // for overflow calc`
109	38	robfinch	`b16 <= ir[23:8];`
110	20	robfinch	`end`
111			`AND_IMM,`BIT_IMM:
112			`begin`
113			`res8 <= acc8 & ir[15:8];`
114	38	robfinch	`res16 <= acc16 & ir[23:8];`
115	20	robfinch	`b8 <= ir[15:8]; // for bit flags`
116	38	robfinch	`b16 <= ir[23:8];`
117	20	robfinch	`end`
118	38	robfinch	`ORA_IMM: begin res8 <= acc8 \| ir[15:8]; res16 <= acc16 \| ir[23:8]; end
119			`EOR_IMM: begin res8 <= acc8 ^ ir[15:8]; res16 <= acc16 ^ ir[23:8]; end
120			`CMP_IMM: begin res8 <= acc8 - ir[15:8]; res16 <= acc16 - ir[23:8]; end
121			`CPX_IMM: begin res8 <= x8 - ir[15:8]; res16 <= x16 - ir[23:8]; end
122			`CPY_IMM: begin res8 <= y8 - ir[15:8]; res16 <= y16 - ir[23:8]; end
123	20	robfinch	`// Handle zp mode`
124	38	robfinch	`LDA_ZP:
125	21	robfinch	`begin`
126			`radr <= zp_address[31:2];`
127			`radr2LSB <= zp_address[1:0];`
128	38	robfinch	load_what <= m16 ? `HALF_71 : `BYTE_71;
129	21	robfinch	`state <= LOAD_MAC1;`
130			`end`
131	38	robfinch	`LDX_ZP,`LDY_ZP:
132			`begin`
133			`radr <= zp_address[31:2];`
134			`radr2LSB <= zp_address[1:0];`
135			load_what <= xb16 ? `HALF_71 : `BYTE_71;
136			`state <= LOAD_MAC1;`
137			`end`
138	21	robfinch	`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
139	38	robfinch	`BIT_ZP,
140	20	robfinch	`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
141			`begin`
142			`radr <= zp_address[31:2];`
143			`radr2LSB <= zp_address[1:0];`
144	38	robfinch	`wadr <= zp_address[31:2];`
145			`wadr2LSB <= zp_address[1:0];`
146			load_what <= m16 ? `HALF_70 : `BYTE_70;
147	21	robfinch	`state <= LOAD_MAC1;`
148	20	robfinch	`end`
149	38	robfinch	`CPX_ZP,`CPY_ZP:
150			`begin`
151			`radr <= zp_address[31:2];`
152			`radr2LSB <= zp_address[1:0];`
153			load_what <= xb16 ? `HALF_70 : `BYTE_70;
154			`state <= LOAD_MAC1;`
155			`end`
156	20	robfinch	`STA_ZP:
157			`begin`
158			`wadr <= zp_address[31:2];`
159			`wadr2LSB <= zp_address[1:0];`
160	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
161	20	robfinch	`state <= STORE1;`
162			`end`
163			`STX_ZP:
164			`begin`
165			`wadr <= zp_address[31:2];`
166			`wadr2LSB <= zp_address[1:0];`
167	38	robfinch	store_what <= xb16 ? `STW_X70 : `STW_X8;
168	20	robfinch	`state <= STORE1;`
169			`end`
170			`STY_ZP:
171			`begin`
172			`wadr <= zp_address[31:2];`
173			`wadr2LSB <= zp_address[1:0];`
174	38	robfinch	store_what <= xb16 ? `STW_Y70 : `STW_Y8;
175	20	robfinch	`state <= STORE1;`
176			`end`
177			`STZ_ZP:
178			`begin`
179			`wadr <= zp_address[31:2];`
180			`wadr2LSB <= zp_address[1:0];`
181	38	robfinch	store_what <= m16 ? `STW_Z70 : `STW_Z8;
182	20	robfinch	`state <= STORE1;`
183			`end`
184			`// Handle zp,x mode`
185	38	robfinch	`LDA_ZPX:
186	21	robfinch	`begin`
187			`radr <= zpx_address[31:2];`
188			`radr2LSB <= zpx_address[1:0];`
189	38	robfinch	load_what <= m16 ? `HALF_71 : `BYTE_71;
190	21	robfinch	`state <= LOAD_MAC1;`
191			`end`
192	38	robfinch	`LDY_ZPX:
193			`begin`
194			`radr <= zpx_address[31:2];`
195			`radr2LSB <= zpx_address[1:0];`
196			load_what <= xb16 ? `HALF_71 : `BYTE_71;
197			`state <= LOAD_MAC1;`
198			`end`
199	21	robfinch	`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
200			`BIT_ZPX,
201	20	robfinch	`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
202			`begin`
203			`radr <= zpx_address[31:2];`
204			`radr2LSB <= zpx_address[1:0];`
205	38	robfinch	`wadr <= zpx_address[31:2];`
206			`wadr2LSB <= zpx_address[1:0];`
207			load_what <= m16 ? `HALF_70 : `BYTE_70;
208	21	robfinch	`state <= LOAD_MAC1;`
209	20	robfinch	`end`
210			`STA_ZPX:
211			`begin`
212			`wadr <= zpx_address[31:2];`
213			`wadr2LSB <= zpx_address[1:0];`
214	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
215	20	robfinch	`state <= STORE1;`
216			`end`
217			`STY_ZPX:
218			`begin`
219			`wadr <= zpx_address[31:2];`
220			`wadr2LSB <= zpx_address[1:0];`
221	38	robfinch	store_what <= xb16 ? `STW_Y70 : `STW_Y8;
222	20	robfinch	`state <= STORE1;`
223			`end`
224			`STZ_ZPX:
225			`begin`
226			`wadr <= zpx_address[31:2];`
227			`wadr2LSB <= zpx_address[1:0];`
228	38	robfinch	store_what <= m16 ? `STW_Z70 : `STW_Z8;
229	20	robfinch	`state <= STORE1;`
230			`end`
231			`// Handle zp,y`
232			`LDX_ZPY:
233			`begin`
234			`radr <= zpy_address[31:2];`
235			`radr2LSB <= zpy_address[1:0];`
236	38	robfinch	load_what <= xb16 ? `HALF_71 : `BYTE_71;
237	21	robfinch	`state <= LOAD_MAC1;`
238	20	robfinch	`end`
239			`STX_ZPY:
240			`begin`
241			`wadr <= zpy_address[31:2];`
242			`wadr2LSB <= zpy_address[1:0];`
243	38	robfinch	store_what <= xb16 ? `STW_X70 : `STW_X8;
244	20	robfinch	`state <= STORE1;`
245			`end`
246			`// Handle (zp,x)`
247			`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
248			`begin`
249			`radr <= zpx_address[31:2];`
250			`radr2LSB <= zpx_address[1:0];`
251	21	robfinch	load_what <= `IA_70;
252			`state <= LOAD_MAC1;`
253	20	robfinch	`end`
254			`// Handle (zp),y`
255			`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
256			`begin`
257			`radr <= zp_address[31:2];`
258			`radr2LSB <= zp_address[1:0];`
259	21	robfinch	isIY <= `TRUE;
260			load_what <= `IA_70;
261			`state <= LOAD_MAC1;`
262	20	robfinch	`end`
263			`// Handle abs`
264	38	robfinch	`LDA_ABS:
265	21	robfinch	`begin`
266			`radr <= abs_address[31:2];`
267			`radr2LSB <= abs_address[1:0];`
268	38	robfinch	load_what <= m16 ? `HALF_71 : `BYTE_71;
269	21	robfinch	`state <= LOAD_MAC1;`
270			`end`
271	38	robfinch	`LDX_ABS,`LDY_ABS:
272			`begin`
273			`radr <= abs_address[31:2];`
274			`radr2LSB <= abs_address[1:0];`
275			load_what <= xb16 ? `HALF_71 : `BYTE_71;
276			`state <= LOAD_MAC1;`
277			`end`
278	21	robfinch	`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
279	20	robfinch	`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
280			`BIT_ABS:
281			`begin`
282			`radr <= abs_address[31:2];`
283			`radr2LSB <= abs_address[1:0];`
284	38	robfinch	`wadr <= abs_address[31:2];`
285			`wadr2LSB <= abs_address[1:0];`
286			load_what <= m16 ? `HALF_70 : `BYTE_70;
287	21	robfinch	`state <= LOAD_MAC1;`
288	20	robfinch	`end`
289	38	robfinch	`CPX_ABS,`CPY_ABS:
290			`begin`
291			`radr <= abs_address[31:2];`
292			`radr2LSB <= abs_address[1:0];`
293			load_what <= xb16 ? `HALF_70 : `BYTE_70;
294			`state <= LOAD_MAC1;`
295			`end`
296	20	robfinch	`STA_ABS:
297			`begin`
298			`wadr <= abs_address[31:2];`
299			`wadr2LSB <= abs_address[1:0];`
300	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
301	20	robfinch	`state <= STORE1;`
302			`end`
303			`STX_ABS:
304			`begin`
305			`wadr <= abs_address[31:2];`
306			`wadr2LSB <= abs_address[1:0];`
307	38	robfinch	store_what <= xb16 ? `STW_X70 : `STW_X8;
308	20	robfinch	`state <= STORE1;`
309			`end`
310			`STY_ABS:
311			`begin`
312			`wadr <= abs_address[31:2];`
313			`wadr2LSB <= abs_address[1:0];`
314	38	robfinch	store_what <= xb16 ? `STW_Y70 : `STW_Y8;
315	20	robfinch	`state <= STORE1;`
316			`end`
317			`STZ_ABS:
318			`begin`
319			`wadr <= abs_address[31:2];`
320			`wadr2LSB <= abs_address[1:0];`
321	38	robfinch	store_what <= m16 ? `STW_Z70 : `STW_Z8;
322	20	robfinch	`state <= STORE1;`
323			`end`
324			`// Handle abs,x`
325	38	robfinch	`LDA_ABSX:
326			`begin`
327			`radr <= absx_address[31:2];`
328			`radr2LSB <= absx_address[1:0];`
329			load_what <= m16 ? `HALF_71 : `BYTE_71;
330			`state <= LOAD_MAC1;`
331			`end`
332			`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,
333			`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX:
334			`begin`
335			`radr <= absx_address[31:2];`
336			`radr2LSB <= absx_address[1:0];`
337			`wadr <= absx_address[31:2];`
338			`wadr2LSB <= absx_address[1:0];`
339			load_what <= m16 ? `HALF_70 : `BYTE_70;
340			`state <= LOAD_MAC1;`
341			`end`
342	20	robfinch	`LDY_ABSX:
343			`begin`
344			`radr <= absx_address[31:2];`
345			`radr2LSB <= absx_address[1:0];`
346	38	robfinch	load_what <= xb16 ? `HALF_71 : `BYTE_71;
347	21	robfinch	`state <= LOAD_MAC1;`
348	20	robfinch	`end`
349			`STA_ABSX:
350			`begin`
351			`wadr <= absx_address[31:2];`
352			`wadr2LSB <= absx_address[1:0];`
353	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
354	20	robfinch	`state <= STORE1;`
355			`end`
356			`STZ_ABSX:
357			`begin`
358			`wadr <= absx_address[31:2];`
359			`wadr2LSB <= absx_address[1:0];`
360	38	robfinch	store_what <= m16 ? `STW_Z70 : `STW_Z8;
361	20	robfinch	`state <= STORE1;`
362			`end`
363			`// Handle abs,y`
364	38	robfinch	`LDA_ABSY:
365			`begin`
366			`radr <= absy_address[31:2];`
367			`radr2LSB <= absy_address[1:0];`
368			load_what <= m16 ? `HALF_71 : `BYTE_71;
369			`state <= LOAD_MAC1;`
370			`end`
371			`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY:
372			`begin`
373			`radr <= absy_address[31:2];`
374			`radr2LSB <= absy_address[1:0];`
375			load_what <= m16 ? `HALF_70 : `BYTE_70;
376			`state <= LOAD_MAC1;`
377			`end`
378	20	robfinch	`LDX_ABSY:
379			`begin`
380			`radr <= absy_address[31:2];`
381			`radr2LSB <= absy_address[1:0];`
382	38	robfinch	load_what <= xb16 ? `HALF_71 : `BYTE_71;
383	21	robfinch	`state <= LOAD_MAC1;`
384	20	robfinch	`end`
385			`STA_ABSY:
386			`begin`
387			`wadr <= absy_address[31:2];`
388			`wadr2LSB <= absy_address[1:0];`
389	38	robfinch	store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
390	20	robfinch	`state <= STORE1;`
391			`end`
392	38	robfinch	`ifdef SUPPORT_816
393			`// Handle d,sp`
394			`LDA_DSP:
395			`begin`
396			`radr <= dsp_address[31:2];`
397			`radr2LSB <= dsp_address[1:0];`
398			load_what <= m16 ? `HALF_71 : `BYTE_71;
399			`state <= LOAD_MAC1;`
400			`end`
401			`ADC_DSP,`SBC_DSP,`CMP_DSP,`ORA_DSP,`AND_DSP,`EOR_DSP:
402			`begin`
403			`radr <= dsp_address[31:2];`
404			`radr2LSB <= dsp_address[1:0];`
405			load_what <= m16 ? `HALF_70 : `BYTE_70;
406			`state <= LOAD_MAC1;`
407			`end`
408			`STA_DSP:
409			`begin`
410			`wadr <= dsp_address[31:2];`
411			`wadr2LSB <= dsp_address[1:0];`
412			store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
413			`state <= STORE1;`
414			`end`
415			`// Handle (d,sp),y`
416			`ADC_DSPIY,`SBC_DSPIY,`CMP_DSPIY,`ORA_DSPIY,`AND_DSPIY,`EOR_DSPIY,`LDA_DSPIY,`STA_DSPIY:
417			`begin`
418			`radr <= dsp_address[31:2];`
419			`radr2LSB <= dsp_address[1:0];`
420			isIY <= `TRUE;
421			load_what <= `IA_70;
422			`state <= LOAD_MAC1;`
423			`end`
424			`// Handle [zp],y`
425			`ADC_IYL,`SBC_IYL,`AND_IYL,`ORA_IYL,`EOR_IYL,`CMP_IYL,`LDA_IYL,`STA_IYL:
426			`begin`
427			`radr <= zp_address[31:2];`
428			`radr2LSB <= zp_address[1:0];`
429			isIY24 <= `TRUE;
430			load_what <= `IA_70;
431			`state <= LOAD_MAC1;`
432			`end`
433			`// Handle al`
434			`LDA_AL:
435			`begin`
436			`radr <= al_address[31:2];`
437			`radr2LSB <= al_address[1:0];`
438			load_what <= m16 ? `HALF_71 : `BYTE_71;
439			`state <= LOAD_MAC1;`
440			`end`
441			`ADC_AL,`SBC_AL,`AND_AL,`ORA_AL,`EOR_AL,`CMP_AL:
442			`begin`
443			`radr <= al_address[31:2];`
444			`radr2LSB <= al_address[1:0];`
445			load_what <= m16 ? `HALF_70 : `BYTE_70;
446			`state <= LOAD_MAC1;`
447			`end`
448			`STA_AL:
449			`begin`
450			`wadr <= al_address[31:2];`
451			`wadr2LSB <= al_address[1:0];`
452			store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
453			`state <= STORE1;`
454			`end`
455			`// Handle alx`
456			`LDA_ALX:
457			`begin`
458			`radr <= alx_address[31:2];`
459			`radr2LSB <= alx_address[1:0];`
460			load_what <= m16 ? `HALF_71 : `BYTE_71;
461			`state <= LOAD_MAC1;`
462			`end`
463			`ADC_ALX,`SBC_ALX,`AND_ALX,`ORA_ALX,`EOR_ALX,`CMP_ALX:
464			`begin`
465			`radr <= alx_address[31:2];`
466			`radr2LSB <= alx_address[1:0];`
467			load_what <= m16 ? `HALF_70 : `BYTE_70;
468			`state <= LOAD_MAC1;`
469			`end`
470			`STA_ALX:
471			`begin`
472			`wadr <= alx_address[31:2];`
473			`wadr2LSB <= alx_address[1:0];`
474			store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
475			`state <= STORE1;`
476			`end`
477			`// Handle [zp]`
478			`ADC_IL,`SBC_IL,`AND_IL,`ORA_IL,`EOR_IL,`CMP_IL,`LDA_IL,`STA_IL:
479			`begin`
480			isI24 <= `TRUE;
481			`radr <= zp_address[31:2];`
482			`radr2LSB <= zp_address[1:0];`
483			load_what <= `IA_70;
484			`state <= LOAD_MAC1;`
485			`end`
486			`endif
487	20	robfinch	`// Handle (zp)`
488	38	robfinch	`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I,`PEI:
489	20	robfinch	`begin`
490			`radr <= zp_address[31:2];`
491			`radr2LSB <= zp_address[1:0];`
492	21	robfinch	load_what <= `IA_70;
493			`state <= LOAD_MAC1;`
494	20	robfinch	`end`
495			`BRK:
496			`begin`
497	38	robfinch	`set_sp();`
498			store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
499	32	robfinch	`state <= STORE1;`
500			`bf <= !hwi;`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_decode.v] - Blame information for rev 38