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robfinch |
// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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BYTE_IFETCH:
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begin
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vect <= `BYTE_IRQ_VECT;
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suppress_pcinc <= 4'hF; // default: no suppression of increment
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opc <= pc;
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hwi <= `FALSE;
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isBusErr <= `FALSE;
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pg2 <= `FALSE;
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store_what <= `STW_DEF;
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if (nmi_edge & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
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ir[7:0] <= `BRK;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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hwi <= `TRUE;
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if (nmoi) begin
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vect <= `NMI_VECT;
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state <= DECODE;
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end
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else begin
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vect <= `BYTE_NMI_VECT;
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state <= BYTE_DECODE;
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end
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end
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else if (irq_i & gie) begin
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wai <= 1'b0;
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if (im) begin
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if (unCachedInsn) begin
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if (bhit) begin
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ir <= ibuf;
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state <= BYTE_DECODE;
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end
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else
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state <= LOAD_IBUF1;
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end
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else begin
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if (ihit) begin
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ir <= insn;
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state <= BYTE_DECODE;
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end
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else
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state <= ICACHE1;
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end
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end
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else begin
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ir[7:0] <= `BRK;
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hwi <= `TRUE;
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if (nmoi) begin
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vect <= {vbr[31:9],irq_vect,2'b00};
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state <= DECODE;
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end
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else begin
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state <= BYTE_DECODE;
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end
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end
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end
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else if (!wai) begin
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if (unCachedInsn) begin
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if (bhit) begin
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ir <= ibuf;
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state <= BYTE_DECODE;
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end
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else
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state <= LOAD_IBUF1;
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end
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else begin
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if (ihit) begin
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ir <= insn;
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state <= BYTE_DECODE;
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end
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else
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state <= ICACHE1;
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end
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end
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if (hist_capture) begin
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history_buf[history_ndx] <= pc;
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history_ndx <= history_ndx+7'd1;
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end
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case(ir[7:0])
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`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAS,`TXS: begin sp <= res8[7:0]; end
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`ADC_IMM:
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begin
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acc[7:0] <= df ? bcaio : res8;
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cf <= df ? bcaico : resc8;
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// vf <= resv8;
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vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
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nf <= df ? bcaio[7] : resn8;
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zf <= df ? bcaio==8'h00 : resz8;
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end
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`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I:
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begin
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acc[7:0] <= df ? bcao : res8;
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cf <= df ? bcaco : resc8;
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vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
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nf <= df ? bcao[7] : resn8;
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zf <= df ? bcao==8'h00 : resz8;
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end
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`SBC_IMM:
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begin
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acc[7:0] <= df ? bcsio : res8;
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cf <= ~(df ? bcsico : resc8);
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vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
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nf <= df ? bcsio[7] : resn8;
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zf <= df ? bcsio==8'h00 : resz8;
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end
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`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I:
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begin
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acc[7:0] <= df ? bcso : res8;
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vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
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cf <= ~(df ? bcsco : resc8);
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nf <= df ? bcso[7] : resn8;
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zf <= df ? bcso==8'h00 : resz8;
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end
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`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,
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`CPX_IMM,`CPX_ZP,`CPX_ABS,
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`CPY_IMM,`CPY_ZP,`CPY_ABS:
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begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
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`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
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begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end
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`TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
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begin zf <= resz8; end
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`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,
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`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,
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`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,
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`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I:
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begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`ASL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`LSR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn8; zf <= resz8; end
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`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn8; zf <= resz8; end
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`PLA: begin acc[7:0] <= res8; zf <= resz8; nf <= resn8; end
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`PLX: begin x[7:0] <= res8; zf <= resz8; nf <= resn8; end
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`PLY: begin y[7:0] <= res8; zf <= resz8; nf <= resn8; end
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`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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endcase
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end
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