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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_ix.v] - Blame information for rev 10

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Line No. Rev Author Line
1 10 robfinch 
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@opencores.org
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
23 5 robfinch 
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
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BYTE_IX1:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hf;
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                adr_o <= {radr,2'b00};
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                state <= BYTE_IX2;
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        end
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        else if (dhit) begin
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                radr <= radr34p1[33:2];
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                radr2LSB <= radr34p1[1:0];
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                ia[7:0] <= rdat8;
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                state <= BYTE_IX3;
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        end
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        else
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                dmiss <= `TRUE;
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BYTE_IX2:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                ia[7:0] <= dati;
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                radr <= radr34p1[33:2];
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                radr2LSB <= radr34p1[1:0];
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                state <= BYTE_IX3;
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        end
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BYTE_IX3:
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        if (unCachedData) begin
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                cyc_o <= 1'b1;
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                stb_o <= 1'b1;
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                sel_o <= 4'hf;
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                adr_o <= {radr,2'b00};
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                state <= BYTE_IX4;
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        end
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        else if (dhit) begin
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                ia[15:8] <= rdat8;
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                ia[31:16] <= 16'h0000;
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                state <= BYTE_IX5;
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        end
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        else
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                dmiss <= `TRUE;
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BYTE_IX4:
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        if (ack_i) begin
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                cyc_o <= 1'b0;
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                stb_o <= 1'b0;
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                sel_o <= 4'h0;
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                adr_o <= 34'h0;
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                ia[15:8] <= dati;
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                ia[31:16] <= 16'h0000;
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                state <= BYTE_IX5;
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        end
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BYTE_IX5:
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        begin
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                radr <= ia[31:2];
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                radr2LSB <= ia[1:0];
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                state <= LOAD1;
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                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
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                        wadr <= ia[31:2];
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                        wadr2LSB <= ia[1:0];
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                        wdat <= {4{acc8}};
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                        state <= STORE1;
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                end
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        end

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