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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_ix.v] - Blame information for rev 30

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)
BYTE_IX1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hf;
                adr_o <= {radr,2'b00};
                state <= BYTE_IX2;
        end
        else if (dhit) begin
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                ia[7:0] <= rdat8;
                state <= BYTE_IX3;
        end
        else
                dmiss <= `TRUE;
BYTE_IX2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                ia[7:0] <= dati;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IX3;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_IX3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hf;
                adr_o <= {radr,2'b00};
                state <= BYTE_IX4;
        end
        else if (dhit) begin
                ia[15:8] <= rdat8;
                ia[31:16] <= 16'h0000;
                state <= BYTE_IX5;
        end
        else
                dmiss <= `TRUE;
BYTE_IX4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                ia[15:8] <= dati;
                ia[31:16] <= 16'h0000;
                state <= BYTE_IX5;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_IX5:
        begin
                radr <= ia[31:2];
                radr2LSB <= ia[1:0];
                state <= LOAD1;
                if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
                        wadr <= ia[31:2];
                        wadr2LSB <= ia[1:0];
                        wdat <= {4{acc8}};
                        state <= STORE1;
                end
        end

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Indirect and indirect X addressing mode eg. LDA ($12,x) : (zp)`
24			`BYTE_IX1:`
25			`if (unCachedData) begin`
26			`cyc_o <= 1'b1;`
27			`stb_o <= 1'b1;`
28			`sel_o <= 4'hf;`
29			`adr_o <= {radr,2'b00};`
30			`state <= BYTE_IX2;`
31			`end`
32			`else if (dhit) begin`
33			`radr <= radr34p1[33:2];`
34			`radr2LSB <= radr34p1[1:0];`
35			`ia[7:0] <= rdat8;`
36			`state <= BYTE_IX3;`
37			`end`
38			`else`
39			dmiss <= `TRUE;
40			`BYTE_IX2:`
41			`if (ack_i) begin`
42			`cyc_o <= 1'b0;`
43			`stb_o <= 1'b0;`
44			`sel_o <= 4'h0;`
45			`adr_o <= 34'h0;`
46			`ia[7:0] <= dati;`
47			`radr <= radr34p1[33:2];`
48			`radr2LSB <= radr34p1[1:0];`
49			`state <= BYTE_IX3;`
50			`end`
51	21	robfinch	`else if (err_i) begin`
52			`lock_o <= 1'b0;`
53			`cyc_o <= 1'b0;`
54			`stb_o <= 1'b0;`
55			`we_o <= 1'b0;`
56			`sel_o <= 4'h0;`
57			`adr_o <= 34'h0;`
58			`dat_o <= 32'h0;`
59			`state <= BUS_ERROR;`
60			`end`
61	5	robfinch	`BYTE_IX3:`
62			`if (unCachedData) begin`
63			`cyc_o <= 1'b1;`
64			`stb_o <= 1'b1;`
65			`sel_o <= 4'hf;`
66			`adr_o <= {radr,2'b00};`
67			`state <= BYTE_IX4;`
68			`end`
69			`else if (dhit) begin`
70			`ia[15:8] <= rdat8;`
71			`ia[31:16] <= 16'h0000;`
72			`state <= BYTE_IX5;`
73			`end`
74			`else`
75			dmiss <= `TRUE;
76			`BYTE_IX4:`
77			`if (ack_i) begin`
78			`cyc_o <= 1'b0;`
79			`stb_o <= 1'b0;`
80			`sel_o <= 4'h0;`
81			`adr_o <= 34'h0;`
82			`ia[15:8] <= dati;`
83			`ia[31:16] <= 16'h0000;`
84			`state <= BYTE_IX5;`
85			`end`
86	21	robfinch	`else if (err_i) begin`
87			`lock_o <= 1'b0;`
88			`cyc_o <= 1'b0;`
89			`stb_o <= 1'b0;`
90			`we_o <= 1'b0;`
91			`sel_o <= 4'h0;`
92			`adr_o <= 34'h0;`
93			`dat_o <= 32'h0;`
94			`state <= BUS_ERROR;`
95			`end`
96	5	robfinch	`BYTE_IX5:`
97			`begin`
98			`radr <= ia[31:2];`
99			`radr2LSB <= ia[1:0];`
100			`state <= LOAD1;`
101			if (ir[7:0]==`STA_IX \|\| ir[7:0]==`STA_I) begin
102			`wadr <= ia[31:2];`
103			`wadr2LSB <= ia[1:0];`
104			`wdat <= {4{acc8}};`
105			`state <= STORE1;`
106			`end`
107			`end`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_ix.v] - Blame information for rev 30