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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_iy.v] - Blame information for rev 25

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// ============================================================================
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@opencores.org
//       ||
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
//
// Indirect Y addressing mode eg. LDA ($12),y
BYTE_IY1:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hf;
                adr_o <= {radr,2'b00};
                state <= BYTE_IY2;
        end
        else if (dhit) begin
                ia[7:0] <= rdat8;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IY3;
        end
        else
                dmiss <= `TRUE;
BYTE_IY2:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                ia[7:0] <= dati;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IY3;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_IY3:
        if (unCachedData) begin
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hf;
                adr_o <= {radr,2'b00};
                state <= BYTE_IY4;
        end
        else if (dhit) begin
                ia[15:8] <= rdat8;
                ia[31:16] <= 16'h0000;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IY5;
        end
        else
                dmiss <= `TRUE;
BYTE_IY4:
        if (ack_i) begin
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                ia[15:8] <= dati;
                ia[31:16] <= 16'h0000;
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IY5;
        end
        else if (err_i) begin
                lock_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                dat_o <= 32'h0;
                state <= BUS_ERROR;
        end
BYTE_IY5:
        begin
                radr <= iapy8[31:2];
                radr2LSB <= iapy8[1:0];
                $display("IY addr: %h", iapy8);
                if (ir[7:0]==`STA_IY) begin
                        wadr <= iapy8[31:2];
                        wadr2LSB <= iapy8[1:0];
                        wdat <= {4{acc8}};
                        state <= STORE1;
                end
                else
                        state <= LOAD1;
        end
 

Line No.	Rev	Author	Line
1	10	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2013 Robert Finch, Stratford`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@opencores.org`
6			`// \|\|`
7			`//`
8			`// This source file is free software: you can redistribute it and/or modify`
9			`// it under the terms of the GNU Lesser General Public License as published`
10			`// by the Free Software Foundation, either version 3 of the License, or`
11			`// (at your option) any later version.`
12			`//`
13			`// This source file is distributed in the hope that it will be useful,`
14			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`// GNU General Public License for more details.`
17			`//`
18			`// You should have received a copy of the GNU General Public License`
19			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
20			`//`
21			`// ============================================================================`
22			`//`
23	5	robfinch	`// Indirect Y addressing mode eg. LDA ($12),y`
24			`BYTE_IY1:`
25			`if (unCachedData) begin`
26			`cyc_o <= 1'b1;`
27			`stb_o <= 1'b1;`
28			`sel_o <= 4'hf;`
29			`adr_o <= {radr,2'b00};`
30			`state <= BYTE_IY2;`
31			`end`
32			`else if (dhit) begin`
33			`ia[7:0] <= rdat8;`
34			`radr <= radr34p1[33:2];`
35			`radr2LSB <= radr34p1[1:0];`
36			`state <= BYTE_IY3;`
37			`end`
38			`else`
39			dmiss <= `TRUE;
40			`BYTE_IY2:`
41			`if (ack_i) begin`
42			`cyc_o <= 1'b0;`
43			`stb_o <= 1'b0;`
44			`sel_o <= 4'h0;`
45			`adr_o <= 34'h0;`
46			`ia[7:0] <= dati;`
47			`radr <= radr34p1[33:2];`
48			`radr2LSB <= radr34p1[1:0];`
49			`state <= BYTE_IY3;`
50			`end`
51	21	robfinch	`else if (err_i) begin`
52			`lock_o <= 1'b0;`
53			`cyc_o <= 1'b0;`
54			`stb_o <= 1'b0;`
55			`we_o <= 1'b0;`
56			`sel_o <= 4'h0;`
57			`adr_o <= 34'h0;`
58			`dat_o <= 32'h0;`
59			`state <= BUS_ERROR;`
60			`end`
61	5	robfinch	`BYTE_IY3:`
62			`if (unCachedData) begin`
63			`cyc_o <= 1'b1;`
64			`stb_o <= 1'b1;`
65			`sel_o <= 4'hf;`
66			`adr_o <= {radr,2'b00};`
67			`state <= BYTE_IY4;`
68			`end`
69			`else if (dhit) begin`
70			`ia[15:8] <= rdat8;`
71			`ia[31:16] <= 16'h0000;`
72			`radr <= radr34p1[33:2];`
73			`radr2LSB <= radr34p1[1:0];`
74			`state <= BYTE_IY5;`
75			`end`
76			`else`
77			dmiss <= `TRUE;
78			`BYTE_IY4:`
79			`if (ack_i) begin`
80			`cyc_o <= 1'b0;`
81			`stb_o <= 1'b0;`
82			`sel_o <= 4'h0;`
83			`adr_o <= 34'h0;`
84			`ia[15:8] <= dati;`
85			`ia[31:16] <= 16'h0000;`
86			`radr <= radr34p1[33:2];`
87			`radr2LSB <= radr34p1[1:0];`
88			`state <= BYTE_IY5;`
89			`end`
90	21	robfinch	`else if (err_i) begin`
91			`lock_o <= 1'b0;`
92			`cyc_o <= 1'b0;`
93			`stb_o <= 1'b0;`
94			`we_o <= 1'b0;`
95			`sel_o <= 4'h0;`
96			`adr_o <= 34'h0;`
97			`dat_o <= 32'h0;`
98			`state <= BUS_ERROR;`
99			`end`
100	5	robfinch	`BYTE_IY5:`
101			`begin`
102			`radr <= iapy8[31:2];`
103			`radr2LSB <= iapy8[1:0];`
104			`$display("IY addr: %h", iapy8);`
105	20	robfinch	if (ir[7:0]==`STA_IY) begin
106	5	robfinch	`wadr <= iapy8[31:2];`
107			`wadr2LSB <= iapy8[1:0];`
108			`wdat <= {4{acc8}};`
109			`state <= STORE1;`
110			`end`
111			`else`
112			`state <= LOAD1;`
113			`end`
114

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_iy.v] - Blame information for rev 25